JPH01222524A - Coding device - Google Patents

Abstract

PURPOSE:To attain high speed coding and to obtain high general purpose applica tion by storing the result of coding operation required including feedback processing of a quantized error into a memory and having only to read the data from the address designated by an input data so as to attain coding. CONSTITUTION:A quantized error feedback outputted from a D flip-flop 35 is added to a sampling value Xi inputted from an input terminal 30 by an adder 31 and fed to a limiter 32. The limiter 32 clips the correction value depending on the carry and the code of the quantized error feedback value of the adder 31. A ROM 33 outputs a prediction difference coding code Yi to an output terminal 34 according to an address signal comprising the input sampling value and the prediction value Xi, a local decoding value Xi is outputted to the D flip-flop 36 to output the quantized error feedback to the D flip-flop 35. Thus, high speed coding is applied and high general purpose application is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an encoding device, and particularly to an encoding device in a system for transmitting a so-called predictive encoding code.

(Prior Art and its Problems) When digitally transmitting information such as images and audio, various encoding methods have been proposed in order to reduce the amount of data to be transmitted. One method is predictive differential coding (hereinafter referred to as DPCM), which aims to compress the amount of information by utilizing the correlation between adjacent sample values. As is well known, in DPCM, an encoded sample value is decoded, the decoded value is used to obtain a predicted value for the next sample value to be encoded, and the error between this predicted value and the actual sample value is quantized. It is encoded using

FIG. 3 is a diagram showing an example of the configuration of a DPCM encoding device using the simplest prior value prediction. The sample value Xi input to the input terminal 10 is applied to a subtracter 12, from which a predicted value (previous value decoded value in this example), which will be described later, is subtracted therefrom. The quantizer 14 quantizes the difference value output from the subtracter 12, encodes it as a DPCM code Y by the encoder 26, and outputs it to the output terminal 16.

The output of quantizer 14 is also applied to inverse quantizer 18 .

The inverse quantizer 18 decodes the output of the quantizer 14 into a difference value and applies it to the adder 20 . In the adder 20, the subtracter 12
The difference value is then added to the previous value predicted value applied to the sample value, thereby restoring the difference value to the sample value. The limiter 22 limits the amplitude of the output of the adder 20 to a predetermined range and supplies it to a D-type flip-flop 24 . The signal is supplied to a D-type flip-flop 24. The output of the D-type flip-flop 24 becomes a predicted value for the next sample value and is supplied to the subtracter 12 and the adder 20.

Generally, the distribution of difference values from previous predicted values is biased toward small values, and by encoding and transmitting the difference values, compressed transmission of information becomes possible.

FIG. 4 shows an example of an encoding device in which a filter (hereinafter referred to as a noise shaping filter) that multiplies the quantization error by a coefficient k (k<1) and feeds it back to the input end is added to the encoding device shown in FIG. 3. FIG. 3 is a diagram showing the configuration. In the figure, the same components as those in FIG. 3 are given the same numbers, and their explanations are omitted.

In FIG. 4, the sample value X8 input to the input terminal 10
is applied to the subtracter 50 and the D-type flip-flop 64
The difference between the output quantization error feedback value and the output quantization error feedback value is calculated.

The limiter 52 limits the data to the maximum value (or minimum value) when the data overflows (or underflows) in the subtracter 50, and the data passed through the limiter 52 becomes the corrected sample value Xi. .

This corrected sample value xi° is subtracted from the predicted value by a subtracter 12, and is supplied to a quantizer 14, a determination circuit 56, and a subtracter 54. The subtracter 54 calculates the difference between the prediction error (difference value) ei and the quantized prediction error R3, and inputs the difference to the a terminal of the switch 58.

The switch 58 selectively outputs the quantization error Q(et') or "0" according to the determination result of the determination circuit 56.

The determination circuit 56 is based on the prediction error ei, for example, 1e=l
When <'rh (Th is a threshold value), the switch 58 is controlled so that the input of the a terminal, that is, the quantization error Q(e,') is supplied to the coefficient circuit 60. The output of the switch 58 is multiplied by a coefficient k in a coefficient circuit 60, supplied to a D-type flip-flop 64, and used to correct the next sample value X1.1.

However, when handling a signal with a high sampling frequency such as an HDTV (high-definition) signal, even if a high-speed logic IC is used, the DPCM loop (from the input to the D-type flip-flop 24) is processed within one sampling period. The calculation cannot be completed until the local decoded value that is the input is obtained, and parallel processing has to be performed. For example, when the sampling frequency is 48.0 MIIz, the sampling period is 20.5 ns.

On the other hand, the time required for the calculation of the DPCM loop is about 165 ns even when a high-speed TTL-IC is used as the logic IC and a high-speed FROM is used as the quantizer 14. Here, since 165/20.5=8.05,
The number of parallel processing will be 9. That is, nine identical circuits are required. Furthermore, when performing complex processing such as feeding back quantization errors to the input side to correct encoded input values as shown in FIG. 4, the number of parallel processing increases further. Furthermore, if parallel processing is adopted, in the above numerical example, a circuit that divides the signal into nine phases and a circuit that multiplexes the nine divided signals will also be required, which will complicate the hardware configuration and increase the scale. It becomes something extremely large.

In addition, in the configuration shown in Figure 3, in order to suppress the locally decoded value within a predetermined range and to effectively use the dynamic range of the input sample value, a sign judgment type quantizer (two difference If there is a change in the algorithm, such as changing the quantizer to a quantizer that allocates values and takes the decoded value within the normal range as the true difference value, the hardware must be fundamentally changed. However, such changes were extremely difficult.

(Objective of the Invention) In view of the above-mentioned background, the present invention provides a highly versatile code that can perform high-speed encoding including processing to feed back quantization errors to the input side and correct the encoded human input values. The purpose is to provide a device for converting

(Structure of the Invention) In order to achieve this objective, the encoding device of the present invention inputs a sample value and its predicted value and generates an encoded code.

a memory that stores data related to local decoded values and quantization errors of the encoded code and reads out the data with respect to the input; and feedback means that feeds back the local decoded values from the memory to the input side of the memory; The apparatus is configured to include means for correcting the sample value based on data related to the quantization error.

(Function) With this configuration, the results of necessary encoding operations, including the feedback processing of the quantization error, are stored in the memory, and the data can be encoded simply by reading the data from the address specified by the input data. can be realized, so the calculation is performed and encoded using a separate calculation circuit.

Encoded codes can be obtained much faster than when decoding is performed.

Further, even when changing the algorithm, it can be realized by an extremely simple operation such as replacing the memory.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the main part configuration of an encoding device as an embodiment of the present invention. In the figure, 30 is a terminal to which an n (in this example, 8) bit sample value X is input; 31 is an adder for correcting the input sample value X with a quantization error feedback value;
32 is a limiter for preventing overflow and underflow of calculations by the adder 31; 33 is a ROM;
34 is the output terminal of the m (4 in this example) bit encoding code Y1, 35 is a D-type flip-flop for feeding back the quantization error feedback value to the next input sample value, and 36 is the output terminal for the locally decoded value to the next input sample value. This is a D-type flip-flop for feeding back as a predicted value.

A quantization error feedback value outputted from a D-type flip-flop 35 is added to the five sample values inputted from the input terminal 30 by an adder 31, and the added values are supplied to a limiter 32. The limiter 32 determines overflow and underflow based on the sign of the carry and quantization error feedback values of the adder 31, and in the case of overflow, a predetermined maximum value (for example, 255) is set, and in the case of underflow, a predetermined minimum value ( For example, clip the correction value to 0). The corrected input sample values X, l and the 8-bit predicted value Xi output from the D-type flip-flop 36 are supplied to the address input of the ROM 33.

That is, the 8-bit input sample value Xi and the 8-bit predicted value X
, becomes a 16-bit address signal for the ROM 33.

The ROM 33 outputs the DPCM code Y to the output terminal 34 according to the address signal consisting of the input sample value XL and the predicted value 75.
, and outputs the locally decoded value Y to the D-type flip-flop 36.
1, and outputs a quantization error feedback value to the D-type flip-flop 35. That is, the ROM 33 of the embodiment of FIG.
fulfills the function indicated by the broken line 62 in FIG. The time required for this output is one read cycle time of the ROM 33, which is extremely short. Therefore, the number of parallel processes can be reduced compared to when a similar circuit is constructed using conventional logic ICs.

Furthermore, since the broken line portion 62 in FIG. 4 is replaced with the ROM 33, the number of ICs in each parallel processing section can also be reduced. Therefore, the number of ICs in the entire device can be significantly reduced, and the amount of hardware can be made extremely small.

In addition, in this embodiment, as long as the input/output characteristics are known and the encoding operation is known, any complex algorithm can be processed by simply replacing (or switching) the ROM as long as the number of manual bits and the number of output bits are the same. However, it is possible to realize it with the same circuit configuration. For example, in the process shown in FIG. 4, it is possible to change the algorithm to include adaptive processing such as changing the coefficient k of the coefficient circuit 60 in accordance with the prediction error e1 instead of the determination circuit 56 and switch 58. Furthermore, even if there is a change in the number of input bits or the number of output bits, a ROM suitable for the change may be prepared and the design may be changed in accordance with the bit width of the signal path. In other words, the encoding device of this embodiment is very easy to change the algorithm described below, and has high versatility.

FIG. 2 is a diagram showing a schematic configuration of an example of a decoding device corresponding to the encoding device of FIG. 1. In the figure, 40 is a terminal to which the transmitted DPCM code Y is input, 42 is a ROM constituting a decoding table, and the DPCM code Yi and a predicted value value described later are input to the address input thereof.

The decoded value output from the ROM 42 is also applied to a D-type flip-flop 46. The output of the D-type flip-flop 46 is applied to the ROM 42 as the predicted value X.

In this case as well, the cycle time of the ROM42 is 35ns.
Since the number of parallel processes is reduced significantly, the amount of hardware can be reduced.

The table in this ROM 42 is determined corresponding to the ROM 33 on the transmitting side.

Note that although the above embodiments have been explained by taking the prior value prediction DPCM as an example, the present invention is not limited to this, and can of course be applied to encoding devices using DPCM that perform predictions such as two-dimensional prediction, three-dimensional prediction, and adaptive prediction. Furthermore, it is also applicable to encoding devices with arbitrary code lengths in addition to these.

(Effects of the Invention) As described above, according to the present invention, an encoding device capable of extremely high-speed encoding can be obtained, and accordingly, the hardware of the entire device can be kept small.

In addition, since the encoding calculation process can be changed relatively easily, the same circuit can be used for a variety of purposes.
We were able to build an extremely versatile system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of an encoding device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a schematic configuration of a decoding device corresponding to the encoding device of FIG. 1, and FIG. Block diagram showing a schematic configuration of a conventional DPCM encoding device, No. 4
The figure is a block diagram showing the configuration of a conventional encoding device that performs processing to feed back quantization errors. lO...Input terminal, 12...Subtractor, 14...
・Quantizer, 16... Output terminal, 18... Inverse quantizer, 20... Adder, 22... Limiter,
24... D-type flip-flop, 26... Encoder, 30... Input terminal, 31... Adder, 32
...Limiter, 33...ROM. 34...Output terminal, 35.36...D-type flip-flop, 40...Reception input terminal, 42...R
OM (decoding table), 44...reception output terminal,
46...D type flip-flop, 50.54...
- Subtractor, 52... Limiter, 56... Judgment circuit, 58... Switch, 60... Coefficient circuit, 6
2...Function corresponding to ROM33, 64...D type flip-flop. Patent applicant International Telegraph and Telephone Corporation

Claims (1)

[Claims] A memory that receives sample values and predicted values thereof as input, stores encoded codes, local decoded values, and data related to quantization errors of the encoded codes, and reads out the data in response to the input, and local decoding from the memory. An encoding device comprising: feedback means for feeding back a value to the input side of the memory; and means for correcting the sample value based on data related to the quantization error.