JPH01220861A - Manufacture of photo electronic integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an integrated circuit with excellent high frequency characteristics by a method wherein, after epitaxial growth for a photo diode (PD) is performed on the whole surface of an InP substrate, unnecessary parts are eliminated, an FET is formed on an N-type GaInAs layer in a region for forming the field effect transistor(FET), and the PD and the FET are electrically isolated. CONSTITUTION:On an InP substrate 1, the following are epitaxially grown in order; a GaInAs layer 2, an N-type AlInAs layer 3, an N-type GaInAs layer 4, a GaInAs layer 5 to which impurity is not added, and a P-type GaInAs layer 6. A region where a P-type electrode is to be formed in a region where the PD is to be formed is left, and the layer 6 and the layer 5 are eliminated, to expose the layer 4. An anode electrode 10 of the PD is formed on the P-type GaInAs layer 6, and a cathode electrode 7 of the PD is formed on the layer 4 in the PD forming region. A source electrode 8 and a drain electrode 9 are formed on the layer 4 in an FET forming region. Next, the layer 4, the layer 3 and the layer 2 between the region where the PD is to be formed, and the region where the FET is to be formed are etched and eliminated, and both regions are electrically isolated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an optoelectronic integrated circuit (OE IC: 0pto-e) in which semiconductor optical elements and electronic elements are integrated on one substrate.
lectronlc integrated clrc
ult).

[Conventional technology]

As an optoelectronic integrated circuit, ■ After forming a photodiode (PD), which is an optical element, on an InP substrate 1i using the VPE method, a GaAs layer is formed on the InP substrate 1 adjacent to this PD, and an electronic layer is formed on it. A device in which a field effect transistor (FET) is formed (1986 Institute of Electronics, Information and Communication Engineers, Semiconductor Materials Division National Conference, Lecture No. S9-1), ■A recess is formed on the InP substrate 1, and a VPE is placed in this recess. After forming a photodiode (PD) using the FET method,
The PD growth layer in the area to be formed is removed, and then the FET is
(1988 Institute of Electronics, Information and Communication Engineers, Semiconductor Materials Division National Conference, Lecture No. S9-3),
■A junction field effect transistor (J-
After forming an n-type GaInAs layer for FET and an epitaxial growth layer for PD, a p region is formed by Be ion implantation to form PD and J-FET (1988 Institute of Electronics, Information and Communication Engineers, Semiconductor National Materials Division Conference, lecture number S9-2), etc.

[Problem to be solved by the invention]

However, in the first and second methods, unnecessary parts are removed after epitaxial growth for PD, and then FET is grown.
It is necessary to re-grow the epitaxial layer for FETs, which complicates the manufacturing process, making it difficult to obtain high-purity crystals during re-growth, making it difficult to reproducibly obtain FETs with good characteristics. There was a problem.

Furthermore, in the third method, the manufacturing process is complicated in that a Be ion implantation process and an annealing process are required to form the p region. Furthermore, there is a problem in that the wafer is warped due to the annealing process, resulting in a decrease in the precision of lithography used in subsequent processes. Moreover,
In this third method, J
-FET must be used as FET.

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, the method for manufacturing an optoelectronic integrated circuit of the present invention includes a GaInAs layer and an n-type A layer on an InP substrate.
, a step of sequentially forming a QInAs layer, an n-type GaInAs layer, an impurity-free GaInAs layer, and an n-type GaInAs layer or a p-type InP layer by epitaxial growth, and a plan to form a p-electrode in a region where a photodiode is to be formed. a step of removing the n-type Ga InAs layer or the p-type InP layer and the impurity-free Ga InAs layer leaving a region to expose the n-type Ga InAs layer; and forming the photodiode on the n-type Ga InAs layer. At the same time, a cathode electrode is formed on the n-type Ga I nAs layer in the photodiode formation region, and a cathode electrode is formed on the n-type Ga I nAs layer in the field effect transistor formation region.
A step of forming a source electrode and a drain electrode on the nAs layer, and an nI layer between the region where the photodiode is to be formed and the region where the field effect transistor is to be formed.
JIGalnAs layer, n-type/jllnAs layer, Ga I
a step of etching away the nAs layer to electrically isolate the two; and a step of etching the nAs layer between the source electrode and the drain electrode in the region where the field effect transistor is to be formed.
This process includes the steps of etching away the As layer to expose the n-type AfI nAs layer, and forming a gate electrode in this exposed portion.

[Effect]

The minimum number of times of epitaxial growth is one, and there is no need to perform regrowth. Also, there is no ion implantation or annealing process. Furthermore, recessed high electron mobility transistors (HEMT:
Hlgh Electron MoblrltyTr
An opto-electronic integrated circuit can be obtained in which an electronic device (Anslstor) is mounted as an electronic element.

[Example] FIG. 1 is a process sectional view showing an example of the present invention. Note that the dimensional ratios in the drawings do not necessarily match the description.

On the Fe-doped InP substrate 1, for example, the substrate temperature is 600.
℃ and a pressure of 60 Torr, the Ga I nA+q layer 2 was converted to about 0.1 μm Sn type A using trimethylindium, triethyl gallium, arsine and phosphine.
llInAs layer 3 at about 300A.

The n-type Ga 1 nAs layer 4 is formed to have a thickness of approximately 2000 Å, and the impurity-free Ga In As layer 5 is formed to a thickness of 1 to 2 ttmsp type impurity-doped Ga In As layer 6 is formed to a thickness of 0.2 μm (FIG. (A)).

Next, the p-electrode formation region of the photodiode (PD) section 12 is masked by a known etching method, and
p-type Ga I nAs layer 6 and impurity-free Ga I
The nAs layer 5 is sequentially etched away from the surface to form an n-type G
a I nAs layer 4 is exposed.

Then, the p-type GaInA remaining as the p-electrode layer of the PD
On the s layer 6, a p-type ohmic electrode 1 made of AuZn etc.
0 and further exposed n-type Ga I nAsA
N-type ohmic electrode made of uGe on s interlayer 7.8.9
is deposited and alloyed at 350°C for 1 minute. The p-type ohmic electrode 10 becomes the anode electrode of a PD formed in the PD section 12, and the n-type ohmic electrode 7 becomes its cathode electrode. Further, the n-type ohmic electrodes 8 and 9 become the source electrode and drain electrode of the FET formed in the FET section 13, respectively (FIG. (B)).

Next, in order to electrically isolate the PD section 12 and the FET section 13, the n-type GaInAs layer 4, the n-type AjllnAs layer 3, and the GaInAs layer 2 are removed by etching (Fig.
)) Subsequently, the n-type GaInAs layer 4 in the gate electrode formation area of the FET section 13 is removed to form an n-type A, 17
The 1nAs layer 3 is exposed, and the gate electrode 11 is placed on the exposed part.
For example, Ti/Pt/Au are formed by a sequential vapor deposition method (Figure (D)).

Through the above steps, a PIN photodiode is formed in the PD section 12, a HEMT with a recessed structure is formed in the FET section 13, and finally, necessary wiring is performed.

As described above, since p-type impurities are added to the p-electrode layer of the PD during epitaxial growth, a diffusion/ion implantation process for forming the p-electrode layer is not necessary. Also,
The n-type Ga InAs layer of the HEMT and the n-type Ga InAs layer of the PD have been made common.

As is well known, a HEMT with a recessed structure can easily reduce the source resistance, and has extremely good high frequency characteristics such as a cutoff frequency fr of 20 GHz or more.

According to this embodiment, for example, the PD light receiving diameter is 50 μmφ,
With a FET gate length of 1 μm, a PS prototype optoelectronic integrated circuit that exhibits good response even to IG optical signals can be manufactured with good reproducibility.

In this example, p-type Ga I is used as the p region of the PD.
Although the nAs layer 6 is used, p-type InP is used instead.
Layers may also be used. In that case, a p-type InP layer may be epitaxially grown in place of the p-type GaInAs layer 6 at the stage shown in FIG. 1(A).

Furthermore, InP substrate 1 and Ga InAs layer 2 have In
A buffer layer made of P,AN InAs layer is provided,
A spacer layer may be provided between the GaInAs layer 2 and the n-type AjllnAs layer 3.

〔Effect of the invention〕

As described above, according to the method for manufacturing an optoelectronic integrated circuit of the present invention, the epitaxial growth step is performed only once, and there is no need to perform regrowth, so that high-purity crystals can be obtained with good reproducibility. Furthermore, since there is no ion implantation or annealing process, the wafer does not warp during the process, and lithography processing can be performed with high precision. Furthermore, since a recessed high electron mobility transistor is formed as an electronic element, an optoelectronic integrated circuit with excellent high frequency characteristics can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment of the present invention. 1-・-1n P substrate, 2-QalnAs layer, 3-0-
n-type AfilnAs layer, 4-n-type GaInAs layer, 5
... Impurity-free GaInAs layer, 6, p-type G
a I nAs layer, 7... Cathode electrode, 8... Source electrode, 9... Drain electrode, 10... Anode electrode, 11... Gate electrode, 12... PD section, 13
...FET department. Patent applicant: Sumitomo Electric Industries, Ltd. Representative patent attorney Yoshiki Hase
Salt 1) Process of Tatsuya Example (first half) Figure 1

Claims (1)

[Claims] GaInAs layer, n-type AlInAs layer, n-type GaInAs layer, impurity-free G on an InP substrate.
aInAs layer and p-type GaInAs layer or p-type I
A process of sequentially forming nP layers by epitaxial growth, and removing the p-type GaInAs layer or the p-type InP layer and the impurity-free GaInAs layer, leaving the p-electrode formation area in the photodiode formation area, and removing the n-type GaInAs layer.
forming an anode electrode of the photodiode on the p-type GaInAs layer and forming a cathode electrode on the n-type GaInAs layer in the photodiode formation region; a step of forming a source electrode and a drain electrode on the n-type GaInAs layer of the n-type GaInAs layer, an n-type AlInAs layer, and a GaInAs layer between the photodiode formation area and the field effect transistor formation area; etching away the n-type GaInAs layer between the source electrode and the drain electrode in the area where the field effect transistor is to be formed to expose the n-type AlInAs layer; and forming a gate electrode.