JPH01218208A - Staircase wave generating circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit by providing a logical gate circuit corresponding to respective plural switch elements to output alternatively plural divided voltages formed by a resistance ladder. CONSTITUTION:In a staircase wave generating circuit, when a staircase wave approximate to a sine wave is formed, outputs Q4-Q1 of a counter circuit COUNT is 0000 and a switch S4 is turned on, a fourth divided voltage is outputted from the maximum value corresponding to a switch S1. Consequently, to a NAND gate circuit corresponding to the switch S4, an output, the inerse of Q4 of the most significant bit to show the positive half cycle and the signals, the inverse of A and B through inverter circuits N7 and N8 is supplied. For this reason, at the time of a timing T1, the switch S4 can be turned on by the 00 of the signals A and B corresponding to the 0000 of counting outputs Q4-Q1. Thus, the output signal outputted through switches S1-S8 is outputted through an arithmetic circuit OP made into a voltage follower mode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a staircase wave generation circuit, and relates to a technique that is effective for use in, for example, a dial tone generation circuit in a telephone.

[Conventional technology]

A staircase wave can be formed by decoding the output signal of the counter circuit and selectively outputting the divided voltage formed by the resistor ladder.

Regarding the D/A conversion circuit using such a resistance ladder, for example, see "A/D - D/A Conversion Technology of the Microcomputer Age" published by Nikkan Kogyo Shimbun, November 30, 1980, page 12.
There are pages 1 to 129.

[Problem to be solved by the invention]

If the output digital signal of the counter circuit is decoded as described above, the circuit scale will become large.

Therefore, the inventor of the present application focused on the fact that when an AC staircase wave is formed, the waveform of the staircase wave is symmetrical in both positive and negative polarities, and found that the scale of the decoder circuit can be reduced.

An object of the present invention is to provide a staircase wave generation circuit in which the circuit is made into a cylindrical element.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a logic gate circuit is provided corresponding to each of a plurality of switch elements that selectively output a plurality of divided voltages formed by a resistor ladder, and a logic gate circuit is provided corresponding to each of a plurality of switch elements that selectively outputs a plurality of divided voltages formed by a resistor ladder, and receives the output signal of a counter circuit and converts it into a staircase wave to be output. Form a corresponding switch control signal.

[For production]

According to the above-mentioned means, since the decoder circuit can basically be constituted by logic gates corresponding to the number of switch elements, the circuit can be made into a cylinder.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Each circuit in the figure is formed on a single semiconductor substrate, such as single crystal silicon, using known semiconductor integrated circuit manufacturing techniques.

Between the positive voltage +V and the negative voltage -2, a series circuit consisting of resistors R1 to R'5 is provided as a representative example. A staircase-like divided voltage is formed at the interconnection point of these resistors.

In this embodiment, in order to form an alternating current staircase wave of both positive and negative polarities, the divided voltage is composed of eight types. A MOSFET (
Switch elements S1 to S8 each consisting of an insulated gate field effect transistor are provided. The output sides of these switch elements S1 to S8 are connected in common.

In this embodiment, the following logic gate circuits are provided for each of the switch elements Sl to S8.

At the gate of the switch element S1, a NAND (N A N
D) A substantial AND gate circuit consisting of a gate circuit Gl and an inverter circuit N9 is provided. The gates of the other switch elements S2 to S8 shown as examples are also provided with Nandt gate circuits G2 to G4 and the like described above. A logic gate circuit consisting of inverter circuits NIO to N12 is provided.

An input signal for controlling each of the above-mentioned switch elements is formed using the counting output of the counter circuit C0UNT. The counter circuit C0UNT is composed of a 4-bit binary counter circuit. In this case, focusing on obtaining a staircase wave approximating a sine wave, the counter circuit C0
Signals Q4 and G4 of the most significant bits of UNT are used as signals specifying positive and negative polarity.

G2, Ql, and Ql are converted into 2-bit signals A and B by a logic gate circuit using a clocked inverter circuit. That is, when forming a staircase wave having both positive and negative polarities as described above, there are voltages that are the same in absolute value.

Therefore, the combination of the above signals A and B defines the absolute value level, and the combination with the above most significant bit forms a switch control signal that outputs a staircase wave of both positive and negative polarities. .

Table 1 shows the output Q4~ of the counter circuit C0UNT.
A conversion list of Q1 and signal AB is shown, and for reference, the number of the switch S that is turned on by it is also shown.

For such conversion, the count output Ql of the lower two bits is
, Ql and G2. G2 is clocked inverter times! It is input to Nl to N4. The remaining 1-bit count output Q3 is sent to the clocked inverter circuit N2 and N
The count output Q3 is supplied to the clock terminals of the clocked inverter circuits N1 and N3.

The outputs of the clocked inverter circuits N1 and N2 are commonly supplied to the input of an output inverter circuit N5, and a conversion signal A is formed from the output thereof. The outputs of the clocked inverter circuits N3 and N4 are transferred to the output inverter circuit N6.
are commonly supplied to the inputs of , and the converted output B is formed from its output. As a result, for example, when the count output Q3 is at a low level (the inverted output Q3 is at a high level), the outputs of the clocked inverter circuits N2 and N4 are enabled, and the conversion outputs A and B follow the count outputs Q1 and Q2. be taken as a thing. At this time, due to the low level of the count output Q3, the outputs of the clocked inverter circuits N1 and N3 are in a high impedance state.

Furthermore, when the counting output Q3 is at a high level (the inverted output Q3 is at a low level), the clocked inverter circuits N1 and N3
The outputs of the conversion outputs A and B become valid and the conversion outputs A and B follow the inverted counting outputs Q1 and Q2. Furthermore, at this time,
Due to the low level of the inverted count output Q3, the outputs of the clocked inverter circuits N2 and N4 are in a high impedance state.

The same holds true in the second half when the most significant bit Q4 is at a high level.

The signals A and B are inverted by inverter circuits N7° and N8, and are input to the Nant gate circuit together with the signals A and B in a combination as described below.

When forming a staircase wave close to a sine wave as shown in FIG. 2, the outputs Q4 to Q1 of the counter circuit C0UNT are 0.
000, the switch S4 is turned on and the fourth divided voltage from the maximum value corresponding to the switch S1 is output. Therefore, the Nant gate circuit corresponding to the switch S4 (not shown in the figure) is supplied with the inverted output Q4 of the most significant bit indicating the positive half cycle and the inverted signals of the signals A and B passed through the inverter circuits N7 and N8. be done. This results in
At timing T1 shown in FIG. 2, switch S4 can be turned on by oO of signals A and B corresponding to 0000 of count outputs Q4 to Q1 in Table 1.

+1 counting operation and output Q of counter circuit C0UNT
When 4 to Q1 is 0001, the switch S3 is turned on and the third divided voltage from the maximum value corresponding to the switch Sl is output. Therefore, the Nant gate circuit G3 corresponding to the switch S3 is supplied with the inverted output Q4 of the most significant bit indicating the positive half cycle, and the inverted signal of the signal A and the signal B passed through the inverter circuit N8. As a result, at timing T2 shown in FIG.
The switch S3 can be turned on.

Furthermore, when a +1 counting operation is performed and the outputs Q4 to Q1 of the counter circuit C0UNT are 0010, the switch S2 is turned on and the second divided voltage from the maximum value corresponding to the switch S1 is output.

Therefore, the Nant gate circuit G2 corresponding to the switch S2
is the inverted output Q of the most significant bit indicating the positive half cycle.
4, signal B and an inverted signal of signal A passed through inverter circuit N7. As a result, at timing T3 shown in FIG.
The switch S2 can be turned on by 01 of the signals A and B corresponding to to.

Further, a +1 counting operation is performed, and when the outputs Q4 to Ql of the counter circuit C0UNT are 0011, the switch S1 is turned on and the maximum value of the divided voltage is output. Therefore, the Nant gate circuit G1 corresponding to the switch Sl is supplied with the inverted output Q4 of the most significant bit indicating the positive half cycle and the signals A and B. As a result, at timing T4 shown in FIG. 2, the count outputs Q4 to Q1 in Table 1 are
The switch S1 can be turned on by signals A and H corresponding to 11.

Further, when a +1 counting operation is performed and the outputs Q4 to Q1 of the counter circuit C0UNT are 0100, the above is repeated. The outputs of the clocked inverter circuits N1 and N3 are enabled instead of the clocked inverter circuits N2 and N4, and the signal A is output as shown in Table-1.
and B will be the same.

Therefore, at timing T5 shown in FIG. 2, the switch S1 can be turned on by signals A and B of 11 corresponding to 0100 of the count outputs Q4 to Q1 in Table 1.

Furthermore, when a +1 counting operation is performed and the outputs Q4 to Q1 of the counter circuit C0UNT are 0101, the outputs of the clocked inverter circuits N1 and N3 are enabled instead of the clocked inverter circuits N2 and N4, as shown in Table-1. Signal A
and B are the same as timing T3. Therefore, at timing T6 shown in FIG. 2, the count output Q4~ of Table-1
01 of the signals A and B corresponding to 0101 of Q1 turns the switch S2 on a', and the second divided voltage is output.

Below, as is clear from the above conversion table, timing T8
The staircase wave changes in the opposite direction until .

Then, from timing T9, a negative polarity output signal is generated. Therefore, the highest level bin) Q4 is supplied to the Nant gate circuits corresponding to the switches S5 to S8 (not shown) that form a staircase wave on the negative polarity side, and the signals A and B that form the positive staircase wave are supplied. It is supplied by a combination similar to the above. As a result, during the period from timing T9 to T16, the signals A and B can be used in the same way as in the case of obtaining the positive polarity staircase wave by simply changing the polarity beep Q4.

In this configuration, the staircase wave can be obtained using a logic gate circuit corresponding to each switch element and a simple signal conversion circuit as described above.

It should be noted that, although not particularly limited, the above-mentioned switch Sl or S
The output signal output through 8 is output through an operational amplifier circuit OP configured as a voltage follower. If it is necessary to remove harmonic components contained in the staircase wave, an appropriate low-pass filter is provided.

For example, when configuring a tone generation circuit for a telephone, by changing the frequency of the input pulse φ supplied to the counter circuit C0UNT, the frequency can be set to 1/16 of that frequency.
It is possible to obtain a pseudo sine wave corresponding to .

The effects obtained from the above examples are as follows. That is, (1) A logic gate circuit should be provided corresponding to each of the plurality of switch elements that selectively output the plurality of divided voltages formed by the resistance ladder, and should receive and output the output signal of the counter circuit. By forming a switch control signal corresponding to a staircase wave, the decoder circuit can basically be configured by logic gates corresponding to the number of switch elements, thereby achieving the effect that the circuit can be simplified. Incidentally, when decoding the output signal of a 4-bit counter circuit, at least 16 logic gate circuits are required, but in the embodiment described above, it can be constructed from 8 logic gate circuits.

(2) The most significant bit of the counter circuit is a bit signal that specifies the positive/negative polarity of the AC staircase wave, and the remaining bits are used as the same bit for staircase waves of the same level of both positive and negative polarities depending on the combination. By using the converted signal, the number of inputs to the logic gate circuit can be reduced. This has the effect of further simplifying the circuit.

(3) When obtaining a staircase wave that is close to the sine wave, by using a clocked inverter circuit as the signal conversion circuit, it is possible to achieve the effect that signal conversion is possible with a simple configuration.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. For example, in FIG. 1, the signal conversion circuit made up of clocked inverter circuits N1 to N4 can be replaced with a switching circuit made up of logic gate circuits. In addition, the Nant gate circuit provided corresponding to the switch element is also
A NOR gate circuit or the like can be used depending on the conductivity type of the O3FET and the logic of the input level.

The present invention can be used as a staircase wave generation circuit, for example, for an application specific (ASIC) coder/decoder with a ringing function (
It can be widely used for applications such as GODEC).

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, a logic gate circuit is provided corresponding to each of a plurality of switch elements that selectively output a plurality of divided voltages formed by a resistor ladder, and a logic gate circuit is provided corresponding to each of a plurality of switch elements that selectively outputs a plurality of divided voltages formed by a resistor ladder, and receives the output signal of a counter circuit and converts it into a staircase wave to be output. By forming corresponding switch control signals, the decoder circuit can basically be configured with logic gates corresponding to the number of switch elements, so that the circuit can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining its operation.

Claims (1)

[Scope of Claims] 1. A resistor ladder that forms a plurality of divided voltages, a plurality of switch elements that selectively output the divided voltages, and a counter circuit provided corresponding to each of the switch elements. 1. A staircase wave generation circuit comprising: a logic gate circuit that receives an output signal of the output signal and forms a switch control signal at a timing corresponding to the staircase wave to be output. 2. The most significant bit of the counter circuit above is a signal that specifies the alternating current positive/negative polarity of the staircase wave to be output, and the remaining bits are used in combination to specify the positive/negative polarity of the staircase wave at the same level. converted into a signal with the same bits,
2. The staircase wave generating circuit according to claim 1, wherein the staircase wave generating circuit is supplied to a logic gate circuit provided corresponding to each of the switching elements. 3. The first or second claim characterized in that the frequency of the input pulse input to the counter circuit is made variable so that the frequency of the staircase wave outputted is also made variable. The staircase wave generation circuit described in item 2.