JPH01218041A - Protective element against static electricity - Google Patents

Protective element against static electricity

Info

Publication number
JPH01218041A
JPH01218041A JP63044788A JP4478888A JPH01218041A JP H01218041 A JPH01218041 A JP H01218041A JP 63044788 A JP63044788 A JP 63044788A JP 4478888 A JP4478888 A JP 4478888A JP H01218041 A JPH01218041 A JP H01218041A
Authority
JP
Japan
Prior art keywords
electrode
wiring
line
parasitic resistance
static electricity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63044788A
Other languages
Japanese (ja)
Inventor
Yoichi Endo
陽一 遠藤
Tomoaki Ito
伊藤 友明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP63044788A priority Critical patent/JPH01218041A/en
Publication of JPH01218041A publication Critical patent/JPH01218041A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate a parasitic resistance and to perform sufficient protection against a breakdown due to static electricity by a method wherein a signal line is bypassed and an emitter electrode part of a protective element is connected to a lowest potential line directly by using a wiring part on an IC. CONSTITUTION:Signal lines L1, L2 are arranged and installed between a base electrode (B) and an emitter electrode (E) of a protective element composed of a bipolar transistor. The electrode (E) is connected directly to a ground line (G) by using a wiring part Ls. Accordingly, a parasitic resistance value r1 becomes nearly zero. The electrode (B) is connected to the ground line (G) through the inside of a substrate via a substrate connection part S3 and a substrate connection part S4; accordingly, a parasitic resistance value r2 is produced. The existence of the resistance value r2 is not so harmful. Accordingly, an excess voltage from the outside can be absorbed completely. By this setup, a sufficient protection against a breakdown due to static electricity can be performed.

Description

【発明の詳細な説明】 [概要] 内部回路を保護するための静電気保護素子の配置に関し
、 静電気破壊からの保護効果を高くすることを目的とし、 単層配線マスタースライス方式の半導体集積回路におい
て、バイポーラトランジスタからなる保護素子のベース
電極とエミッタ電極との間に信号線が配設され、前記エ
ミッタ電極と最低電位線が配線で直接接続されているこ
とを特徴とする。
[Detailed Description of the Invention] [Summary] With regard to the arrangement of electrostatic protection elements for protecting internal circuits, the purpose of this invention is to improve the protection effect from electrostatic damage in a single-layer wiring master slice type semiconductor integrated circuit. A signal line is disposed between a base electrode and an emitter electrode of a protection element made of a bipolar transistor, and the emitter electrode and the lowest potential line are directly connected by wiring.

[産業上の利用分野] 本発明は内部回路を保護するための静電気保護素子の配
置に関する。
[Industrial Field of Application] The present invention relates to the arrangement of electrostatic protection elements for protecting internal circuits.

ICデバイスは微細化されて耐圧が低くなっており、現
在、静電破壊(Electro 5tatic Dis
charge)に対する保護対策は益々その重要性が増
している。
IC devices have become smaller and have lower withstand voltages, and are currently prone to electrostatic damage (electrostatic discharge).
Measures to protect against ``charge'' are becoming more and more important.

[従来の技術] 静電気保護とは、入出力端(以下は入力端によって説明
する)に静電気に伴う異常高圧、例えば、数百ポルトの
高圧が印加されたとき、IC内部のトランジスタが破壊
されないように保護する素子のことで、その異常電圧は
チャージされた人体から受けることも多く、人体は容易
に帯電して数千ボルトにも達する場合がある。
[Prior Art] Electrostatic protection is a method to prevent transistors inside an IC from being destroyed when an abnormally high voltage due to static electricity, for example, a high voltage of several hundred ports, is applied to input/output terminals (the input terminals will be explained below). The abnormal voltage is often received from a charged human body, and the human body is easily charged and can reach several thousand volts.

このような異常高圧によるICの破壊を防ぐため、従来
から種々の保護素子、保護回路素子が考案されており、
例えば、抵抗、ダイオード、トランジスタの付加、抵抗
とダイオードの組み合わせ回路等が考案されている。そ
れは外部入力端と内部回路間にそのような保護素子、保
護回路素子を挿入して、過電圧を入力端で吸収させる方
式である。
In order to prevent IC destruction due to such abnormally high voltage, various protection elements and protection circuit elements have been devised.
For example, the addition of resistors, diodes, and transistors, and combination circuits of resistors and diodes have been devised. In this method, such a protection element or protection circuit element is inserted between the external input terminal and the internal circuit, and the overvoltage is absorbed at the input terminal.

例えば、アナログマスクスライスICにおいては、内部
回路の構成と同じバイポーラトランジスタからなる保護
素子を設けており、これは製作上都合が良いためで、第
3図はその保護素子の回路図を示し、Iは外部入力端、
0は内部回路入力端。
For example, in an analog mask slice IC, a protection element made of a bipolar transistor that has the same configuration as the internal circuit is provided. This is convenient for manufacturing. Figure 3 shows the circuit diagram of the protection element. is the external input terminal,
0 is the internal circuit input terminal.

Tはバイポーラトランジスタ+’l+’2はこの保護素
子Tに寄生する抵抗を示している。
T indicates a bipolar transistor, and +'l+'2 indicates a resistance parasitic to this protection element T.

一方、マスクスライス方式のICは利用者の要望によっ
て内部回路を設計するため、IC面の配線は自由にパタ
ーンニングされ、また、出来るだけ短期間に納入するこ
とが必要になって、製造工程を簡単にして、且つ、安価
に作製する関係上、IC面には単層配線のみを設けてお
り、通常、多層配線は形成していない。
On the other hand, since the internal circuits of mask-sliced ICs are designed according to the user's requests, the wiring on the IC surface can be patterned freely, and it is necessary to deliver the product as quickly as possible, which reduces the manufacturing process. For simplicity and inexpensive manufacturing, only single-layer wiring is provided on the IC surface, and multilayer wiring is usually not formed.

第4図はそのような単層配線アナログマスクスライスI
Cにおける従来の保護素子部分の平面図を示し、Cはト
ランジスタTのコレクタ電極部。
Figure 4 shows such a single-layer wiring analog mask slice I.
A plan view of a conventional protection element portion in C is shown, and C is a collector electrode portion of a transistor T.

Bはベース電極部、Eはエミ・7タ電極部、Gは接地線
(最低電位線) r  L + +  L2は信号線、
 Paはポンディングパッド(外部入力端)、Sl、S
2は基板接続部、その他の斜線部分は配線しoである。
B is the base electrode part, E is the emitter/7 electrode part, G is the ground line (lowest potential line) r L + + L2 is the signal line,
Pa is the bonding pad (external input terminal), Sl, S
2 is a board connection portion, and the other shaded portions are wiring lines.

また、第5図は第4図のAA断面図を示し、第4図と同
一部位に同一記号を付けているが、その以外のlはP型
シリコン基板、2はトランジスタTのN型コレクタ領域
、3はP型ベース領域。
Moreover, FIG. 5 shows a cross-sectional view taken along the line AA in FIG. 4, and the same parts as in FIG. , 3 is a P-type base region.

4はN+型エミッタ領域である。4 is an N+ type emitter region.

このように、アナログマスクスライスICにおいては、
バイポーラトランジスタからなる保護素子を設けて、静
電破壊に対する保護をおこなっている。
In this way, in analog mask slice IC,
A protection element made of a bipolar transistor is provided to protect against electrostatic discharge damage.

[発明が解決しようとする課題] ところで、上記の構造で問題となるのは、エミッタ電極
部Eが基板接続部S1と82とを介して長い基板内部を
通じて接地線Gに接続していることで、そのために寄生
抵抗r1が大きくなる。これは第3図の回路図と第4図
の平面図とを比較参照すれば明らかであるが、そのため
に外部より印加した過電圧(静電破壊電圧)の接地側へ
の吸収が不完全になって、静電気破壊からの保護効果が
十分でなくなる欠点がある。
[Problems to be Solved by the Invention] By the way, the problem with the above structure is that the emitter electrode portion E is connected to the ground line G through the inside of the long substrate via the substrate connection portions S1 and 82. , therefore, the parasitic resistance r1 increases. This is clear by comparing the circuit diagram in Figure 3 and the plan view in Figure 4, but as a result, the absorption of externally applied overvoltage (electrostatic breakdown voltage) to the ground side is incomplete. Therefore, there is a drawback that the protection effect against electrostatic damage is not sufficient.

本発明はこのような問題点を解消させて、静電気破壊か
らの保護効果を高めることを目的とした静電気保護素子
を提案するものである。
The present invention solves these problems and proposes an electrostatic protection element for the purpose of increasing the protection effect from electrostatic damage.

[課題を解決するための手段] その目的は、バイポーラトランジスタからなる保護素子
のベース電極とエミッタ電極との間に信号線が配設され
、該エミッタ電極と最低電位線が配線で直接接続されて
いる静電気保護素子によって達成される。
[Means for solving the problem] The purpose is to provide a signal line between a base electrode and an emitter electrode of a protection element made of a bipolar transistor, and to directly connect the emitter electrode and the lowest potential line with wiring. This is achieved by an electrostatic protection device.

[作用] 即ち、単層配線のICにおいては、信号線の存゛在のた
めに保護素子のエミッタと最低電位線(例えば、接地線
)との接続を配線(導電性の良い線)でおこなうことが
できず、最低電位線には基板を通じて接続している。そ
のために、大きな寄生抵抗r1か発生する。
[Function] In other words, in a single-layer wiring IC, due to the presence of a signal line, the emitter of the protection element and the lowest potential line (e.g., ground line) are connected by wiring (a wire with good conductivity). Therefore, it is connected to the lowest potential line through the board. Therefore, a large parasitic resistance r1 occurs.

本発明は信号線を迂回させて、保護素子のエミッタ電極
部と最低電位線との接続を直接IC面上の配線でおこな
うように構成する。そうすれば、寄生抵抗r、が殆どな
くなって、静電気破壊からの保護が十分になる。
The present invention is configured so that the signal line is detoured and the connection between the emitter electrode portion of the protection element and the lowest potential line is directly made by wiring on the IC surface. By doing so, the parasitic resistance r is almost eliminated, and protection from electrostatic damage becomes sufficient.

[実施例] 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

第1図は本発明にかかる保護素子部分の平面図を示し、
第2図は第1図のDD断面図を示している。これらの図
において、第4図および第5図と同一部位に同一記号が
付けであるが、その他の部位のs3.s4は基板接続部
、Lsは配線(エミッタ接続部Eと接地線Gとを直接接
続する配線)である。図示のように、信号線1.、、L
2は迂回させて、バイポーラトランジスタTのベース電
極部とエミッタ電極部の間に配設しており、エミッタ電
極部と接地線Gとの直接の配線1.sが可能になってい
る。
FIG. 1 shows a plan view of a protection element portion according to the present invention,
FIG. 2 shows a DD sectional view of FIG. 1. In these figures, the same parts as in Figs. 4 and 5 are given the same symbols, but other parts of s3. s4 is a substrate connection portion, and Ls is a wiring (a wiring that directly connects the emitter connection portion E and the ground line G). As shown, signal line 1. ,,L
2 is detoured and arranged between the base electrode part and the emitter electrode part of the bipolar transistor T, and the wiring 1.2 is directly connected between the emitter electrode part and the ground line G. s is now possible.

これは第1図に示す平面図と第3図の回路図とを比較す
ると明らかで、このように、配線Lsによってエミッタ
電極部Eと接地線Gとを直接接続しているため、第3図
に示す寄生抵抗rlは殆ど零になる。一方、ベース電極
部Bは基板接続部S3と54とを介して長い基板内部を
通じて接地線Gに接続することになるから、寄生抵抗r
2が発生する。しかし、寄生抵抗r2の存在は余り害に
はならず、寄生抵抗r1が除去された本発明にかかる保
護素子の構成は外部からの過電圧を完全に吸収して、静
電気破壊から十分に保護することができる。従って、I
Cの信頼性を一層向上させることができる。
This becomes clear when comparing the plan view shown in FIG. 1 with the circuit diagram shown in FIG. The parasitic resistance rl shown in is almost zero. On the other hand, since the base electrode part B is connected to the ground line G through the inside of the long board via the board connection parts S3 and 54, the parasitic resistance r
2 occurs. However, the presence of the parasitic resistance r2 does not cause much harm, and the structure of the protection element according to the present invention in which the parasitic resistance r1 is removed completely absorbs external overvoltage and provides sufficient protection from electrostatic damage. Can be done. Therefore, I
The reliability of C can be further improved.

なお、上記の実施例は最低電位線を接地線として説明し
ているが、接地線より更に低電位の最低電位線(例えば
、電源線)を有する回路にも、その最低電位線とエミッ
タ電極部を直接配線して接続する方法によって本発明を
適用することができ、また、アナログ以外の単層配線マ
スクスライスICにも適用できることは当然である。
Note that although the above embodiment has been described using the lowest potential line as the ground line, a circuit having a lowest potential line (for example, a power supply line) that is lower in potential than the ground line may also have the lowest potential line and the emitter electrode section. It goes without saying that the present invention can be applied by a method of connecting by direct wiring, and can also be applied to single-layer wiring mask slice ICs other than analog ones.

[発明の効果] 以上の実施例の説明から明らかなように、本発明にかか
る静電気保護素子を配設すれば、マスクスライスICの
信φ頁性向上に一層効果があるものである。
[Effects of the Invention] As is clear from the description of the embodiments above, if the electrostatic protection element according to the present invention is provided, the reliability of the mask slice IC can be further improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明にかかる保護素子部分の平面図、第2図
は第1図のDD断面図、 第3図は保護素子の回路図、 第4図は従来の保護素子部分の平面図、第5図は第4図
のAA断面図である。 図において、 Tはトランジスタ(バイポーラトランジスタ)、rl、
r2は寄生抵抗、 Cはコレクタ電極部、 Bはベース電極部、 Eはエミッタ電極部、 Gは接地線(最低電位線)、 L、、L2は信号線、 Paはボンディングパソド(外部入力端)、S、、S2
は基板接続部、 Loは配線、 Lsは配線(エミッタ接続部Eと接地線Gとを直接接続
する配線)、 1はP型シリコン基板、 2はN型コレクタ領域、 3はP型ベース領域、 4はN+型エミッタ領域 を示している。 第 1 A 才1聞へDDur命図 第 2 図 alll) l1lOnQ 第3図 イ声?jトワイjミgl己1【都7乏デ1り平面rン〕
第4図 ?41ZI tQAA @ffxr m第5図
FIG. 1 is a plan view of the protection element portion according to the present invention, FIG. 2 is a DD sectional view of FIG. 1, FIG. 3 is a circuit diagram of the protection element, and FIG. 4 is a plan view of the conventional protection element portion. FIG. 5 is a sectional view along line AA in FIG. 4. In the figure, T is a transistor (bipolar transistor), rl,
r2 is the parasitic resistance, C is the collector electrode, B is the base electrode, E is the emitter electrode, G is the ground line (lowest potential line), L, L2 is the signal line, and Pa is the bonding path (external input terminal). ), S,, S2
is the substrate connection part, Lo is the wiring, Ls is the wiring (the wiring that directly connects the emitter connection part E and the ground line G), 1 is the P-type silicon substrate, 2 is the N-type collector region, 3 is the P-type base region, 4 indicates an N+ type emitter region. 1st A To 1st hearing DDur life chart 2nd diagram allll) l1lOnQ 3rd diagram I voice? j toy j mi gl self 1 [city 7 poor de 1ri plane rn]
Figure 4? 41ZI tQAA @ffxr mFigure 5

Claims (1)

【特許請求の範囲】[Claims]  単層配線マスタースライス方式の半導体集積回路にお
いて、バイポーラトランジスタからなる保護素子のベー
ス電極とエミッタ電極との間に信号線が配設され、前記
エミッタ電極と最低電位線が配線で直接接続されている
ことを特徴とする静電気保護素子。
In a semiconductor integrated circuit using a single-layer wiring master slice method, a signal line is provided between a base electrode and an emitter electrode of a protection element made of a bipolar transistor, and the emitter electrode and the lowest potential line are directly connected by wiring. An electrostatic protection element characterized by:
JP63044788A 1988-02-26 1988-02-26 Protective element against static electricity Pending JPH01218041A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63044788A JPH01218041A (en) 1988-02-26 1988-02-26 Protective element against static electricity

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63044788A JPH01218041A (en) 1988-02-26 1988-02-26 Protective element against static electricity

Publications (1)

Publication Number Publication Date
JPH01218041A true JPH01218041A (en) 1989-08-31

Family

ID=12701146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63044788A Pending JPH01218041A (en) 1988-02-26 1988-02-26 Protective element against static electricity

Country Status (1)

Country Link
JP (1) JPH01218041A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009064974A (en) * 2007-09-06 2009-03-26 Sanyo Electric Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009064974A (en) * 2007-09-06 2009-03-26 Sanyo Electric Co Ltd Semiconductor device

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