JPH01217934A - Carrier tape - Google Patents

Abstract

PURPOSE:To provide multiple pins and to improve reliability and operating efficiency by allowing conductor wirings to protrude at its ends into a device hole for mounting a chip, and providing a wiring region by utilizing the hole. CONSTITUTION:A plurality of sprocket holes 2 are punched at both ends of a resin film of a carrier tape 1 on the basis of a standard, and device holes 3 are punched at the center thereof at suitable intervals, respectively, a copper foil is then, for example, laminated on the tape, a pattern of conductor wirings 4 are formed by photoresist or etching technique, and the ends of the wirings 4 protrude into the hole 3. A point (a) is connected to a point (b) by the wiring 4B to avoid a cross under. Thus, since the wirings 4 and 4B are not to be possibly short-circuited, there is no necessity of interposing an insulating film therebetween. Even if the region of the wirings 4 at the periphery of the hole 3 is crowded, the connection can be performed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a carrier tape, and in particular to the arrangement of a carrier tape used when incorporating semiconductor chips by tape automated bonding (TAB) method. Regarding technology.

[Conventional technology]

One of the technologies for integrating semiconductor elements is the tape carrier method. This method uses film carrier or TAB
(Tape Automated Bonding)
It is also called a method. This method is a method in which semiconductor elements are successively assembled into a resin tape with long sprocket holes (half-olace sprocket holes).
The tape carrier has a lead pattern (conductor layout WM) that matches the electrode arrangement of a semiconductor element (chip) formed on a resin film that has sprocket holes and device holes, such as a polyimide film with adhesive. Slit it to an appropriate width, punch sprocket holes for feeding and positioning, and device holes for incorporating the chip, laminate it with steel foil, and create the desired lead pattern using photoresist technology and etching technology. It is manufactured through a process of forming.

This method is characterized by protruding finger-shaped leads into the device hole, and the chip is aligned face-up and bonded to the tip of the lead.

This bonding (intake/debonding) method involves forming bumps (protruding electrodes) on the chip side electrodes, and performing gang bonding between these and finger leads on the tape, or placing a panda on the lead side. There is a method of forming a bump in advance and performing gigantic bonding between the bump and the chip-side electrode.

By the way, the number of electrodes of the chip incorporated in the tape carrier is increasing (multi-bin) as the circuit elements in the chip become more highly integrated.As a result, the number of conductor wiring is increasing and the pattern thereof is also becoming more complex. There is a tendency to become

On the other hand, 21. Conventionally, in aging tests of chips, a new 1iE source line was provided outside the lead pattern along the length of the tape, and 1[pressure] was sent from the power line to the chip to cause the chip to operate. was adopted, but this method did not allow the chip to operate satisfactorily, causing problems in testing, and also caused the chip to lack reliability.

Incidentally, an example of the above-mentioned tape carrier technique described above is JP-A-55-143040.

[Problem to be solved by the invention]

An object of the present invention is to provide a technique that can cope with an increase in the number of conductor wirings and the complexity of their patterns. As a countermeasure, it may be possible to route the conductor wiring so that it crosses over the conventional lead pattern, but with this one-way lossover method,
Absolutely to prevent cuttate between leads! ＃Leave the membrane
It is necessary to take measures such as interposition between cables, which increases costs and reduces work efficiency.The aim is therefore to provide a technology that can meet such demands without having to deal with such drawbacks. do.

Further, the present invention aims to provide a technique capable of improving the accuracy and reliability of testing in the above-mentioned knee test. teeth,
It will become clear from the description of this specification and the accompanying drawings.

[Failure to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In the present invention, the tip of the conductor wiring is made to protrude into a device hole for chip integration, and the device hole is utilized to further provide a wiring area in the device hole.

[Effect]

In this way, by determining the wiring area in the device hole, when it is necessary to increase the number of conductor wirings, it is possible to avoid crossing the conventional conductor wirings, and to prevent overlapping, it is possible to avoid Since there is no need to interpose a film between the conductor wirings, costs can be reduced in manufacturing the chip carrier, and processes can be omitted, improving work efficiency.

In addition, when providing the distribution area in the device hole, we use conductor wiring that can be bonded to the chip and send voltage to the chip through the conductor wiring, making aging tests possible and improving reliability. can be done.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a plan view showing an embodiment of the present invention.

In FIG. 1, 1 is a carrier tape, 2 is a sprocket hole, 3 is a device hole, and 4 is a conductor wiring.

For example, a long resin film is suitable for the carrier tape 1! A tape is constructed by slitting the tape, and a sugrocookt hole 2 is formed at both ends of the tape based on the standard.
In addition, a plurality of device holes 3 are punched in the center at appropriate intervals, and then conductors are arranged. I
! It can be manufactured by laminating, for example, a copper foil for forming the A4 on the tape, and forming a pattern of the conductor wiring 4 by making full use of photoresist technology or etching technology. The tip of the conductor arrangement Mj4 is made to protrude into the device hole 3.

In such a carrier tape 1, a conductor wiring is now formed from a point 10 located away from one side of the device hole 3 to a point 0 located away from the opposite side of the device hole 3, and the conductor wiring connects these 0 points. If you want to connect the 0 point and
This becomes possible by forming a . But then,
Since the conductor wiring M14 and the conductor wiring m4A are short-circuited5, it becomes necessary to interpose an insulating film between these wirings. If this happens, material costs will increase, the process will become longer, and if the wiring pattern becomes complex, it will become virtually impossible to make it that way.

Therefore, in the present invention, as shown in FIG. 1, the device hole 3 is utilized and the 0 points are connected via the conductor wiring 4B. As a result, the above-mentioned cross-under can be avoided, and since there is no risk of short-circuiting between the conductor wiring 4 and the conductor wiring @4B, there is no need for an intervening insulating film. In addition, since the device hole 3 is utilized and there is no need to use the conventional conductor distribution area 4 for connection, the conventional conductor distribution M4 around the device hole 3 is To enable connection even if the m% area becomes crowded. In the above, even if the tip of the conductor wiring @4 is patterned in accordance with the electrode pad position of the chip to be incorporated into the carrier tape 1, the conductor wiring 4B for connecting the 0 points and the 0 points is between the pads. Butter it so that it is located.

FIG. 1 shows how the chip 5 is bonded.

FIG. 2 shows another embodiment of the invention. In this embodiment, three consecutive conductor wirings 4B are arranged along the sprocket hole 2 of the tape, and the device hole 3
The conductor wiring 4B connected through the white line extends to the adjacent device hole 3, and is connected to the conductor wiring @4B connected through the device hole 3 adjacent to the white line.
The individual conductor wires 4B of the main conductor wires 4B are a common wire.

That is, these conductor wirings 4B of the chip 5! , and other pads, and the chip 5 incorporated in each device hole 3 is electrically connected by the conductor wiring 4B.

From this K, multiple signals can be sent to the chip 5 through multiple conductor arrangements @4B, and testing and reliability can be improved. In addition, in FIG. 2, the conventional conductor arrangement wA4 is omitted.

The semiconductor element (chip) 5 used in the present invention is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip by well-known techniques to provide one circuit function. Specific examples of circuit elements include MO
Consists of S transistors, and these circuit elements:
For example, logic circuits and memory circuit functions are formed.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions among the inventions disclosed in this section is as follows.

According to the present invention, when manufacturing a tape carrier, it is possible to reduce costs, improve work efficiency, meet the demand for increasing the number of pins, and improve reliability.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of the invention, and FIG. 2 is a plan view showing another embodiment of the invention. 1...Carrier tape, 2...Tin rocket hole, 3...Device hole, 4...Conductor wiring, 4A・
...Conductor wiring, 4B...Conductor wiring, 5...Semiconductor element (chip). Figure 1 Figure 2

Claims (1)

[Scope of Claims] 1. A long tape has a plurality of device holes formed at appropriate intervals in the center thereof for incorporating semiconductor elements, and a plurality of feeding/positioning holes at both ends of the tape. In a carrier tape having a sprocket hole for mating, and a conductor wiring formed on the tape with a tip thereof protruding into the device hole, a part of the conductor wiring on the tape is A carrier tape characterized in that the carrier tape is connected through the device hole. 2. The carrier tape according to claim 1, wherein the conductor wirings connected through the device holes extend to adjacent device holes, and these conductor wirings are connected along the length direction of the tape.