JPH01217511A - Interruption circuit - Google Patents

Abstract

PURPOSE:To prevent unnecessary initial setting and to eliminate a trouble or an accident by causing a CPU to have function to output the executing condition of an interruption processing program to an external part in the shape of an output signal and providing a circuit to prohibit the input of a reset signal to the CPU with the output signal. CONSTITUTION:An external output terminal OUT of a CPU40 is controlled by the interruption processing program and when the CPU40 executes the interruption processing program, the external output terminal OUT goes to H. Thus, an output side N3 of a NAND gate 72 goes to H and a reset input terminal inverting RES goes to non-active. Accordingly, the input of a reset signal 60S is prohibited and the input of an interrupting signal 50S gets priority. When the interrupting signal 50S and reset signal 60S are simultaneously generated, the interrupting signal 50S is inputted top the CPU40 with priority. Namely, when a power source voltage is lowered and a system is instable, data are saved without fail and emergency stop is executed. Then, the causes of the trouble or accident are erased and the recovery work of the unnecessary initial set is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an interrupt circuit in a microcomputer application system.

(Prior Art) Conventionally, as this type of interrupt circuit, for example, the one shown in FIG. 2 has rarely been used. The configuration will be explained below.

FIG. 2 is a block diagram showing an example of the configuration of an interrupt circuit in a conventional microcomputer application system.

This interrupt circuit includes a central processing unit (hereinafter referred to as CP) having an interrupt input terminal INI, a reset input terminal I<S, etc.
10, whose interrupt input terminal TXT is connected to a voltage drop detection circuit 20, and whose reset input terminal RES is connected to an initial reset circuit 30. The voltage drop detection circuit 20 detects a drop in the power supply voltage VCC, outputs an interrupt signal 203, and sends it to the CPU 10.
This is a circuit that supplies the interrupt input terminal I N 'l.

The initial reset circuit 30 is a circuit that outputs a reset signal 308 when the power is turned on and supplies it to the reset input terminal RES of the CPUIO.
The resistor 31 and the capacitor 32 are connected in series between the resistor 31 and the ground, and the diode 33 is connected in parallel to the resistor 31.

Next, the operation will be explained.

When the power supply voltage VCC is supplied to the system, the reset input terminal RES of the CPU 10 becomes active (active state) by the reset signal 30S for a period of time due to the charging action of the capacitor 32 of the initial reset circuit 30. The above-mentioned dwell time is determined by the resistor 31 and capacitor 32. When the reset input terminal RES becomes active, the CPU 10 enters the reset state, and when the reset input terminal RES changes to non-active (inactive state), it fetches the instruction at address O and starts the initial program prepared in advance from address O. (Initial program)
Execute.

On the other hand, the voltage drop detection circuit 20 detects the system power supply voltage VC.
C is constantly monitored, and when the voltage falls below a preset setting voltage, an interrupt signal 203 is output to activate the interrupt input terminal INT of the CPU 10. When the interrupt input terminal I\T becomes active, the CPU 10 interrupts the program currently being executed and executes the interrupt processing program at a predetermined address, thereby performing processing when the power supply voltage VCC drops.

(Problems to be Solved by the Invention) However, the interrupt circuit having the above configuration has the following problems.

The initial reset circuit 30 outputs a reset signal 303 for setting initial data at a required location when the voltage has not risen completely when the power is turned on. For example, in the case of the CPU 10, the contents of each register are forcibly set to predetermined values, and in the case of a system, the registers, buffers, etc. of each system are forcibly set to predetermined values. Since the initial reset circuit 30 is necessary for a circuit having such a function, it outputs the reset signal 308 when the voltage reaches a voltage value in which the voltage does not rise completely except when the power is turned on. As a result, the power supply voltage CC becomes unstable while the CPU 10 or the system is operating, and the voltage drops only momentarily, and the CPU ignores the current processing status.
U10 or the system will be forcibly returned to the initial state. If the system returns to its initial state even though it is in operation, status information, danger information in the system, etc. will disappear, potentially causing trouble or accidents. Furthermore, even if such troubles or accidents do not occur, a great deal of effort is required to restore the current processing state.

The present invention solves the problems that the prior art had, such as the fact that a reset signal is output at times other than when the power is turned on, which can cause troubles or accidents, or when the initial settings are made unnecessarily. The present invention provides an interrupt circuit that solves the problem of requiring a great deal of effort.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an initial reset circuit that outputs a reset signal for initial setting when the power is turned on, and an initial reset circuit that outputs a reset signal for initial setting when the power supply voltage drops below a set value. a voltage drop detection circuit that detects and outputs an interrupt signal;
In an interrupt circuit comprising a CPU that executes an initial setting program upon input of the reset signal, executes an interrupt processing program upon input of the interrupt signal, and holds data being processed, the execution state of the interrupt processing program is determined. The function of outputting to the outside in the form of an output signal is provided by the CP.
In addition, a prohibition circuit is provided for prohibiting input of the reset signal to the CPU based on the output signal.

(Function) According to the present invention, since the interrupt circuit is configured as described above, the inhibit circuit outputs the output from the initial reset circuit based on the output signal of the CPU during a temporary voltage drop other than when the power is turned on. It works to inhibit input of the reset signal to the CPU. This prevents the CPU from being forcibly initialized by ignoring the processing state/υ due to a temporary drop in power supply voltage, which can prevent troubles and accidents, and the current situation due to unnecessary initialization. Restoration work can be simplified. Therefore, it is necessary because the above problem can be solved.

(Embodiment) FIG. 1 is a block diagram of an interrupt circuit in a microcomputer application system according to an embodiment of the present invention.

In Figure 1, the CPtJ40, which controls the necessary microcomputer application system, executes an interrupt processing program at a predetermined address that interrupts the currently executing program, in addition to the control section, arithmetic section, register section, etc. An interrupt input terminal i to which an interrupt signal 503 is input for
NT, a reset input terminal RES for inputting a reset signal for bringing the CPtJ40 into an initial state, and an external output terminal OUT for outputting a signal indicating the execution state of the interrupt processing program.

A voltage drop detection circuit 50 is connected to the interrupt input terminal TXT of the CPU 40, and an initial reset circuit 60 is connected to the interrupt input terminal TXT of the CPU 40.
is connected to the reset input terminal π' of the CPU 40 via the inhibit circuit 70.

The voltage drop detection circuit 50 monitors a drop in the power supply voltage CC, and when the power supply voltage VCC drops below a set value, outputs an interrupt signal Q50S to the interrupt input terminal i of the CPU 40.
This is the circuit that supplies NI.

The initial reset circuit 60 is a circuit that generates a reset signal 60S for a certain period of time when the power is turned on.
For example, it includes a resistor 61 and a capacitor 62 connected in series between the power supply voltage VCC and ground, and a diode 63 connected in parallel to the resistor 61. Prohibition circuit 70
is an interrupt signal @ when the CPU 40 is operating normally.
50S and the reset signal 603 are generated at the same time, this circuit inhibits the reset signal 603 and gives priority to the interrupt signal @50B and supplies it to the CPU 40. This inhibition circuit 70 includes, for example, a Schmitt trigger inverter 71 that outputs a square wave signal from a reset signal 603, and a manually operated NAND gate (hereinafter referred to as a NAND gate) 72.
, a PNP type transistor 3 and a resistor 74, and the output side node N of the Schmitt 1 to Rigger inverter 71
1 is connected to one input terminal of the NAND gate 72,
An external output terminal OUT of the CPU 40 is connected to the base of the transistor 73. Roughly speaking, the collector of the transistor 73 is grounded, and the node N2 on the emitter side is
It is connected to the power supply voltage VCC via a resistor 74, and
It is connected to the other input terminal of the NAND gate 72, and the output node N3 of the NAND gate 72 is connected to the reset input terminal τ of the CPU 40.

3 is a waveform diagram of FIG. 1, and FIG. 4 is a flowchart of FIG. 1, and the operation of FIG. 1 will be explained with reference to these figures.

When the CPU 40 is operating normally, if the power supply voltage Vcc to the microcomputer application system drops below a certain set voltage Vth, the voltage drop detection circuit 50 detects each and sets the voltage to a low level (hereinafter referred to as LI+). The interrupt signal 503 is output. Then, the interrupt input terminal TXT of the CPU 40 becomes active, so the CPU 40 sets the external output terminal OUT to "HH" to prohibit the input of the reset signal 608, and also changes the currently running program as shown in FIG. The CPU 40 interrupts the process and executes an interrupt processing program prepared in advance at a predetermined address.In other words, the CPU 40 saves the processing data currently being executed to a location where it will not be destroyed, such as a backup memory, and enters an emergency stop state.Next Then, the CPU 40 sets the external output terminal OUT to "'H" to permit input of the reset signal 603 (step 102>), waits for a certain period of time (step 103), and reset signal @603 must be input during this time. In this case, it is determined that the power supply voltage CC is momentarily stopped, and the external output terminal OUT is set to prohibit input of the reset signal 603.
is set to "Lpa" and jumps to the 1st day back program, starts the 1st day back program (step 105), and ends the process.

On the other hand, as shown in FIG. 3, when the power supply voltage VCC decreases, the initial reset circuit 60
Since the charge stored in is discharged to the power supply voltage VCC side via the diode 63, a reset signal 60S is output which lowers the voltage below the reference voltage Vi, 11. This reset signal 60S causes the capacitor 62 to return to the power supply voltage VC.
Since it is charged with C, it exceeds the base Q voltage Vih and rises to the power supply voltage Vcc. Then, the Schmitt trigger inverter 71 rises to 11H11 when the reset signal @60S drops to the reference voltage iQ, and goes "L" when the reset signal 60S rises again to the reference voltage Vih.
A falling signal is output to the output node N1. Here, in order for the reset input terminal RES of the CPU 40 to become active, the input side node N1 of the NAND gate 72 must be
．． In other words, in order for node N2 to become 1 (HI+), the transistor 73 must be turned off by the external output terminal OUT becoming "HMI." The output terminal OUT is controlled by the interrupt processing program and
When the PU40 executes the interrupt processing program, its external output terminal OUT becomes 11H41, so the NAN
The output side N3 of the D gate 72 becomes 14HT1, the reset input terminal RES becomes non-active, the input of the reset signal @6os is prohibited, and the input of the interrupt signal 503 is prioritized. In this way, the interrupt signal 50
3 and the reset signal 60S occur at the same time, the interrupt signal @50S is input to the CPU 40 with priority, ensuring that data is not lost when the system becomes most unstable due to a drop in the power supply voltage. Evacuation and emergency stop of the operating parts are performed, thereby eliminating troubles and accidents, and unnecessary work to restore initial settings can be omitted.

Note that the present invention is not limited to the illustrated embodiment, and the initial reset circuit 60 may be configured with another circuit, or the inhibition circuit 70 may be configured with a circuit other than that shown in FIG. 1 using another gate circuit, etc. , various modifications are possible.

(Effects of the Invention) As described above in detail, according to the present invention, the CPU is provided with the function of outputting the execution state of the interrupt processing program in the form of an output signal, and the inhibition circuit is provided.
The prohibition circuit prohibits input of a reset signal to the CPU when the power supply voltage temporarily decreases. Therefore, unnecessary initial settings can be prevented, troubles and accidents can be eliminated, and work for restoring unnecessary initial settings can be omitted, improving reliability.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an interrupt circuit showing an embodiment of the present invention, Fig. 2 is a block diagram of a conventional interrupt circuit, Fig. 3 is a waveform diagram of Fig. 1, and Fig. 4 is a flowchart of Fig. 1. is. 40...CPU, 50...Voltage drop detection circuit, 60...Initial reset circuit, 7
0...Prohibition circuit, 503...υ1 included signal, 603...Reset signal, OUT...
...External output terminal. Applicant's agent Yasushi Kakimoto 60 Initial reset circuit 70 Inhibition circuit 5081 Sub-commitment No. 6QS Reset signal L-1-----'' Spreading circuit of the present invention Fig. 1 of Fig. 1 Waveform diagram

Claims (1)

[Scope of Claims] An initial reset circuit that outputs a reset signal for initial setting when the power is turned on; a voltage drop detection circuit that detects when the power supply voltage drops below a set value and outputs an interrupt signal; Execution of the interrupt processing program in an interrupt circuit comprising a central processing unit that executes an initial setting program upon input of the reset signal, executes an interrupt processing program upon input of the interrupt signal, and holds data being processed. The central processing unit is provided with a function of outputting the state to the outside in the form of an output signal, and a prohibition circuit is provided that prohibits input of the reset signal to the central processing unit based on the output signal. interrupt circuit.