JPH01216560A - Board for die bonding semiconductor device - Google Patents

Board for die bonding semiconductor device

Info

Publication number
JPH01216560A
JPH01216560A JP4158888A JP4158888A JPH01216560A JP H01216560 A JPH01216560 A JP H01216560A JP 4158888 A JP4158888 A JP 4158888A JP 4158888 A JP4158888 A JP 4158888A JP H01216560 A JPH01216560 A JP H01216560A
Authority
JP
Japan
Prior art keywords
substrate
thickness
metal layer
diamond layer
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4158888A
Other languages
Japanese (ja)
Inventor
Toru Kono
河野 通
Katsuhiro Shimada
島田 勝弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Metal Corp
Original Assignee
Mitsubishi Metal Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Metal Corp filed Critical Mitsubishi Metal Corp
Priority to JP4158888A priority Critical patent/JPH01216560A/en
Publication of JPH01216560A publication Critical patent/JPH01216560A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve heat sink and electric insulation by laminating a diamond layer of specific thickness through a high melting point metal layer made of W, Mo, Ta, Nb or Hf with specific thickness on the semiconductor chip brazing face and circuit forming of an Fe series alloy body containing high Ni content. CONSTITUTION:A diamond layer having 0.1-20mum of mean thickness is laminated through a high melting point metal layer made of W, Mo, Ta, Nb or Hf with 0.01-1mum of mean thickness on the semiconductor chip brazing face and circuit forming face of an Fe series alloy body containing high Ni content. Thus, a board for die bonding a semiconductor device with excellent electric insulation and heat sink is formed. A substrate B is charged with the metal layer disposed upside in a quartz reaction tube A of a chemical vapor deposition unit, the unit is evacuated in vacuum and degassed, and a metal tungusten filament C placed 3cm separately from the surface of the substrate B is heated to 2000 deg.C. Mixture reaction gas D of CH4 and H2 is introduced from the top of the tube A, vapor precipitation reaction is executed, thereby forming a diamond layer of mean thickness.

Description

【発明の詳細な説明】 〔産業上の利用分野) この発明は、すぐれた電気絶縁性および放熱性を有し、
かつ半導体チップとのろう付け性および形成回路との密
着性にもすぐれた半導体装置のダイボンディング用基板
に関するものである。
[Detailed description of the invention] [Industrial application field] This invention has excellent electrical insulation and heat dissipation properties,
The present invention also relates to a substrate for die bonding of semiconductor devices which has excellent brazing properties with semiconductor chips and excellent adhesion with formed circuits.

〔従来の技術〕[Conventional technology]

一般に、半導体装置のダイボンディング用基板としては
、特開昭81−30042号公報に記載されるように、
Fe−42%Niの組成を有する4270イや、Fe−
29%Ni−17%Coの組成を有するコバールなどの
高Ni含有のFe系合金製本体の半導体チップろう付け
面および回路形成面側を、電気絶縁性を確保する目的で
AfI203.BeO。
Generally, as a substrate for die bonding of a semiconductor device, as described in Japanese Patent Application Laid-Open No. 81-30042,
4270I with a composition of Fe-42%Ni, Fe-
The semiconductor chip brazing surface and circuit forming surface of the main body made of a high Ni-containing Fe-based alloy such as Kovar having a composition of 29% Ni-17% Co are coated with AfI203. BeO.

SiC,A#N、あるいは5t3N4などからなる平均
層厚=3〜15μmのセラミックス層で被覆してなるも
のが広く用いられている。
Those coated with a ceramic layer made of SiC, A#N, 5t3N4, etc. and having an average layer thickness of 3 to 15 μm are widely used.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

一方、近年の電子機器の高性能化および軽薄短小化に伴
い、半導体装置の集積回路も高密度化する傾向にあり、
この結果、例えば基板と半導体チップ間の電気絶縁性お
よび熱伝導性に問題が生じるようになっている。すなわ
ち、集積回路の高密度化に伴い、基板のセラミックス層
が半導体チップや、これに形成された回路との間でコン
デンサ化し、集積回路に電気的悪影響を及ぼすようにな
るものであり、これは、前記セラミック層が高い誘電率
をもっためで、このような問題点を解決するためには、
セラミックス層を20μs以上の厚さに厚くする必要が
ある。
On the other hand, in recent years, as electronic devices have become more sophisticated, lighter, thinner, and smaller, the integrated circuits of semiconductor devices are also becoming more dense.
As a result, problems arise, for example, in electrical insulation and thermal conductivity between the substrate and the semiconductor chip. In other words, as the density of integrated circuits increases, the ceramic layer of the substrate becomes a capacitor between the semiconductor chip and the circuits formed on it, which has a negative electrical effect on the integrated circuit. This is because the ceramic layer has a high dielectric constant, and in order to solve this problem,
It is necessary to thicken the ceramic layer to a thickness of 20 μs or more.

しかし、基板におけるセラミックス層を厚くすると、放
熱性が著しく低下し、高温のために半導体装置が十分機
能しなくなるという問題が生じるようになる。
However, if the ceramic layer in the substrate is made thicker, the heat dissipation performance will be significantly reduced, causing the problem that the semiconductor device will no longer function adequately due to the high temperature.

〔課題を解決するための手段〕[Means to solve the problem]

そこで、本発明者等は、上述のような観点から、放熱性
および電気絶縁性にすぐれた半導体装置のダイボンディ
ング用基板を開発すべく研究を行なった結果、上記の従
来ダイボンディング用基板におけるセラミックス層を、
同じく半導体チップとのろう付け性および形成回路との
密着性にすぐれ、かつ放熱性および電気絶縁性にすぐれ
たダイヤモンド層に代え、この場合ダイヤモンド層と基
板本体を構成する上記の高Ni含有のFe系合金とは密
着性が著しく悪く、かつダイヤモンドの気相析出速度も
著しく遅いが、前記高Ni含有のFe系合金製本体のろ
う付け面および回路形成面に、例えばスパッタリング法
などにより形成したW、 Mo 、 TB 、 Nb 
、またはHrからなる高融点金属層を介して、例えば化
学蒸着法によりダイヤモンドを気相析出せしめると、速
い析出速度でダイヤモンド層が形成されるようになり、
しかもこのダイヤモンド層は前記高融点金属層を介して
著しく強固に高Nl含有のFe系合金製本体に接合する
ようになることから、この結果のダイボンディング用基
板は、前記ダイヤモンド層が基板本体から剥離すること
が皆無で、かつ前記ダイヤモンド層によってすぐれた放
熱性と電気絶縁性が確保されるようになり、信頼性のき
わめて高いものとなるという知見を得たのである。
Therefore, from the above-mentioned viewpoint, the present inventors conducted research to develop a substrate for die bonding of semiconductor devices with excellent heat dissipation and electrical insulation properties, and as a result, they found that layer,
In place of the diamond layer, which also has excellent brazing properties with the semiconductor chip and adhesion with the formed circuit, as well as excellent heat dissipation and electrical insulation properties, in this case, the above-mentioned high Ni-containing Fe, which constitutes the diamond layer and the substrate body, is used. The adhesion with the alloy is extremely poor, and the rate of vapor phase precipitation of diamond is also extremely slow. , Mo, TB, Nb
When diamond is deposited in a vapor phase by, for example, chemical vapor deposition through a high melting point metal layer made of Hr or Hr, a diamond layer is formed at a high deposition rate,
Moreover, this diamond layer is extremely strongly bonded to the high Nl-containing Fe-based alloy main body through the high melting point metal layer. They found that there is no peeling, and the diamond layer ensures excellent heat dissipation and electrical insulation, resulting in extremely high reliability.

この発明は、上記知見にもとづいてなされたものであっ
て、高Ni含有のFe系合金製本体の半導体チップろう
付け面および回路形成面側に、平均層厚:Q、Ql〜1
μmを有するW、Mo、Ta。
This invention was made based on the above knowledge, and the average layer thickness: Q, Ql~1
W, Mo, Ta with μm.

Nb、またはHrからなる高融点金属層を介して、平均
層厚:0.1〜204のダイヤモンド層を積層形成して
なる電気絶縁性および放熱性のすぐれた半導体装置のダ
イボンディング用基板に特徴を有するものである。
Features of a substrate for die bonding of semiconductor devices with excellent electrical insulation and heat dissipation properties, which is formed by laminating diamond layers with an average layer thickness of 0.1 to 204 through a high melting point metal layer made of Nb or Hr. It has the following.

なお、この発明の基板において、高融点金属層の平均層
厚を0.01〜1−と限定したのは、その平均層厚が0
.Ol−未満では、ダイヤモンド層を厚さ均一に、かつ
密着性よく形成することができず、一方その平均層厚が
1μmを越えても作用効果は飽和するだけであって、生
産性および放熱性の点からは不利となるという理由から
であり、またダイヤモンド層は、これ自体熱伝導率が約
5cal/備・see ・℃と大きく、−万態膨張係数
が2.3×10’/”Cと小さく、したがって放熱性に
すぐれると共に、半導体チップとの整合性にもすぐれ、
さらに誘電率も5.88 (500−3000Hz)と
小さいので十分な電気絶縁性を示すが、その平均層厚が
O,la未満では所望の放熱性、整合性、および電気絶
縁性を確保することができず、一方その平均層厚を20
μmを越えて厚くしても、前記作用効果が飽和し、より
一層の向上効果はみられないことから、その平均層厚を
0.1〜20uと定めた。
In addition, in the substrate of this invention, the average layer thickness of the high melting point metal layer is limited to 0.01 to 1-1.
.. If it is less than 1 μm, it will not be possible to form a diamond layer with a uniform thickness and good adhesion, while even if the average layer thickness exceeds 1 μm, the effect will only be saturated and the productivity and heat dissipation will be reduced. This is because it is disadvantageous from the point of view of It is small and therefore has excellent heat dissipation and compatibility with semiconductor chips.
Furthermore, since the dielectric constant is as small as 5.88 (500-3000Hz), it exhibits sufficient electrical insulation, but if the average layer thickness is less than O.la, it is difficult to ensure the desired heat dissipation, consistency, and electrical insulation. On the other hand, the average layer thickness is 20
Even if the thickness exceeds .mu.m, the above-mentioned effects are saturated and no further improvement is observed, so the average layer thickness was set at 0.1 to 20 u.

また、上記の高融点金属層は、通常のスパッタリング法
や化学蒸着法などによって形成し、さらに上記のダイヤ
モンド層は、通常の化学蒸着法やプラズマ化学蒸着法1
、さらに光化学蒸着法などによって形成すればよい。
Further, the above-mentioned high melting point metal layer is formed by a normal sputtering method or a chemical vapor deposition method, and the above-mentioned diamond layer is formed by a normal chemical vapor deposition method or a plasma chemical vapor deposition method.
, and may be further formed by a photochemical vapor deposition method or the like.

さらに、この発明の基板において、基板本体を構成する
高Ni含有のFe系合金としては、上記の4270イや
コバールのほかに、半導体チップやセラミックケースの
熱膨張係数に近い熱膨張係数を有するものであればよく
、高Ni鋳鉄の適用も可能である。
Furthermore, in the substrate of the present invention, in addition to the above-mentioned 4270I and Kovar, the high Ni-containing Fe-based alloy constituting the substrate body may be one having a coefficient of thermal expansion close to that of a semiconductor chip or a ceramic case. Any material is acceptable, and high Ni cast iron can also be used.

〔実 施 例〕〔Example〕

つぎに、この発明の基板を実施例により具体的に説明す
る。
Next, the substrate of the present invention will be specifically explained using examples.

基板本体として、平面寸法: ummX25mm、厚さ
二〇、I1mの寸法をもった4270イおよびコバール
製圧延板材を用意し、ついで、これらの圧延板材の片面
に、通常のスパッタリング法にて、それぞれ第1表に示
される平均層厚の高融点金属層を形成し、引続いて第1
図に概略説明図で示される熱電子放射材法による化学蒸
着装置の石英反応管A内に、前記の高融点金属層形成の
基板本体Bを前記高融点金属層を上側にして装入し、反
応管A内を真空脱気した後、前記基板本体Bの表面から
30I11離れて置かれた金属タングステンフィラメン
トCを2000℃に加熱し、反応管Aの頂部よりC10
とHの混合反応ガスD <0M4/H2−容量比で1/
99)を炉内圧力を20トルに保持しながら、300 
ml/mlnの割合で導入し、気相析出反応をそれぞれ
所定時間行なわしめて、第1表に示される平均層厚のダ
イヤモンド層を形成することによって本発明基板1〜2
4をそれぞれ製造した。
As the substrate body, rolled plate materials made of 4270 and Kovar with planar dimensions: umm x 25 mm, thickness 20 mm, and I1 m were prepared. Next, one side of each of these rolled plate materials was coated with a sputtering method using a normal sputtering method. A high melting point metal layer having an average layer thickness shown in Table 1 is formed, and then a first
Into a quartz reaction tube A of a chemical vapor deposition apparatus using the thermionic radiation material method shown in the schematic explanatory diagram in FIG. After evacuating the inside of the reaction tube A, a metal tungsten filament C placed 30I11 away from the surface of the substrate main body B is heated to 2000°C, and C10 is heated from the top of the reaction tube A.
and H mixed reaction gas D <0M4/H2-volume ratio 1/
99) at 300 Torr while maintaining the furnace pressure at 20 Torr.
ml/mln, and conduct a vapor phase precipitation reaction for a predetermined time to form a diamond layer having an average layer thickness shown in Table 1.
4 were produced respectively.

また、比較の目的で、同じ<4270イおよびコバール
製板材を基板本体とし、これの片面に通常の化学蒸着法
にて、同じく第1表に示される平均層厚のセラミック層
を形成することによって従来基板1〜lOをそれぞれ製
造した。
For comparison purposes, we used the same <4270 I and Kovar plate material as the main body of the substrate, and formed a ceramic layer on one side of this using the usual chemical vapor deposition method, with the average layer thickness shown in Table 1. Conventional substrates 1 to 1O were each manufactured.

つぎに、この結果得られた各種の基板について、電気絶
縁性を評価する目的で絶縁耐圧試験を行ない、またダイ
ヤモンド層およびセラミックス層の密着性を評価する目
的でスクラッチテストを行なった。
Next, with respect to the various substrates obtained as a result, a dielectric strength test was conducted for the purpose of evaluating electrical insulation properties, and a scratch test was conducted for the purpose of evaluating the adhesion between the diamond layer and the ceramic layer.

なお、絶縁耐圧試験は、JIS−C2110にもとづき
、直径;61μmの上下の電極間に基板をはさみ、これ
に500vの電圧を印加し、1時間保持の条件で行ない
、この間の通電の有無を観察し、第1表に示した。
In addition, the dielectric strength test was conducted based on JIS-C2110 by sandwiching the board between upper and lower electrodes with a diameter of 61 μm, applying a voltage of 500 V to this, and holding it for 1 hour, observing whether or not electricity was applied during this time. and shown in Table 1.

また、スクラッチテストは、通常のスクラッチテスター
を用い、荷重スピード: ION/s1nの条件で行な
い、臨界荷重を測定したが、第1表には10回の試験の
平均値として示した。
The scratch test was carried out using a normal scratch tester at a loading speed of ION/s1n to measure the critical load, which is shown in Table 1 as the average value of 10 tests.

〔発明の効果〕〔Effect of the invention〕

第1表に示される結果から、本発明基板1〜24は、い
ずれもダイヤモンド層が従来基板1〜lOにおけるセラ
ミック層と同等のすぐれた密着性を有し、一方電気絶縁
性については従来基板に比して一段とすぐれたものであ
ることが明らかである。
From the results shown in Table 1, it can be seen that the diamond layer of substrates 1 to 24 of the present invention has excellent adhesion comparable to that of the ceramic layer in conventional substrates 1 to 1O, while the electrical insulation properties are superior to those of the conventional substrates. It is clear that it is far superior.

なお、高融点金属層の形成がない4270イおよびコバ
ール製板材へのダイヤモンド層の形成を試みたが、この
場合ダイヤモンドの析出はきわめて遅く、実用規模でダ
イヤモンド層を形成することができないものであった。
In addition, we attempted to form a diamond layer on 4270I and Kovar plates, which do not have a high-melting point metal layer, but in this case, diamond precipitation was extremely slow and it was impossible to form a diamond layer on a practical scale. Ta.

上述のように、この発明の基板は、高Ni含有のFe系
合金製本体の半導体チップろう付け面および回路形成面
側に高融点金属層を介して強固に接合したダイヤモンド
層によって、すぐれた電気絶縁性および放熱性が確保さ
れ、かつこのダイヤモンド層は半導体チップとのろう付
け性および形成回路との密着性にもすぐれているので、
高い発熱を伴なう高集積度の半導体装置のダイボンディ
ング用基板として十分実用に供することができるなど工
業上有用な特性を有するのである。
As described above, the substrate of the present invention has excellent electrical properties due to the diamond layer firmly bonded to the semiconductor chip brazing surface and circuit forming surface of the main body made of a high Ni-containing Fe-based alloy via a high melting point metal layer. Insulation and heat dissipation properties are ensured, and this diamond layer also has excellent brazing properties with semiconductor chips and adhesion with formed circuits.
It has industrially useful properties such that it can be put to practical use as a die bonding substrate for highly integrated semiconductor devices that generate a high amount of heat.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は熱電子放射材法によるダイヤモンド層の形成装
置を示す概略説明図である。 A・・・石英反応管、    B・・・基板本体、C・
・・金属タングステンフィラメント、D・・・反応ガス
。  “
FIG. 1 is a schematic diagram showing an apparatus for forming a diamond layer using the thermionic emitter method. A...Quartz reaction tube, B...Substrate body, C...
...Metal tungsten filament, D...Reactive gas. “

Claims (1)

【特許請求の範囲】[Claims] (1)高Ni含有のFe系合金製本体の半導体チップろ
う付け面および回路形成面側に、平均層厚:0.01〜
1μmを有するW、Mo、Ta、Nb、またはHfから
なる高融点金属層を介して、平均層厚:0.1〜20μ
mのダイヤモンド層を積層形成してなる半導体装置のダ
イボンディング用基板。
(1) Average layer thickness: 0.01~
Through a high melting point metal layer made of W, Mo, Ta, Nb, or Hf having a thickness of 1 μm, the average layer thickness is 0.1 to 20 μm.
A substrate for die bonding of a semiconductor device, which is formed by stacking m diamond layers.
JP4158888A 1988-02-24 1988-02-24 Board for die bonding semiconductor device Pending JPH01216560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4158888A JPH01216560A (en) 1988-02-24 1988-02-24 Board for die bonding semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4158888A JPH01216560A (en) 1988-02-24 1988-02-24 Board for die bonding semiconductor device

Publications (1)

Publication Number Publication Date
JPH01216560A true JPH01216560A (en) 1989-08-30

Family

ID=12612582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4158888A Pending JPH01216560A (en) 1988-02-24 1988-02-24 Board for die bonding semiconductor device

Country Status (1)

Country Link
JP (1) JPH01216560A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02175694A (en) * 1988-12-27 1990-07-06 Aisin Seiki Co Ltd Diamond coating
JP2008280198A (en) * 2007-05-09 2008-11-20 Nachi Fujikoshi Corp Diamond film-coated member and its production method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02175694A (en) * 1988-12-27 1990-07-06 Aisin Seiki Co Ltd Diamond coating
JP2008280198A (en) * 2007-05-09 2008-11-20 Nachi Fujikoshi Corp Diamond film-coated member and its production method

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