JPH0121611B2 - - Google Patents
Info
- Publication number
- JPH0121611B2 JPH0121611B2 JP57130475A JP13047582A JPH0121611B2 JP H0121611 B2 JPH0121611 B2 JP H0121611B2 JP 57130475 A JP57130475 A JP 57130475A JP 13047582 A JP13047582 A JP 13047582A JP H0121611 B2 JPH0121611 B2 JP H0121611B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- layer
- layers
- conductor layers
- printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 46
- 239000012212 insulator Substances 0.000 claims description 7
- 238000004804 winding Methods 0.000 claims description 4
- 229910000859 α-Fe Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 14
- 239000011229 interlayer Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 15
- 238000007639 printing Methods 0.000 description 6
- 239000000843 powder Substances 0.000 description 5
- 239000000696 magnetic material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
Description
本発明は積層インダクタに関し、特に内部容量
の小さい積層インダクタに関する。
印刷法等による厚膜法や蒸着法、スパツタ法等
による薄膜法で製作される積層インダクタは公知
である。印刷法による積層インダクタは例えば非
磁性セラミツクや磁性フエライトなどのうち、電
気絶縁性のものの粉末をペースト化し、又、銀・
銀―パラジウムなどの金属粉末をペースト化し、
絶縁体ペーストを薄膜状に印刷して絶縁体層を形
成し、その面に金属粉末ペーストを線状に印刷し
てほぼ半ターン分の導体を形成し、この導体の一
端を除いて第2の絶縁体層を印刷し、さらにその
上に前記導体の露出端に接続するほぼ半ターン分
の第2の導体を印刷し、以下同様の工程を所定回
数反復して絶縁体中で垂直方向に重畳しながら周
回するコイル状導体パターンを形成し、こうして
得た積層体を焼成して一体化した焼結積層体とす
る方法である。また蒸着法は上記と同じような工
程で絶縁体と導体とを交互に蒸着して行く方法で
ある。いずれにしても、上記積層インダクタは同
じ平面に導体の渦巻きパターンを形成してその一
端を次の層の渦巻き導体へ結合する場合のような
広い面積で導体層が対向することがなく、従つて
インダクタの内部容量が少ないという特徴を有す
る。しかしながら、印刷または蒸着で形成される
導体は従来の丸導線とは違つて幅のある層である
から、各層でわずかに1ターンでも垂直方向に重
畳している導体のターン間にはなお相当大きい容
量が形成される。例えば第9図に示すようにイン
ダクタンス値がL(μH)で導体の各ターン間に形
成される容量を△C(pF)とすると、自己共振周
波数は
The present invention relates to a laminated inductor, and particularly to a laminated inductor with a small internal capacitance. 2. Description of the Related Art Laminated inductors manufactured by a thick film method such as a printing method, a thin film method such as a vapor deposition method, or a sputtering method are well known. Multilayer inductors made by the printing method are made by pasting electrically insulating powders such as non-magnetic ceramics and magnetic ferrites, and
Metal powder such as silver-palladium is made into a paste,
An insulating layer is formed by printing a thin film of insulating paste, and a conductor of approximately half a turn is formed by printing metal powder paste in a line on that surface. An insulator layer is printed, and a second conductor for approximately half a turn is printed on it to connect to the exposed end of the conductor, and the same process is repeated a predetermined number of times to overlap vertically in the insulator. In this method, a coiled conductor pattern is formed while rotating, and the thus obtained laminate is fired to form an integrated sintered laminate. Further, the vapor deposition method is a method in which an insulator and a conductor are alternately vapor-deposited in the same steps as above. In any case, in the laminated inductor described above, the conductor layers do not face each other over a large area, as is the case when forming a spiral pattern of conductors on the same plane and connecting one end to the spiral conductor of the next layer. It has the characteristic that the internal capacitance of the inductor is small. However, unlike conventional round conductors, printed or vapor-deposited conductors are formed in wide layers, so even if there is just one turn in each layer, there is still a considerable gap between vertically overlapping turns of the conductor. A capacitance is formed. For example, as shown in Figure 9, if the inductance value is L (μH) and the capacitance formed between each turn of the conductor is △C (pF), the self-resonant frequency is
【式】となる。従つて、△Cが
大きいと高周波で使用するのに適さなかつた。
従つて本発明は上記欠点のない積層インダクタ
を提供することを目的とする。本発明は積層イン
ダクタにおいて少くとも隣り合つた導体ターンを
食違い関係に配置することにより重畳部分を最低
限におさえて内部容量を最低にしたことを特徴と
する。これにより薄層状の導体を用いる積層イン
ダクタは純粋のインダクタに近い形で使用できる
ものとする。
以下本発明の実施例を図面を参照して詳細に説
明する。以下の例において、絶縁体は磁性フエラ
イト粉末を用い、導体は金属粉末を用いるものと
し、印刷法によるものとする。これらは公知であ
るから説明を省略し、本発明の理解に必要な部分
のみを説明する。なお本発明は蒸着法、スパツタ
法等の薄膜形成法によつても実現しうることは明
らかであろう。
第1図ないし第7図は本発明の実施例による積
層インダクタとその製造方法を示す工程図であ
る。第1図に示すように、電気絶縁性磁性体層1
を印刷により用意し、その面に、線状導体2を印
刷する。導体2の引出端T1は磁性体1の下辺部
へ引出しておく。第2図の工程に移つて、導体2
の一端が露出するようにして磁性体層3を印刷
し、導体2の露出端に接続する導体4をL字形に
印刷する。次に、第3図に示すように導体4の一
端が露出するようにして積層体の上半分に磁性体
層5を印刷し、次いで導体4の露出端に接続する
L字形の導体6を印刷する。この場合に導体6は
下側の導体2と交差した後、それと重畳すること
なく平行して延びていることが大切である。これ
により導体間の静電容量が減じる。第4図の工程
において、導体6の一端を露出したまま磁性体層
7を印刷し、次いで下側の導体4と平行する導体
8をL字形に印刷することにより導体6を延長さ
せる。第5図に示すように、今度は積層体の上側
部分(図で見て)に磁性体層9を印刷し、さらに
L字形の導体10を導体8の一端に接続するよう
に印刷する。この場合にも導体10は下側の導体
6と交差した上平行に延びている。なお導体2と
導体10とは重畳しないようにすることが望まし
いが、間に絶縁性磁性体3,5,7,9が介在し
ているため、重畳位置にあつても結合容量は非常
に小さくなるので問題がない。導体10の一端は
積層体の上辺に引出して引出端T2とする。最後
に第6図に示すように積層体表面に磁性体11を
印刷して積層を終る。得られた積層体を焼成炉に
入れて高温焼成して一体構造の焼結体とする。第
7図のように焼結体の上下辺に露出する引出端
T1,T2に接続する外部端子T1′,T2′を例えば導
電ペーストの塗布及び低温焼付けによつて形成し
て、本発明の積層インダクタを完成する。第8図
はその斜視図である。なお積層数は任意に変更し
うるし、また磁性体層の一部を非磁性セラミツク
材で置換えることも可能である。例えば開磁路形
積層インダクタに変更するには導体に囲まれた部
分のみを磁性体にし、他の部分はAl2O3やTiO2な
どのセラミツク材にする。
以上の説明から明らかなように、外部端子
T1′から始つてT2′に至る導体路は少くとも隣り合
つたターン間で重畳が生じない周回パターンを有
する巻線を形成する。このため巻線のターン間に
介在する磁性体をはさんで隣り合つたターンを形
成する導体層の間には容量結合が生じる可能性が
大きく減じる。又、本発明の積層インダクタは若
干の印刷パターンの組合せで製造することができ
るから、工程は単純化されるなど積層インダクタ
の利点を何ら失うことなく特性の良いインダクタ
を提供できるものである。[Formula] becomes. Therefore, if ΔC is large, it is not suitable for use at high frequencies. It is therefore an object of the present invention to provide a laminated inductor that does not have the above-mentioned drawbacks. The present invention is characterized in that in a laminated inductor, at least adjacent conductor turns are arranged in a staggered relationship to minimize overlapping portions and thereby minimize internal capacitance. As a result, a laminated inductor using a thin layered conductor can be used in a form close to a pure inductor. Embodiments of the present invention will be described in detail below with reference to the drawings. In the following example, magnetic ferrite powder is used for the insulator, metal powder is used for the conductor, and the printing method is used. Since these are well known, their explanation will be omitted, and only the parts necessary for understanding the present invention will be explained. Note that it is clear that the present invention can also be realized by thin film forming methods such as vapor deposition and sputtering. 1 to 7 are process diagrams showing a laminated inductor and its manufacturing method according to an embodiment of the present invention. As shown in FIG. 1, an electrically insulating magnetic layer 1
is prepared by printing, and the linear conductor 2 is printed on its surface. The lead-out end T 1 of the conductor 2 is drawn out to the lower side of the magnetic body 1 . Moving on to the process shown in Figure 2, conductor 2
The magnetic layer 3 is printed so that one end of the conductor 2 is exposed, and the conductor 4 connected to the exposed end of the conductor 2 is printed in an L-shape. Next, as shown in FIG. 3, a magnetic layer 5 is printed on the upper half of the laminate so that one end of the conductor 4 is exposed, and then an L-shaped conductor 6 is printed to connect to the exposed end of the conductor 4. do. In this case, it is important that the conductor 6 crosses the lower conductor 2 and then extends parallel to it without overlapping it. This reduces the capacitance between the conductors. In the process shown in FIG. 4, a magnetic layer 7 is printed with one end of the conductor 6 exposed, and then a conductor 8 parallel to the lower conductor 4 is printed in an L shape to extend the conductor 6. As shown in FIG. 5, a magnetic layer 9 is now printed on the upper part of the stack (as seen in the figure), and an L-shaped conductor 10 is also printed so as to be connected to one end of the conductor 8. In this case as well, the conductor 10 extends above and parallel to the lower conductor 6. Note that it is desirable that the conductors 2 and 10 do not overlap, but since the insulating magnetic materials 3, 5, 7, and 9 are interposed between them, the coupling capacitance is very small even if they are in an overlapping position. So there is no problem. One end of the conductor 10 is drawn out to the upper side of the laminate to form a drawn-out end T2 . Finally, as shown in FIG. 6, a magnetic material 11 is printed on the surface of the laminate to complete the lamination. The obtained laminate is placed in a firing furnace and fired at a high temperature to form a sintered body having an integral structure. The pull-out end exposed on the top and bottom sides of the sintered body as shown in Figure 7
External terminals T 1 ′ and T 2 ′ connected to T 1 and T 2 are formed by, for example, applying a conductive paste and baking at a low temperature to complete the multilayer inductor of the present invention. FIG. 8 is a perspective view thereof. Note that the number of laminated layers can be changed arbitrarily, and it is also possible to replace a part of the magnetic layer with a non-magnetic ceramic material. For example, to change to an open magnetic path multilayer inductor, only the part surrounded by the conductor should be made of magnetic material, and the other parts should be made of ceramic material such as Al 2 O 3 or TiO 2 . As is clear from the above explanation, the external terminal
The conductor path starting from T 1 ' and ending at T 2 ' forms a winding with a circumferential pattern in which at least no overlap occurs between adjacent turns. Therefore, the possibility that capacitive coupling will occur between the conductor layers forming adjacent turns with the magnetic material interposed between the turns of the winding wire is greatly reduced. Furthermore, since the laminated inductor of the present invention can be manufactured by combining several printed patterns, it is possible to provide an inductor with good characteristics without losing any of the advantages of the laminated inductor, such as simplified processes.
第1図ないし第7図は本発明の積層インダクタ
の順次製造工程及び構造を示す平面図、第8図は
完成した積層インダクタの斜視図、及び第9図は
コイルの内部容量を説明する概念図である。図中
主な部分は次の通りである。
1,3,5,7,9,11:磁性体層、2,
4,6,8,10:線状導体。
Figures 1 to 7 are plan views showing the sequential manufacturing process and structure of the laminated inductor of the present invention, Figure 8 is a perspective view of the completed laminated inductor, and Figure 9 is a conceptual diagram explaining the internal capacitance of the coil. It is. The main parts in the figure are as follows. 1, 3, 5, 7, 9, 11: magnetic layer, 2,
4, 6, 8, 10: Linear conductor.
Claims (1)
層体であつて、前記導体層が前記絶縁体層の縁部
を介して接続されて前記絶縁体層の層間から層間
へと周回する巻線を形成するように端部で接続さ
れている積層インダクタにおいて、前記導体層は
各層で約半ターン分のコイルを形成し、前記導体
層が接続された縁部を有する絶縁体層はほぼ同一
形状に形成され且つ前記縁部は前記積層体の対向
した2つの個所に交互に形成されており、前記巻
線の少くとも上下に隣接した部分の大部分は互に
層面方向に食い違つていることを特徴とする積層
インダクタ。 2 絶縁体層は磁性フエライトである特許請求の
範囲第1項記載の積層インダクタ。[Scope of Claims] 1. An alternately laminated body of a plurality of insulator layers and a plurality of conductor layers, wherein the conductor layers are connected via the edges of the insulator layers so that there is no interlayer connection between the insulator layers. In a laminated inductor in which the conductor layers are connected at their ends to form a winding that goes around from layer to layer, the conductor layers form a coil of about half a turn in each layer, and the edges to which the conductor layers are connected The insulating layers having substantially the same shape are formed, and the edge portions are formed alternately at two opposing locations of the laminate, and at least most of the vertically adjacent portions of the winding wire are formed in substantially the same shape. A laminated inductor characterized by being staggered in the direction of the layer planes. 2. The multilayer inductor according to claim 1, wherein the insulating layer is made of magnetic ferrite.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13047582A JPS5922303A (en) | 1982-07-28 | 1982-07-28 | Laminated inductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13047582A JPS5922303A (en) | 1982-07-28 | 1982-07-28 | Laminated inductor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5922303A JPS5922303A (en) | 1984-02-04 |
JPH0121611B2 true JPH0121611B2 (en) | 1989-04-21 |
Family
ID=15035131
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13047582A Granted JPS5922303A (en) | 1982-07-28 | 1982-07-28 | Laminated inductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5922303A (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0729610Y2 (en) * | 1988-06-09 | 1995-07-05 | 株式会社村田製作所 | Composite inductor |
JPH0656812B2 (en) * | 1990-10-11 | 1994-07-27 | 東光株式会社 | Multilayer inductor and manufacturing method thereof |
JP2520622Y2 (en) * | 1990-11-20 | 1996-12-18 | 太陽誘電株式会社 | Multilayer chip inductor |
JPH0634216U (en) * | 1992-10-02 | 1994-05-06 | 太陽誘電株式会社 | Multilayer chip inductor |
CN105453200B (en) | 2013-07-29 | 2017-11-10 | 株式会社村田制作所 | Multilayer coil |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5541012A (en) * | 1978-09-18 | 1980-03-22 | Hitachi Ltd | Gain control circuit |
JPS5540577B2 (en) * | 1974-06-10 | 1980-10-18 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS603528Y2 (en) * | 1978-09-09 | 1985-01-31 | ヤマハ株式会社 | Multilayer etching coil |
-
1982
- 1982-07-28 JP JP13047582A patent/JPS5922303A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5540577B2 (en) * | 1974-06-10 | 1980-10-18 | ||
JPS5541012A (en) * | 1978-09-18 | 1980-03-22 | Hitachi Ltd | Gain control circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS5922303A (en) | 1984-02-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3197022B2 (en) | Multilayer ceramic parts for noise suppressor | |
JPH04150011A (en) | Composite electronic component | |
GB2045540A (en) | Electrical inductive device | |
JP2004128506A (en) | Stacked coil component and its manufacturing method | |
JPH03241862A (en) | Laminated composite component | |
JPS5917705A (en) | Layer-built plate antenna coil | |
JPS6050331B2 (en) | Inductance element and its manufacturing method | |
JP2655657B2 (en) | Structure of laminated application parts | |
JPH0121611B2 (en) | ||
US6466120B1 (en) | Laminated inductor and method of producing the same | |
JP3444226B2 (en) | Multilayer inductor | |
JPS6228891B2 (en) | ||
JPH0777175B2 (en) | Laminated transformer | |
JPH0358164B2 (en) | ||
JPH04243104A (en) | Laminated chip transformer | |
JPH0115159Y2 (en) | ||
JPH0365645B2 (en) | ||
JPH0447950Y2 (en) | ||
JPS6229885B2 (en) | ||
JPH04140909A (en) | Composite type lc filter | |
JPH07106896A (en) | Band pass filter | |
JPS6031242Y2 (en) | LC composite parts | |
JPS5853807A (en) | Composite chip component of rolled type | |
JPS5922304A (en) | Laminated transformer | |
JP2831392B2 (en) | Laminated bifilar winding transformer |