JPH01215043A - Working method of through-hole to inter-layer film - Google Patents

Abstract

PURPOSE:To control the depth and spread of a tapered section, and to improve the inferior coverage of a wiring continuity section easy to be generated in a through-hole in a stepped lower section particularly by depositing a metal into the through-hole while forming the tapered section. CONSTITUTION:A wiring layer 1 on a foundation substrate 9 is buried, an inter- layer film 2, the surface of which is flattened and which is composed of, an organic insulator, is shaped, and the inter-layer film 2 is worked and a through- hole 10 reaching the wiring layer 1 is bored. A metallic projection 5a is formed into the through-hole 10 as a continuity section by depositing a metal onto the whole surface including the through-hole 10, and a second organic insulating film 6 is shaped onto the whole surface so as to bury the metallic projection 5a. The second organic insulating film 6 on the inter-layer film 2 is removed selectively, and a metal 5b on the exposed inter-layer film 2 is gotten rid of while a taper 11 is formed to the inlet of the through-hole 10 under the state in which the metallic projection 5a is left into the through-hole 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a through hole processing method for forming a multilayer interconnection structure using an organic resin as an interlayer film.

[Conventional technology]

IC's? With the increasing integration of fjb, the wiring area formed in multiple layers is getting smaller and smaller, and in order to realize this, the through holes that become the conductive part of the interlayer film are becoming smaller. It is in. Regarding the hole processing technique when the interlayer film is an inorganic film such as 5iO1, for example, Nikkei Microdevice May 1986 issue 957 describes a technique for filling the holes by electroless plating or the like. However, sufficient technology has not yet been established for organic interlayer films that are thick. Therefore, when using through holes with high aspect ratios due to miniaturization, the problem is how to achieve conduction. Conventional techniques for through-holes for obtaining conductivity include tapered through-hole technology and 12113 foot 7 type through-hole technology.

[Problem to be solved by the invention]

(1: The illll taber through-hole technology described above is a method that uses a combination of isotropic and anisotropic etching to widen the diameter of the through-hole formed in the interlayer film by tapering it. This improves the coverage within the through-hole of the upper layer wiring connected to the upper layer wiring.

As shown in Fig. 17, this tapered through hole is
When there is a step in the base substrate 9, the depth Y of the through hole at the bottom of the step is compared to the depth Y of the through hole at the top of the step because the surface of the interlayer insulating film 2 made of organic resin is flat. In a through hole of the same diameter, the diameter X of the lower step becomes smaller than the diameter XI of the upper step.

FIG. 18 shows a state in which the through hole shown in FIG. 17 is shifted to the right due to the photoresist mask shift, resulting in a gap. In order to prevent such openings, it is necessary to increase the area of the trap lower layer AA wiring, and therefore, it is necessary to make the pitch of the wiring larger than that without a taper, which is undesirable in terms of integration. As shown in Figure 19, the lift-off type through-hole technology of front placement 2+ deposits M (51) with the resist material (7) remaining on the surface of the insulating film where no through holes are formed, and then dissolves and removes the resist. A! is left in the through hole as a part of the conductive part.If there is a step in the base substrate 9 as shown in the row, the aspect ratio of the through hole is <Y, /X,) at the bottom of the step. Because of the height, as shown in the 20th cause, the coverage is poor at the conductive part of the AJ line at the bottom of the step, and disconnection may occur.The invention is intended to overcome this problem. What is its purpose? The purpose is to improve the poor coverage of the interconnection conduction part, which tends to occur in the through-holes at the bottom of the step.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve 22 machines]

Representative I! of the inventions disclosed in this application!
A brief explanation of the main points is as follows.

That is, an interlayer film made of an organic insulator is formed by embedding the wiring layer (lower layer AJ wiring layer) on the base substrate and flattening the surface, and processing this interlayer film to form a through hole (through hole) that reaches the wiring layer. ), and by depositing a metal such as A1 on the entire surface of the hole, a metal protrusion is formed in the hole as a part of the interconnection conductive part, and a metal protrusion is formed on the entire surface so as to embed the protrusion. 2.0 An organic insulating film is formed, and then the organic insulating film is selectively removed, and then the metal on the exposed interlayer film is removed, while the metal protrusion remains in the through-hole. This is to form a taper.

[Effect]

According to the above-mentioned means, the depth and spread of the taper can be controlled by depositing metal in the through hole and creating a taper at the same time. gets better.

[Embodiment 1] FIGS. 1 to 8 show an embodiment of the present invention, and are cross-sectional views of a process in which a two-layer wiring structure is formed on a base substrate. Each step will be explained below.

11'l Lower layer A provided on base semiconductor substrate 9!
The glabellar insulating film 2 is formed by applying (spraying) a thick layer of polyimide resin or the like, which is an organic insulating material, and polymerizing and curing it.

Plasma S for an etch mask on the interlayer insulating film
An i3N4 film 3 is produced and a photoresist film 4 is overlaid (FIG. 1).

(2: Patterning the resist by photo processing,
Through anisotropic dry etching, a through hole (
Through hole) 10. Then Regis)
(Remove 41 (Figure 2).

! 31 Deposit A1 on the entire surface and apply AJ in the through hole.
A protrusion 5a is formed. At this time, the AJ film 5b also covers the S i and N4 films 3 (FIG. 3).

(4) Furthermore, a coated insulating film 6 is formed sufficiently thickly over the entire surface so as to fill the inside of the through hole (FIG. 4).

(5) By asher treatment, Si, N, A1 on film 3
Retract the insulation wi & 6 until 5b is exposed and etch away the AA from the 7th part. At this time, a part of the insulating film and A15a) remain in the through hole 10 (FIG. 5).

(6) By dry etching (anisotropic) and asher processing, the A1 protrusion 5a inside the through hole is exposed and the insulating film 6 is etched on the side 5, and the insulating film at the entrance of the through hole is tapered 1.
1 (Figure 6).

(The 71Si3N4 film 3 is removed by plasma sputtering or the like (FIG. 7).

(By depositing and patterning 81AA, an upper layer A! interconnection 12 is formed which connects to the A1 interconnection layer 1 of the first layer via the A1 protrusion 5a, thereby completing the two-layer wiring structure (FIG. 8) .

According to the embodiments described above, the following effects can be obtained.

In other words, there is a person inside the hole! By providing the protrusions, the deep through hole becomes substantially shallow, and the aspect ratio becomes smaller.The conventional lift-off method can also reduce the aspect ratio, but 1.
A at the bottom of the protrusion! While it is difficult to form a film, in this example, as shown in FIGS. 3 and 4, the area around the An projections is filled with an insulating material (6) to achieve flattening and transparent film formation. In addition to providing a taper of the insulating film in the hole population, the formation of the A1 hole in the upper layer was facilitated.

For the above reasons, the coverage of the interfering section of AJ melting can be improved compared to the conventional method.

[Embodiment 2] Figures 9 to 12 show other embodiments of the present invention, and are cross-sectional views of a process in which a two-layer A1 mausoleum is formed on a substrate having a base step. be.

(In the conductor substrate 13 having 11 base steps, a lower layer A1 arrangement [14at14b is provided at the lower part and upper part of the step, respectively, and the A1 arrangement 1ii14a, 14b is buried and polyimide resin etc. is applied to form an interlayer insulating film 2. Further, on top of that, plasma Si, N, 1il (
3. Layer photoresist 4 (Figure 9).

(21 Using the photoresist described above, the through holes 15 are formed in the interlayer insulating film.
．． Open 16 (Figure 10).

13) Deposit AA17 on the entire surface and apply A! in the through holes 15 and 16 of different depths. Protrusions 18 and 19 are formed (FIG. 11).

(A 41 coating type insulating film 20 is formed on the entire surface to fill the inside of the through hole (FIG. 12).

(5) The edge of the insulating film on the Si, N, and film 3 is set back by an asher process, and then the underlying AJ film is removed (FIG. 13).

(6) After applying a resist having asher resistance (e.g., Si-containing resist) and patterning it to form a mask 21 that extends through the through-holes 15 at the upper part of the base step, asher processing is performed to form the through-holes 15 at the lower part of the step. The inner insulator 20 is etched to the extent that the A1 protrusion 19 underneath is exposed, and a taper 23 is provided at the entrance of the through hole (FIG. 14).

(7) The resist mask 12υ is removed and the entire surface is subjected to an ashing process to form a taper 22 in the through hole 15 at the top of the step.
As the A2 protrusion 18 is exposed, the taper 23 at the bottom of the step is further widened (FIG. 15).

(8) Remove the plasma S isK gland 131 and
Deposition 1 line patterning and upper l- person 1 wiring 24
(Fig. 16).

According to the embodiments described above, the following effects can be obtained.

(1) A in the hole! By providing protrusions and tapers, the aspect ratio is reduced, and the upper J@A
Improving the coverage of the four glands is the same as in the previous embodiment.

(21 In the conventional tapered through hole, when the ground level difference is large, the wiring pitch of the lower layer A1 wiring tends to become large for the reason mentioned above. In the present invention, the inner dimension of the through hole is This method is optimized, that is, can be controlled by mask dimensions.Therefore, since the wiring pitch is determined by the accuracy of mask alignment of the through holes, the wiring pitch can be made smaller than in the conventional method.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof.

For example, it can be carried out by changing the steps of Example 1 or Examples (2) to (5) described above as follows, and further lifting off A1. That is, plus vsi3N
J: The resist (first cause) is patterned, a hole is made in the interlayer insulating film with the Lee resist left intact by anisotropic dry etching, and then AA is deposited and the resist is removed to form a hole in the hole. A1 is formed in a protruding shape only. Even with such a lift-off method, Example 1
The same effects as described above can be obtained.

The present invention is most effective when applied to linear IC products that have a large base level difference and require strong demands for finer wiring.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, in multilayer wiring, the coverage of the upper layer wiring is good in wiring connections through through-holes, and the wiring pitch can be reduced when there is a step difference in the base layer.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 8 are cross-sectional views of a two-layer wiring process showing an embodiment of the present invention. 9 to 16 show another embodiment of the present invention 2j
FIG. 3 is a cross-sectional view of the interconnection process. FIGS. 17 to 20 are partial process cross-sectional views showing an example of a conventional multilayer wiring process. l...lower layer A! Wiring, 2... interlayer insulating film, 3...
P-8i3N48, 4... Photoresist, 5a"
・AA protrusion, 5 b...A, -: Rini luck,
6...S 凰, N, MEMBRANE. Figure 1 Figure 2 Figure 3 Figure 5! Figure 6 @ Figure 7 Figure 9 Figure 11 Figure 13

Claims (1)

[Claims] 1. Form an interlayer film made of an organic insulator with a planarized surface by embedding the wiring layer on the base substrate, process this interlayer film to make a through hole reaching the wiring layer, and By depositing metal on the entire surface including the through hole, a metal protrusion is formed as a conductive part in the through hole, and a second organic insulating film is formed on the entire surface so as to bury the metal protrusion. second on membrane
An interlayer film characterized by selectively removing an organic insulating film, then removing metal on the exposed interlayer film, and forming a taper at the entrance of the through hole while leaving a metal protrusion in the through hole. Through-hole processing method. 2. The interlayer film according to claim 1, wherein the base substrate has a step part, and wiring is embedded above the step part and above the step part, respectively, and an interlayer film made of an organic insulator is formed thereon. Through-hole processing method.