JPH01214779A - Input-voltage detecting circuit - Google Patents

Input-voltage detecting circuit

Info

Publication number
JPH01214779A
JPH01214779A JP63041160A JP4116088A JPH01214779A JP H01214779 A JPH01214779 A JP H01214779A JP 63041160 A JP63041160 A JP 63041160A JP 4116088 A JP4116088 A JP 4116088A JP H01214779 A JPH01214779 A JP H01214779A
Authority
JP
Japan
Prior art keywords
voltage
transistor
resistor
input
reference potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63041160A
Other languages
Japanese (ja)
Other versions
JP2567015B2 (en
Inventor
Naohito Oikawa
尚人 及川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63041160A priority Critical patent/JP2567015B2/en
Publication of JPH01214779A publication Critical patent/JPH01214779A/en
Application granted granted Critical
Publication of JP2567015B2 publication Critical patent/JP2567015B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To prevent erroneous operations during the operation of an IC and to reduce current consumption, by performing transition into an operating mode by the input of a negative voltage, and to prevent the operations of two transistors when the input voltage is at a reference potential. CONSTITUTION:Transistors (Tr)Q1 and Q2 are provided in a semiconductor integrated circuit. The base of the TrQ1 and the emitter of the TrQ2 are connected to reference potential points. An input terminal is connected to the emitter of the TrQ1 through a resistor R3. The emitter of the TrQ1 is connected to the base of the TrQ2 through a resistor R4. The base of the TrQ2 is connected to the reference potential through a resistor R5. Control outputs are obtained from the collectors of the Trs Q1 and Q2. Even if a slight difference occurs in a power source voltage with respect to a peripheral circuit during the operation of an IC, an erroneous operation does not occur and transition into a test mode does not occur. When the input voltage is equal to the reference potential, the two Trs Q1 and Q2 are not operated. Therefore a current does not flow. When a standby mode is set during the operating mode of the semiconductor integrated circuit, the current consumption can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はICの動作モードを切り換える制御電圧を検出
する入力電圧検出回路に関し、特にICにそのICの良
否判定のためのテストに備えたテストモードへの移行を
制御する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an input voltage detection circuit that detects a control voltage for switching the operating mode of an IC, and particularly to a test for preparing an IC for a test to determine the quality of the IC. Control transition to mode.

〔従来の技術〕[Conventional technology]

従来この種の制御を行なうために、本来動作モード制御
用として備えている外部端子に通常の動作では印加され
ない電源電圧を越える電圧を印加したときに、テストモ
ードへ移行する技術がある。
Conventionally, in order to perform this type of control, there is a technique of shifting to a test mode when a voltage exceeding the power supply voltage, which is not applied during normal operation, is applied to an external terminal originally provided for controlling the operation mode.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の電源電圧を越える電圧によりテストモー
ドへ移行する技術では、実際の動作時にテストモードへ
移行してしまう次のような欠点があった。
The above-described conventional technique of shifting to the test mode using a voltage exceeding the power supply voltage has the following drawback in that the mode shifts to the test mode during actual operation.

すなわちテストモードを備えた第1のICとこの第1の
ICに制御電圧を与える第2のICの電源電圧が別の電
源から与えられている場合で第1のICへの電源電圧よ
り第2のICの電源電圧が高くなりかつ第2のICから
高いレベルの制御電圧を第1のICへ印加したとき、第
1のICの入力端子には、第1のICの電源より高い電
圧が印加されるために、第1のICが誤動作してテスト
モードへ移行してしまう欠点があった。
In other words, if the power supply voltages of a first IC equipped with a test mode and a second IC that provides a control voltage to the first IC are supplied from different power supplies, the power supply voltage to the first IC is higher than that of the second IC. When the power supply voltage of the second IC increases and a high level control voltage is applied from the second IC to the first IC, a voltage higher than the power supply of the first IC is applied to the input terminal of the first IC. Therefore, there is a drawback that the first IC malfunctions and enters the test mode.

〔発明の従来技術に対する相違点〕[Differences between the invention and the prior art]

上述した従来のテストモードへの移行技術に対して、本
発明は、テストモードへの制御電圧を基準電位点より低
い負電圧で行ない、さらに入力電圧が基準電位の場合に
は、電流が流れないという独創的内容を有する。
In contrast to the conventional technique for transitioning to the test mode described above, the present invention performs the control voltage for the test mode at a negative voltage lower than the reference potential point, and furthermore, when the input voltage is at the reference potential, no current flows. It has an original content.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の入力電圧検出回路は、各トランジスタのベース
・エミッタ間電圧を第3の抵抗R8,第4の抵抗R4,
及び第5の抵抗R6により制御し、入力電圧が基準電位
である場合に動作しない第1のトランジスタQ、及び第
2のトランジスタQ2を有している。
The input voltage detection circuit of the present invention detects the base-emitter voltage of each transistor by a third resistor R8, a fourth resistor R4,
and a fifth resistor R6, and includes a first transistor Q and a second transistor Q2 that do not operate when the input voltage is at the reference potential.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例であり、入力端子VINには
抵抗R3が接続されている。抵抗R3の他の一端はトラ
ンジスタQ1のエミッタ及び抵抗R4に接続されている
。抵抗R4の他の一端はトランジスタQ2のベース及び
抵抗R6に接続されている。
FIG. 1 shows an embodiment of the present invention, in which a resistor R3 is connected to the input terminal VIN. The other end of resistor R3 is connected to the emitter of transistor Q1 and resistor R4. The other end of resistor R4 is connected to the base of transistor Q2 and resistor R6.

抵抗R6の他の一端は基準電位点に接続されている。ト
ランジスタQ1のベースは基準電位点に接続され、トラ
ンジスタQ1のコレクタは出力端子A及び抵抗R1を介
して電源に接続されている。
The other end of the resistor R6 is connected to a reference potential point. The base of the transistor Q1 is connected to a reference potential point, and the collector of the transistor Q1 is connected to a power supply via an output terminal A and a resistor R1.

また、トランジスタQ2のエミッタは基準電位点に接続
され、そしてトランジスタQ2のコレクタは出力端子B
及び抵抗R3を介して電源に接続されている。
Also, the emitter of transistor Q2 is connected to the reference potential point, and the collector of transistor Q2 is connected to output terminal B.
and is connected to a power supply via a resistor R3.

ここで、電源Vccの電圧が4.5〜5.5vの範囲に
あるとし、さらに各トランジスタはベース・エミッタ間
電圧が0.5v以下ならば動作せず、0.8v以上にな
ると動作するものとする。また、電源電圧の70%以上
は旧ghレベル、電源電圧の30%以下はLowレベル
の信号として取り扱うものとする。
Here, assume that the voltage of the power supply Vcc is in the range of 4.5 to 5.5V, and furthermore, each transistor does not operate if the base-emitter voltage is less than 0.5V, and operates when it becomes 0.8V or more. shall be. Further, 70% or more of the power supply voltage is treated as an old gh level signal, and 30% or less of the power supply voltage is treated as a low level signal.

今、第1図の回路に関して考えると、入力端子VINに
旧ghレベルの信号が入力した場合には、トランジスタ
Q1は動作しない。このときトランジスタQ、は、 すなわち、  ”    >0.254ならば、ベース
R1+R*+Rs ・エミッタ間電圧が0.8v以上となることにより動作
する。
Now, considering the circuit shown in FIG. 1, when a signal at the old GH level is input to the input terminal VIN, the transistor Q1 does not operate. At this time, the transistor Q operates as follows: If >0.254, the voltage between base R1+R*+Rs and emitter becomes 0.8V or more.

次に、入力端子v1NにLowレベルの信号が入力した
場合を考えると、トランジスタQ1は動作せず、トラン
ジスタQ2も すなわち、−一1と=−>0.303ならば、ベースR
s+R*+R* ・エミッタ間電圧が0.5v以下になるため動作しない
Next, considering the case where a low level signal is input to the input terminal v1N, the transistor Q1 does not operate and the transistor Q2 also does not operate, that is, if -1 and =->0.303, the base R
s+R*+R* ・It does not operate because the emitter voltage is less than 0.5V.

また、入力端子v!、に、次式 を満足し、さらに基準電圧より低い電圧のVIN’が入
力した場合にはトランジスタQ1は動作し、トランジス
Q2は動作しない。
Also, the input terminal v! , if the following equation is satisfied and VIN' of a voltage lower than the reference voltage is input, the transistor Q1 operates and the transistor Q2 does not operate.

ところで、ここでトランジスタの動作のし方と出力の関
係について考えると、トランジスタQ1が動作した場合
、抵抗R1を大きな値に設定すれば出力端子Aの電圧は
Lowレベルとなり、トランジスタQ1が動作しなかっ
た場合には出力端子Aの電圧は旧ghレベルとなる。ま
た、トランジスタQ2が動作した場合、抵抗R2を大き
な値に設定すれば出力端子Bの電圧はLowレベルとな
り、トランジスタQ2が動作しなかった場合には出力端
子Bの電圧は旧ghレベルとなる。
By the way, if we consider the relationship between transistor operation and output, if transistor Q1 operates, if resistor R1 is set to a large value, the voltage at output terminal A will be at a low level, and transistor Q1 will not operate. In this case, the voltage at the output terminal A becomes the old gh level. Further, when the transistor Q2 operates, the voltage at the output terminal B becomes the Low level by setting the resistor R2 to a large value, and when the transistor Q2 does not operate, the voltage at the output terminal B becomes the old gh level.

以上説明したように、式■、■、■を満足するように抵
抗Rs、R4,Rsの抵抗値、及びv、、’の値を設定
することにより、入力電圧に対する出力端子A及びBの
電圧を図3のようにすることができる。
As explained above, by setting the resistance values of the resistors Rs, R4, and Rs and the values of v, , and ' to satisfy the formulas ■, ■, and ■, the voltage at the output terminals A and B relative to the input voltage can be can be made as shown in FIG.

第3図の方式により、入力電圧v1、を出力端子A及び
Bにより検出することができる。
By the method shown in FIG. 3, the input voltage v1 can be detected by the output terminals A and B.

本発明のように動作モードへの移行を負電圧の入力によ
って行った場合には、ICの動作中に、周囲の回路との
電源電圧に多少差が生じても、誤動作してテストモード
へ移行することはない。また、入力電圧v1NがLow
レベルの場合には、回路中に電流が流れない。
If the transition to the operating mode is performed by inputting a negative voltage as in the present invention, even if there is a slight difference in the power supply voltage with the surrounding circuits while the IC is operating, the IC will malfunction and transition to the test mode. There's nothing to do. In addition, the input voltage v1N is Low
In the case of level, no current flows in the circuit.

第2図に、また別の本発明による入力電圧検出回路を示
す。第1図に示した例と比較して、第1゜第2のダイオ
ードD+、Dzが第3のトランジスタのエミッタと基準
電位点との間に接続された点のみが異なり、他は同様の
構成となっている。
FIG. 2 shows another input voltage detection circuit according to the present invention. Compared to the example shown in FIG. 1, the only difference is that the first and second diodes D+ and Dz are connected between the emitter of the third transistor and the reference potential point, and the other configurations are the same. It becomes.

第2図は第1.第2のダイオードの追加により、第3の
トランジスタQ、のベース・エミッタ間の逆バイアスの
大きさが第1.第2のダイオードDIPD2の順方向電
圧以上にならないようにし、第3のトランジスタQ、の
保護を行なった例である。
Figure 2 is 1. By adding the second diode, the magnitude of the reverse bias between the base and emitter of the third transistor Q is increased to the magnitude of the first. This is an example in which the third transistor Q is protected by preventing the forward voltage from exceeding the forward voltage of the second diode DIPD2.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、ICの動作中に周
囲の回路との電源電圧に多少差が生じても誤動作して、
テストモードへ移行することがなく、さらに入力電圧が
基準電位の場合には2つのトランジスタを動作させない
ことにより、電流を流さないので、このとき半導体集積
回路の動作モードでスタンバイモードにすれば消費電流
を小さくできる利点をもつ。
As explained above, according to the present invention, even if there is a slight difference in power supply voltage with surrounding circuits during operation of an IC, malfunction will occur.
There is no transition to the test mode, and if the input voltage is at the reference potential, the two transistors are not operated, so no current flows, so if the semiconductor integrated circuit is set to standby mode, the current consumption It has the advantage of being able to be made smaller.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による入力電圧検出回路の実施例の回路
図、第2図は本発明による入力電圧検出回路の別の実施
例の回路図。 図において、Vccは電源、VfNは入力信号、A、 
B、 C,Dは出力端子、R1〜R1゜は抵抗、Q1〜
Q、はトランジスタ、Dl、D2はダイオードを示す。 第3図は、本発明による入力電圧に対する出力端子A、
Bの電圧レベルの方式を示す。図において、負電圧とは
、■式を満足する必要がある。 代理人 弁理士  内 原   音
FIG. 1 is a circuit diagram of an embodiment of the input voltage detection circuit according to the present invention, and FIG. 2 is a circuit diagram of another embodiment of the input voltage detection circuit according to the present invention. In the figure, Vcc is the power supply, VfN is the input signal, A,
B, C, D are output terminals, R1~R1゜ are resistors, Q1~
Q represents a transistor, and Dl and D2 represent diodes. FIG. 3 shows the output terminal A for input voltage according to the present invention;
The voltage level scheme of B is shown. In the figure, the negative voltage needs to satisfy formula (2). Agent Patent Attorney Oto Uchihara

Claims (1)

【特許請求の範囲】[Claims]  半導体集積回路において、第1、第2のトランジスタ
を備えそれぞれ前記第1のトランジスタのベースと前記
第2のトランジスタのエミッタは基準電位点へ接続され
、入力端子より第3の抵抗を介して前記第1のトランジ
スタのエミッタへ接続され、さらに該第1のトランジス
タのエミッタから第4の抵抗を介して前記第2のトラン
ジスタのベースへ接続され、該第2のトランジスタのベ
ースは第5の抵抗を介して基準電位に接続され、前記第
1、第2のトランジスタのコレクタより制御出力を得る
ことを特徴とする入力電圧検出回路。
The semiconductor integrated circuit includes first and second transistors, the base of the first transistor and the emitter of the second transistor are connected to a reference potential point, and the second The emitter of the first transistor is further connected to the base of the second transistor via a fourth resistor, and the base of the second transistor is connected to the base of the second transistor via a fifth resistor. An input voltage detection circuit characterized in that the input voltage detection circuit is connected to a reference potential and obtains a control output from the collectors of the first and second transistors.
JP63041160A 1988-02-23 1988-02-23 Input voltage detection circuit Expired - Lifetime JP2567015B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63041160A JP2567015B2 (en) 1988-02-23 1988-02-23 Input voltage detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63041160A JP2567015B2 (en) 1988-02-23 1988-02-23 Input voltage detection circuit

Publications (2)

Publication Number Publication Date
JPH01214779A true JPH01214779A (en) 1989-08-29
JP2567015B2 JP2567015B2 (en) 1996-12-25

Family

ID=12600671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63041160A Expired - Lifetime JP2567015B2 (en) 1988-02-23 1988-02-23 Input voltage detection circuit

Country Status (1)

Country Link
JP (1) JP2567015B2 (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS471179U (en) * 1971-01-19 1972-08-11
JPS5024104U (en) * 1973-06-27 1975-03-18
JPS5892681U (en) * 1981-12-16 1983-06-23 富士通株式会社 logic circuit checker
JPS58164040U (en) * 1983-03-07 1983-11-01 工業技術院長 logic check device
JPS61179615A (en) * 1985-02-05 1986-08-12 Nec Corp Test input circuit
JPH07249693A (en) * 1994-03-14 1995-09-26 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH0851151A (en) * 1994-08-08 1996-02-20 Mitsubishi Electric Corp Semiconductor device and manufacture of semiconductor device
JPH08250678A (en) * 1995-02-17 1996-09-27 Samsung Electron Co Ltd Capacitor of semiconductor memory device and its manufacture

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS471179U (en) * 1971-01-19 1972-08-11
JPS5024104U (en) * 1973-06-27 1975-03-18
JPS5892681U (en) * 1981-12-16 1983-06-23 富士通株式会社 logic circuit checker
JPS58164040U (en) * 1983-03-07 1983-11-01 工業技術院長 logic check device
JPS61179615A (en) * 1985-02-05 1986-08-12 Nec Corp Test input circuit
JPH07249693A (en) * 1994-03-14 1995-09-26 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH0851151A (en) * 1994-08-08 1996-02-20 Mitsubishi Electric Corp Semiconductor device and manufacture of semiconductor device
JPH08250678A (en) * 1995-02-17 1996-09-27 Samsung Electron Co Ltd Capacitor of semiconductor memory device and its manufacture

Also Published As

Publication number Publication date
JP2567015B2 (en) 1996-12-25

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