JPH01214014A - Manufacture of soi substrate - Google Patents

Manufacture of soi substrate

Info

Publication number
JPH01214014A
JPH01214014A JP3881588A JP3881588A JPH01214014A JP H01214014 A JPH01214014 A JP H01214014A JP 3881588 A JP3881588 A JP 3881588A JP 3881588 A JP3881588 A JP 3881588A JP H01214014 A JPH01214014 A JP H01214014A
Authority
JP
Japan
Prior art keywords
silicon
layer
silicon nitride
trench
growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3881588A
Other languages
Japanese (ja)
Inventor
Masatoshi Yazaki
矢崎 正俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP3881588A priority Critical patent/JPH01214014A/en
Publication of JPH01214014A publication Critical patent/JPH01214014A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent a silicon nitride nucleus from being stripped off without working the silicon nitride nucleus minutely and to form falt, easy-to-work and homogeneous single-crystal silicon on an insulating substrate by a method wherein a polycrystalline silicon layer and a silicon dioxide layer are laminated on a silicon nitride layer and a single-crystal silicon layer is formed inside a trench. CONSTITUTION:A silicon nitride layer 2 is formed on an insulating substrate 1; a polycrystalline silicon layer 3 is laminated on it; in addition, a silicon dioxide layer 4 is laminated on it; a trench 5 ranging from the surface of the silicon dioxide layer 4 to the silicon nitride layer 2 is formed. Then, a single-crystal silicon layer 6 is formed inside said trench 5 by a selective epitaxial growth operation by making use of the silicon nitride layer 2 as a growth nucleus. By this setup, when the selective epitaxial growth operation of silicon is executed by making use of the silicon nitride layer 2 as the growth nucleus, it is affected by a crystal lattice of the polycrystalline silicon layer 3 constituting sidewalls of the trench 5; accordingly, the growth orientation can be controlled; priority is given to the growth only in the direction perpendicular to the surface of the insulating substrate 1; as a result, a flat single-crystal silicon layer 6 is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、絶縁性基体上に結晶性のシリコン層を形成す
るSOI基体の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an SOI substrate in which a crystalline silicon layer is formed on an insulating substrate.

〔従来の技術〕[Conventional technology]

従来のSOI基体の製造方法の一例はr EXtend
ed Abstracts of the 19th 
Conference on 5otidstate 
DeViCe and Materials、Toky
o、1987. pp、i91〜194/5elect
ive Growth of Nuclei on A
morphous 5ubstrates」に記載され
た第2図(a) 〜(C)に示したものである。第2図
(a)において、二酸化シリコンよりなる絶縁性基体1
の上に、後に単結晶シリコンを成長させるための核とな
る膜厚0.1〜0.2μmの直方体状の窒化シリコン核
7を形成する。窒化シリコン核7の絶縁性基本1の表面
に水平な面の面積は約7μm2以下である。この面積が
16μm2以上になると、窒化シリコン核7を中心とし
て複数のシリコン結晶が成長して多結晶化し、単結晶に
はならない0次に、四塩化シリコンか二塩化シランと水
素の混合ガスを使い、エピタキシャル反応炉で選択エピ
タキシャル成長反応を行ない、第2図(b)に示すよう
に窒化シリコン核7を中心に、単結晶シリコン粒8の成
膜を行なう、隣接して存在する窒化シリコン核7から成
長を続けた単結晶シリコン粒8は、やがて、第2図(c
)に示すようにぶつかり合い結晶粒界9を形成して絶縁
性基体上に凹凸のあるシリコン層を構成することになる
。さらに、この凹凸形状のシリコン層を使って半導体装
置を形成する場合は、表面形状を平坦にするための研磨
を行ない加工のしやすいものとする必要がある。
An example of a conventional SOI substrate manufacturing method is r EXtend.
ed Abstracts of the 19th
Conference on 5otidstate
DeViCe and Materials, Tokyo
o, 1987. pp, i91~194/5 select
ive Growth of Nuclei on A
2(a) to (C) described in "Morphous 5 Substrates". In FIG. 2(a), an insulating substrate 1 made of silicon dioxide
A rectangular parallelepiped silicon nitride core 7 having a film thickness of 0.1 to 0.2 μm is formed thereon to serve as a core for later growing single crystal silicon. The area of the plane of the silicon nitride core 7 that is horizontal to the surface of the insulating base 1 is about 7 μm 2 or less. When this area becomes 16 μm2 or more, multiple silicon crystals grow around the silicon nitride core 7 and become polycrystalline, and do not become a single crystal. , a selective epitaxial growth reaction is carried out in an epitaxial reactor, and single crystal silicon grains 8 are formed around silicon nitride nuclei 7 as shown in FIG. 2(b). The single-crystal silicon grains 8 that continued to grow eventually become as shown in Figure 2 (c
), the grains collide to form crystal grain boundaries 9, forming an uneven silicon layer on the insulating substrate. Furthermore, when a semiconductor device is formed using this uneven silicon layer, it is necessary to polish the surface to make it flat and easy to process.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、従来の技術では、窒化シリコン核の絶縁性基体
の表面に水平な面の面積を約7μm2以下にバターニン
グする必要があり、微小なために絶縁性基体1との密着
面が小さく剥離しやすく、窒化シリコン核7が失なわれ
ることが多かった。
However, in the conventional technology, it is necessary to pattern the area of the surface of the silicon nitride core horizontal to the surface of the insulating substrate to about 7 μm2 or less, and due to the small size, the surface in close contact with the insulating substrate 1 may peel off. The silicon nitride core 7 was often lost.

さらに、窒化シリコン核7から等友釣にシリコンの成長
が始まるために、最終的に構成されたシリコン表面には
大きな凹凸が生じ、後のシリコン膜を利用した半導体装
置形成の際には、表面を平坦にするための加工工程を要
する問題点を有していた。また、成長中心核となる窒化
シリコン核と成長する単結晶シリコン粒8とは組成が異
なり、結晶の格子定数も異なるため、成長する単結晶シ
リコン粒8の成長面の方位性の制御ができず、種々の方
向への成長が同時進行し、均質なシリコン結晶粒を得る
ことができないという問題点も有していた。
Furthermore, since silicon begins to grow equidistantly from the silicon nitride core 7, large irregularities occur on the final silicon surface. This had the problem of requiring a machining process to make it flat. Furthermore, since the silicon nitride nucleus, which is the center of growth, and the growing single-crystal silicon grain 8 have different compositions and crystal lattice constants, it is not possible to control the orientation of the growth plane of the growing single-crystal silicon grain 8. However, there was also the problem that growth proceeded in various directions simultaneously, making it impossible to obtain homogeneous silicon crystal grains.

そこで、本発明のSOI基体の製造方法は、窒化シリコ
ン核の微細な加工をすることなく、窒化シリコン核の剥
離を無くし、平坦で加工のしやすい均質な単結晶シリコ
ンを絶縁性基体上に形成する製造方法を提供することを
目的としている。
Therefore, the method for manufacturing an SOI substrate of the present invention eliminates the peeling of silicon nitride nuclei without performing fine processing of silicon nitride nuclei, and forms homogeneous single crystal silicon that is flat and easy to process on an insulating substrate. The purpose is to provide a manufacturing method that

〔課題を解決するための手段〕[Means to solve the problem]

本発明のSOI基体の製造方法は、絶縁基体上に、窒化
シリコン層を成膜し、前記窒化シリコン層上に多結晶シ
リコン層を積層し、前記多結晶シリコン層上に二酸化シ
リコン層を積層し、前記二酸化シリコン層表面から前記
窒化シリコン層に到るトレンチを構成して、前記トレン
チ内に前記窒化シリコン層を成長核として選択エピタキ
シャル成長法により単結晶シリコン層を構成したことを
特徴とする。
The method for manufacturing an SOI substrate of the present invention includes forming a silicon nitride layer on an insulating substrate, laminating a polycrystalline silicon layer on the silicon nitride layer, and laminating a silicon dioxide layer on the polycrystalline silicon layer. A trench is formed from the surface of the silicon dioxide layer to the silicon nitride layer, and a single crystal silicon layer is formed in the trench by selective epitaxial growth using the silicon nitride layer as a growth nucleus.

〔実 施 例〕〔Example〕

本発明のSOI基体の製造方法の実施例を図面に基づき
以下に説明する。
Embodiments of the method for manufacturing an SOI substrate of the present invention will be described below with reference to the drawings.

第1図(a)において、絶縁性基体1の上に窒化シリコ
ンN2を成膜する。窒化シリコン層2の成膜は、通常の
減圧下の化学的気相反応やプラズマを利用した化学的気
相反応のいずれによって成膜してもよい、減圧下の化学
的気相反応では、反応ガスとしてはシランガスとアンモ
ニアの混合ガスを600℃以上の温度条件下で反応させ
る。
In FIG. 1(a), a film of silicon nitride N2 is formed on an insulating substrate 1. In FIG. The silicon nitride layer 2 may be formed by either a normal chemical vapor phase reaction under reduced pressure or a chemical vapor phase reaction using plasma. As the gas, a mixed gas of silane gas and ammonia is reacted at a temperature of 600° C. or higher.

次に第1図(b)において、成膜した窒化シリコン層の
上に多結晶シリコン3を5μm〜0.5μmの膜厚で成
膜する。
Next, in FIG. 1(b), polycrystalline silicon 3 is formed to a thickness of 5 μm to 0.5 μm on the silicon nitride layer thus formed.

多結晶シリコン層3を積層した後、第1図(c)に示す
ように、二酸化シリコン層4を積層する二酸化シリコン
層4を構成する方法としては、前工程で積層した多結晶
シリコン層3の表面を熱酸化する方法か、化学的気相反
応によりシランと酸素の混合ガスにより成膜する方法が
ある。
After laminating the polycrystalline silicon layer 3, a silicon dioxide layer 4 is laminated as shown in FIG. There is a method of thermally oxidizing the surface, or a method of forming a film using a mixed gas of silane and oxygen through a chemical vapor phase reaction.

次に、第1図(d)に示すように、RIEによる異方性
のドラマ・エツチング技術により二酸化シリコン層4表
面より、窒化シリコン層2に到るトレンチ5を構成する
。多結晶シリコン層3とトレンチ5の底部に露出する窒
化シリコン層2とは組成が異なるため、窒化シリコン層
2がトレンチ5の底部に露出しな後さらにエツチングを
続けても、露出した窒化シリコン層2内部までエツチン
グが進行することがなく、エツチングの対窒化シリコン
に対する選択性は高い、したがって、エツチング所要時
間の設定範囲は広く、エツチング時間がたとえ標準より
超過しても、トレンチ5形状にあたえる影響はほとんど
ない。
Next, as shown in FIG. 1(d), a trench 5 extending from the surface of the silicon dioxide layer 4 to the silicon nitride layer 2 is formed using an anisotropic drama etching technique using RIE. Since the polycrystalline silicon layer 3 and the silicon nitride layer 2 exposed at the bottom of the trench 5 have different compositions, even if etching is continued after the silicon nitride layer 2 is not exposed at the bottom of the trench 5, the exposed silicon nitride layer 2. Etching does not progress to the inside of trench 5, and etching has high selectivity to silicon nitride. Therefore, the setting range of the etching time is wide, and even if the etching time exceeds the standard, it will have no effect on the shape of trench 5. There are almost no

トレンチ5が構成された後は、第1図(e)に示すよう
に、トレンチ5を埋め込むように窒化シリコン層2を成
長核としたシリコンの選択エピタキシャル成長を行なう
、このエピタキシャル成長時には、トレンチ5の側壁を
構成する多結晶シリコン層3の結晶格子の影響を受ける
ため成長方位の制御が可能で、成長方法は、絶縁性基体
1の表面に垂直な方向のみが優先的になるので、従来例
のように等方的な結晶成長と異なり、平坦な単結晶シリ
コン層6が構成される。
After the trench 5 is formed, as shown in FIG. 1(e), silicon is selectively epitaxially grown using the silicon nitride layer 2 as a growth nucleus so as to fill the trench 5. During this epitaxial growth, the side walls of the trench 5 are It is possible to control the growth direction because it is influenced by the crystal lattice of the polycrystalline silicon layer 3 constituting the insulating substrate 1, and the growth direction is prioritized only in the direction perpendicular to the surface of the insulating substrate 1. Unlike isotropic crystal growth, a flat single crystal silicon layer 6 is formed.

〔発明の効果〕〔Effect of the invention〕

上記実施例より明らかなように、本発明によるSol基
体の製造方法によれば、結晶核となる窒化シリコン膜を
、微小な形状にバターニングする工程は不要になり、窒
化シリコン膜の剥離も生ずることなく、トレンチの大き
さにより窒化シリコン膜の成長時における有効面積を簡
単に制御することも可能である。また、トレンチ側壁を
多結晶シリコン層が囲むため、トレンチ内に成長する単
結晶シリコンの成長方位を制御することも可能で、成長
が絶縁性基体の表面に対し、垂直方向に優先的に成長す
るため、得られる単結晶シリコン層の表面は平坦である
。このため、核から等方的に成長する結晶成長の場合と
異なり、得られた単結晶シリコン層を平坦に再加工する
必要もない、さらに、トレンチの構成の際には、トレン
チ底部に露出する結晶成長核となる窒化シリコン層がエ
ツチングのストッパーの役割りをはなし、エツチング時
間のマージンが広く、加工が容易であるという効果も有
する。
As is clear from the above examples, according to the method for manufacturing a Sol substrate according to the present invention, there is no need for the step of buttering the silicon nitride film, which serves as a crystal nucleus, into a minute shape, and peeling of the silicon nitride film also occurs. It is also possible to easily control the effective area during growth of the silicon nitride film by adjusting the size of the trench. Additionally, since the trench sidewalls are surrounded by a polycrystalline silicon layer, it is also possible to control the growth direction of the single crystal silicon that grows inside the trench, preferentially growing in the direction perpendicular to the surface of the insulating substrate. Therefore, the surface of the obtained single crystal silicon layer is flat. For this reason, unlike in the case of crystal growth that grows isotropically from a nucleus, there is no need to reprocess the obtained single crystal silicon layer to make it flat. The silicon nitride layer, which serves as a crystal growth nucleus, acts as an etching stopper, has a wide etching time margin, and has the advantage of being easy to process.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(e)は本発明のSOI基体の製造方法
の一実施例を示す要部断面図、第2図(a)〜(c)は
従来のSOI基体の製造方法を示す要部断面図である。 1・・・絶縁性基体 2・・・窒化シリコン層 3・・・多結晶シリコン層 4・・・二酸化シリコン層 5・・・トレンチ 6・・・単結晶シリコン層 7・・・窒化シリコン核 8・・・単結晶シリコン粒 9・・・結晶粒界 以上 纂 1 旧
FIGS. 1(a) to (e) are cross-sectional views of essential parts showing an embodiment of the method for manufacturing an SOI substrate of the present invention, and FIGS. 2(a) to (c) show a conventional method for manufacturing an SOI substrate. It is a sectional view of the main part. 1... Insulating substrate 2... Silicon nitride layer 3... Polycrystalline silicon layer 4... Silicon dioxide layer 5... Trench 6... Single crystal silicon layer 7... Silicon nitride core 8 ...Single-crystal silicon grain 9...Above the grain boundary 1 Old

Claims (1)

【特許請求の範囲】[Claims]  絶縁性基体上に、窒化シリコン層を成膜し、前記窒化
シリコン層上に多結晶シリコン層を積層し、前記多結晶
シリコン層上に二酸化シリコン層を積層し、前記二酸化
シリコン層表面から前記窒化シリコン層に到るトレンチ
を構成して、前記トレンチ内に前記窒化シリコン層を成
長核として選択エピタキシャル成長法により単結晶シリ
コン層を構成したことを特徴とするSOI基体の製造方
法。
A silicon nitride layer is formed on an insulating substrate, a polycrystalline silicon layer is laminated on the silicon nitride layer, a silicon dioxide layer is laminated on the polycrystalline silicon layer, and the nitride layer is laminated from the surface of the silicon dioxide layer. 1. A method for manufacturing an SOI substrate, comprising forming a trench reaching a silicon layer, and forming a single crystal silicon layer in the trench by selective epitaxial growth using the silicon nitride layer as a growth nucleus.
JP3881588A 1988-02-22 1988-02-22 Manufacture of soi substrate Pending JPH01214014A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3881588A JPH01214014A (en) 1988-02-22 1988-02-22 Manufacture of soi substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3881588A JPH01214014A (en) 1988-02-22 1988-02-22 Manufacture of soi substrate

Publications (1)

Publication Number Publication Date
JPH01214014A true JPH01214014A (en) 1989-08-28

Family

ID=12535764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3881588A Pending JPH01214014A (en) 1988-02-22 1988-02-22 Manufacture of soi substrate

Country Status (1)

Country Link
JP (1) JPH01214014A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5234861A (en) * 1989-06-30 1993-08-10 Honeywell Inc. Method for forming variable width isolation structures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5234861A (en) * 1989-06-30 1993-08-10 Honeywell Inc. Method for forming variable width isolation structures

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