JPH01213037A - Voice decoder - Google Patents

Abstract

PURPOSE:To simplify the constitution of the address circuit of data reading by writing serial input digital voice data to be a condition deinterleaved on the memory map of a memory. CONSTITUTION:The respective address signals of a deinterleaving address generator 32, a range address generator 33 and a data address generator 34 are selected by a selector 35. The generator 32 is constituted with a ROM, for instance, and data to indicate the original arranging position of voice data, to which interleaving is given, is stores in advance. The selector 35 selects only the data read from the generator on the writing of a RAM 24 by the select signal from a timing clock generator 14, and the voice data supplied from a descramble circuit 15 to the RAM 24 serially are written to an address corresponding to the original arranging position. Consequently, a reading address is satisfied with counting up from an initial value in order, and the circuit constitution of the generators 33 and 34 can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an audio decoder, and more particularly to a decoder that deinterleaves received digital audio data and then converts it into an original analog audio signal.

BACKGROUND OF THE INVENTION Various methods have been known in the past for multiplexing digital audio data with other information signals and transmitting them. There is a new television audio multiplex broadcasting system in the UK that transmits television signals that are frequency-division multiplexed onto video signals by phase modulating the digital audio signals (digital audio data).

This television audio multiplex broadcasting system transmits and receives television signals as shown in FIG.

In the figure, ■ is a video signal transmission band, Sl is a conventional FM audio subcarrier obtained by frequency modulating (FM) a subcarrier 6 M l-IZ higher than the video carrier with an analog audio signal,
S2 is a subcarrier 6.552M @ z higher than the video carrier with digital audio data using four-phase difference phase similarity shift II.
(DPSK: D1ffcrential
phase 3hift KeViH) L/L/. The audio signal transmission specifications related to this PCM audio subcarrier are shown in the numerical table.

The above-mentioned digital audio data is synthesized in time series in frame units in the frame structure shown in FIG. 6 and transmitted.

In Figure 6, FAW (Frame Alignment
CW (Control Word) is a 5-bit control word, followed by 11-bit independent data WD and 704-bit digital audio data (hereinafter also referred to as audio data). One frame is composed of a total of 728 bits, which are synthesized in chronological order.

Since this one frame is transmitted at 1 g+sec, the code transmission rate is 728 kB/S and the data rate is 728 kl-IZ, as shown in the table above.

In addition, the audio data has a quantization bit number of 14 bits obtained by PCM at a sampling frequency of 32 kHz.
It is compressed quasi-instantaneously to 10 hits, and 1 parity bit is added to this to form 1 word. FIG. 7 shows the signal format of this one word audio data. In the same figure, Do~D9 are the audio data of the above 10 pits 1~, P
s is a 1-bit parity pit. This parity pit Ps is one bit generated based on the following equation.

D4■D5■D6■D7■D8■D9■P=0P■R=
Ps (2) In the above equation, P is an even parity bit for the upper 6 bits D4 to D9, and R is a range bit indicating the 14/10 bit quasi-instantaneous row reduction information.

In 14/10-bit quasi-instantaneous compression, when PCM audio data with a quantization bit number of 14 bits is coded in two's complement representation, if the level is small, the MSB (most significant bit) is added to the upper bits of the PCM audio data. ) since the same value as the polarity sign bit continues, the upper bits except the MSB are dropped, and since low level noise is difficult to distinguish when the level is large, the lower bits are dropped to compress it to 10 bits. Since this quasi-instantaneous companding itself is well known, detailed explanation thereof will be omitted.

In addition, the audio data is interleaved with 16 bits to protect against burst errors, and has a matrix configuration of 16 rows and 44 columns. Furthermore, in order to reduce the number of consecutive identical values (1 or 0), M-sequence PN (P5eudo Random) is used.
Scrambled by the Noise) signal.

The audio data that has been subjected to each of the above processes is as shown by WA in Figure 6, with a total of 6 audio data of 1 word, 11 pins, 1-.
11 words (32 words/channel) are synthesized in time series.

Problems to be Solved by the Invention In order to demodulate digital audio data, a random access memory (RAM) is required as the buffer 7 memory. Since this RAM is written in 21 bits/word, if the digital audio data is 2m bits per word, it is convenient for timing generation and data processing such as deinterleaving and range code detection.

However, as mentioned above, in the above TV audio multiplex broadcasting system, one frame is not 128 bits or 21 bits, and one word of audio data is also 11 bits, not 2 m pitch 1-, so the 2η pitch 1~/word structure is RA of
Using M requires complex circuitry for timing generation such as deinterleaving and range code detection.

The present invention has been made in view of the above points, and an object of the present invention is to provide an audio decoder that solves the above problems by using a serial time-division processing method.

Means for Solving the Problems The audio decoder of the present invention includes storage means and control means. The storage means stores in advance data indicating the original arrangement position of the interleaved digital audio data in the interleaved order.

Further, the control means causes the serial human horn digital voice data to be written in the address of the memory according to the data read from the storage means.

Operation: The storage means stores in advance data indicating the original arrangement position of interleaved digital audio data in the interleaved order. Therefore, the interleaved digital audio data serially supplied to the memory is deinterleaved and written by the control means.

That is, the arrangement order of interleaved digital audio data in one frame is known; for example, the first audio data is the 25th.

If the next audio data is in the order of 69th, 113th, 151st, etc., then the storage means has r'25J, r69J, r113.
J.

Data is stored and read out in the order of 157J, etc., so the first audio data is stored at address 25, and the serial input digital audio data is sequentially stored at addresses 69, 113, 157, and so on. This means that the serial input digital audio data will be gain-interleaved on the memory map.Therefore, when reading, the read address can be simply incremented by 1. It will be a good thing.

Embodiment FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram schematically showing the processing operation of FIG. 1, and FIG. 3 is a diagram of a television receiver having an audio decoder of the present invention. A block system diagram of an example of main parts is shown.

In FIG. 1 and FIG. 3, the same components are given the same reference numerals.

First, referring to FIG. 3, the TV audio multiplex broadcast signal received by the antenna 1 is converted into an intermediate frequency signal (IF signal) by the Ul-IF tuner 2, and then
The signal is output to a video detection circuit (not shown) through an output terminal 3, and is supplied to a filter circuit 5 through a preamplifier 4. Filter circuit 5 has a center frequency of 32.948M
Hz video intermediate frequency signal and center frequency 39.5MHz
The audio intermediate frequency signals are converted into P waves and supplied to the video intermediate frequency detector 6. As a result, the video intermediate frequency detector 6 outputs the FM audio subcarrier (
81 in Figure 5) and a center frequency of 6.552M H
Z (7) P 0M voice subcarrier (designated S2 in FIG. 5) is extracted. The FM audio subcarrier is supplied to a bandpass filter (BPF) 16-1, where unnecessary frequency components are removed, and then supplied to an FM demodulator 16-2, where the F
After being demodulated, the PCM audio subcarrier is output to an output terminal 7, and is supplied to a bandpass filter (BPF) 8, where unnecessary frequency components are removed, and then supplied to a 4-phase DPSK III device 9.

The configurations of the four-phase DPSK modulator 9 and the differential converter 11 are well known, and after converting a Gray code binary number into a natural binary number, parallel-to-serial conversion is performed to obtain demodulated data. Also, 4-phase D
The clock generator 11 performs clock recovery from the output signal of the PSK demodulator 9, and generates 728 kHz and 5824 kHz.
Two types of clock pulses of kHz (=728kl-1z x 8) are taken out in parallel.

The above demodulated data is supplied to a frame synchronization circuit 13 within the audio decoder 12, and two types of clock pulses are supplied to a timing clock generator 14 within the audio decoder 12.

The frame synchronization circuit 13 has a circuit configuration shown in FIG. 4, for example, and detects a frame synchronization signal indicated by FAW in FIG. 6. In FIG. 4, a frame synchronization pattern detection circuit 41 is supplied with a clock pulse from a timing clock generator 14 and a frame position pulse from a 7-frame counter 42, and is also supplied with demodulated data as input data, which are set in advance. It is determined whether the frame synchronization pattern matches the demodulated data, and if they do not match, the synchronization counter 45 is cleared through the AND circuit 44, and the asynchronous counter 46 counts by one. Further, in the case of a match, the synchronous number counter 45 counts by one through the AND circuit 43, and at the same time, the asynchronous number counter 46 is cleared. Each of the counters 45 and 46 has predetermined values set in advance, and when the count reaches the predetermined value, the flip-flop 47 is set or reset. In response to this, a synchronizing signal is output to the output terminal 48, and a signal indicating asynchronous state is output to the output terminal 49. In the case of non-synchronization, the demodulated data is sequentially shifted one bit at a time and input, and a match/mismatch determination is made. If there is a match, the frame counter 42 is initialized and the determination is made at the next frame synchronization pattern position.

If synchronized, the determination is always made based on the frame synchronization pattern position.

Returning to FIG. 3, the timing clock extracted from the timing clock generator 14 is used not only by the frame synchronization circuit 13 but also by the descrambling circuit 15. RAM controller 17. It is supplied to an error detection and error correction circuit 19 and an output register 21, respectively.

The demodulated data is subjected to processing similar to the scramble processing on the transmitting side by the descrambler circuit 15 to become the original data before being scrambled, and then serially supplied to the RAM 24, where the main parts of the present invention described later are processed. RAM that forms
The data is written to the address specified by the address signal from the controller 17.

The data deinterleaved and read from the RAM 24 is subjected to a parity check using the even parity P generated from D4 to D9 by inversely calculating the received parity Ps by the scale detection circuit 18, and the result is sent to the error detection and error correction circuit 19. Error detection and error correction based on majority decision are performed. Furthermore, the scale detection circuit 18 detects the even parity P and the received parity P.
Range information R is obtained from s and supplied to an expansion circuit 20, where it is expanded into audio data with a correct value of quantization bits of 14 bits based on the audio data from the error detection and error correction circuit 19.

This audio data with a quantization bit count of 14 bits is externally supplied to a D/A converter 25 through an output register 21, where it is converted into a reproduced audio signal of an analog signal. .28 and mute/switch circuit 26-1. ．． It is output to output terminal 29.30 through 26-2.

Note that the control circuit 23 is a mute/switch circuit 26-1.
．． The operation of 26-2 is controlled to be muted when a predetermined number of errors or more occur. In addition, the mode detection circuit 22
detects whether the received audio data mode is monaural, stereo, bilingual, or other than audio data.

In the audio decoder 12 in the television receiver having such a configuration, this embodiment is characterized in that it is configured as shown in FIG. In FIG. 1, 32 is a deinterleave address generator, 33 is a range address generator, and 3
4 is a data address generator, and a selector 35 selects and outputs only one of these output address signals.

The deinterleave address generator 32 is, for example, a read address generator.
It is composed of only memory (ROM), and data indicating the original arrangement position (zamble position) of interleaved audio data is stored in advance.

The selector 35 selects 2 from the timing clock generator 14.
Since it is configured to selectively output only the data read out from the deinterleave address generator 32 when writing to the RAM 24 using a select signal of 912 kHz, the audio data serially supplied from the descrambling circuit 15 to the RAM 24 is It is written to the address corresponding to the original array location. This data writing is the second
This is carried out during the period indicated by 54 in the figure.

Only 104-bit audio data indicated by WA in FIG. 6 is written into the RAM 24, and the RAM 24 performs time division processing operations as shown in FIG. 2 by the RAM controller 17 shown in FIG. That is, the RAM 24 receives one bit of audio data (for example, Do) from the address applied from the data address generator 31 in FIG.
, and then obtain range information from the address applied from the range address generator 33 in FIG. 1 via the selector 35 during the period shown at 52 in FIG. (for example, D4).

Next, the RAM 24 again reads out one bit (for example, D+) of the audio data based on the address from the data address generator 34 during the period indicated by 53 in FIG.
During the period indicated by 54 in the figure, one bit of audio data is written to the deinterleaved address based on the output address of the deinterleave address generator 32 as described above.

Thereafter, the same operation as above is repeated periodically.

The audio data read from the RAM 24 is subjected to an even parity inverse operation and a parity check in the parity check circuit 36 shown in FIG.
is supplied to The decompression processing circuit 37 is similar to the decompression circuit 20.
It is composed of a scale detection circuit 18, an error check detection and error correction circuit 19, an output register 21, etc., and outputs audio data expanded to 14 quantized bits to a D/A converter 25.

Since the audio data is written in the RAM 24 at an address corresponding to the value indicating its original (before interleaving) sample order, the read address only has to be counted up one by one starting from the initial value. Therefore, the range address generator 33 and the data address generator 34 can have a simple circuit configuration such as a counter.

It should be noted that the present invention is not limited to the case where it is applied to the audio decoder in the above-mentioned British television audio multiplex broadcasting system, but can be applied to all audio decoders that decode interleaved digital audio data. Of course.

Effects of the Invention As described above, according to the present invention, since serially input digital audio data is written in a deinterleaved state on the memory map of the buffer memory, even if the audio data does not have a 21-bit/word configuration, It has the advantage that the address circuit for data reading can be made into a simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram schematically showing the processing operation of FIG. 1, and FIG. 3 is a main part of a television receiver having an audio decoder of the present invention. FIG. 4 is a circuit diagram of an example of the frame synchronization circuit in FIG. 3, FIG. 5 is a frequency spectrum diagram of an example of a TV audio multiplex broadcast signal, and FIG. 6 is a one-frame signal. FIG. 7 is a diagram showing an example of a signal format of audio data. 12... Audio decoder, 13... Frame synchronization circuit, 14... Timing clock generator, 15... Descrambling circuit, 17... RAM controller, 2
4...RAM (random access memory), 3
2...Deinterleave address generator, 33...
Range address generator, 34...Data address generator, 35...Zelector.

Claims (1)

[Scope of Claims] An audio device that controls the memory to write interleaved digital audio data into a memory and read out deinterleaved digital audio data in the original order before interleaving from the memory. The decoder includes a storage means in which data indicating the original arrangement position of the interleaved digital audio data is stored in advance in interleaved order, and the interleaved digital audio data is serially supplied to the memory. The present invention is also characterized by comprising control means for supplying the data sequentially read out from the storage means as an address signal to the memory in synchronization with the above, and causing the serial input digital audio data to be written to the address. audio decoder.