JPH01212463A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To suppress a transistor constituting a parasitic thyristor from being turned on upon application of a trigger current and to prevent a latchup from taking place by a method wherein a P-N junction capacitor is formed by a semiconductor substrate and a second well and a backward bias potential is supplied to the P-N junction. CONSTITUTION:This design is different from a conventional design in that an N-type well 11 is formed in the surface of a P-type semiconductor substrate 1 and, in the surface of the N-type well 11, an N-type diffusion region 12 is formed for an ohmic contact, wherethrough a ground potential VSS is applied. With a P-N junction capacitor being formed by the semiconductor substrate 1 and the N-type well 11 and with a backward bias potential being applied to the P-N junction, a trigger current that may cause a latchup upon injection is allowed to flow partly into the P-N junction capacitor where it is accumulated. Such a design impedes a transistor constituting a parasitic thyristor from being turned on, preventing a latchup from taking place.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device used in a DRAM, etc., and particularly relates to a semiconductor integrated circuit device that is capable of preventing latch-up due to the occurrence of a parasitic thyristor phenomenon. It is something.

(・Prior art) Figure 3 shows CMO8I used in conventional DRAM! I
1 shows a schematic diagram of a semiconductor device having a structure. In the figure, reference numeral 1 denotes a P-type semi-dedicated substrate, and an N-type well 2 for forming a P-channel transistor is formed in the upper layer of the P semiconductor substrate 1. As shown in FIG.

In the upper layer of this N-type well 2, there are P-type diffusion regions 3 for the source and drain of the P-channel transistor.
Further, an N-type diffusion region 5 is formed in the upper layer of the N-type well 2 to obtain ohmic contact, and P N, which is the common bulk of the channel transistors
Power supply potential V to type well 2. 0 is given, and the potential of the N-type well 2 is the power supply level 1 V. , and is configured to be fixed to . The reason for fixing the potential of the N-type well 2 to the power supply potential VOD in this way is to effectively absorb electrons and lower the spreading resistance of the tube. N-type diffusion regions 6.7 for the drain and source of an N-channel transistor are formed at regular intervals in the upper layer of the P-type semiconductor substrate 1 except for the P-type semiconductor substrate 1. Further, a P-type diffusion region 8 for obtaining ohmic contact is formed in the upper layer of the P-type semiconductor substrate 1, and a negative substrate bias potential is applied to the P-type semiconductor substrate 1 via this P-type diffusion region 8. vBB is applied, and the potential of the P-type semiconductor substrate 1 is fixed to the substrate bias potential vBB. The P-type diffusion region 3 for the source of the P-channel transistor is supplied with the power supply potential VDO, while the N-type diffusion region 7 for the source of the P-channel transistor is supplied with the ground potential v,8. ing.

4th f! 1 represents an equivalent circuit of a parasitic thyristor occurring in the semiconductor device of FIG. In FIGS. 3 and 4, 9 is a vertical PNP transistor with the P-type diffusion region 3 in the N-type well 2 as the emitter, the N-type well 2 as the base, and the P-type semiconductor substrate 1 as the collector. , 10 is
This is a lateral NPN transistor having an N-type diffusion region 7 in a semiconductor substrate 1 as an emitter, a P-type semiconductor substrate 1 as a base, and an N-type well 2 as a collector. The base terminal of the vertical PNP transistor 90 is the N-type diffused @i region 5, and in reality, a parasitic resistance exists between this N-type diffusion region 5 and the N-type well 2, which becomes the active base region. Fourth
In the figure, the parasitic resistance is omitted for simplicity of explanation. Furthermore, the base terminal of the lateral NPN transistor 10 is the P-type diffusion region 8, and a parasitic resistance also exists between this P-type diffusion region 8 and the P-type semiconductor substrate 1, which becomes the active base region. In FIG. 4, the parasitic resistance is omitted as in the above case. Furthermore, although there are actually emitter and collector resistors of each parasitic bipolar transistor 9, 10, these resistors are also omitted in FIG.

Next, the mechanism by which the latch-up phenomenon occurs will be explained. Some kind of trigger is required to start latch-up, but in the above 0M08 circuit, the trigger current is a displacement current due to fluctuations in the power supply voltage VD, a substrate current flowing from an N-channel transistor, This is caused by punch-through current around the well boundary and drain junction leakage current.

In addition, generation of electron-hole pairs due to radiation incidence is also difficult.
Sometimes it becomes. Furthermore, the negative substrate bias potential ■
3. In a semiconductor integrated circuit device in which the voltage is generated by a substrate potential generation circuit (not shown) on the semiconductor substrate 1, the power supply voltage ■. When the 0 turn is turned on, the substrate bias potential BB is also temporarily raised to a positive potential due to capacitive coupling, which may act as a trigger.

When such a trigger current is injected, if its amount exceeds a certain value, latch-up begins. For example, the substrate bias potential VBB is temporarily raised to a positive potential as described above, and the trigger current generated thereby raises the base potential of the lateral NPN transistor 10 in FIG. 4 to a potential that is forward biased. Then, the lateral NPN transistor 10 is turned on.

However, this alone still does not lead to latch-up. In order to reach latch-up, the collector current of the turned-on lateral NPN transistor 10 flows from the N-type diffusion region 5, which is the well electrode, and the amount of current needs to reach an amount sufficient to turn on the vertical PNP transistor 9. When the vertical PNP transistor 9 is turned on and even a small amount of collector current flows through the transistor 9, the current flows toward the P-type diffusion region 8, which is the electrode of the semiconductor substrate 1, and the current flows toward the P-type diffusion region 8, which is the electrode of the semiconductor substrate 1. The active base potential of NPN transistor 10 is increased. As a result, the collector current of the lateral NPN transistor 10 also increases, causing positive feedback and leading to latch-up.

- In the membrane, the trigger current is often a transient noise. The trigger current value increases as the noise pulse width becomes shorter, and the latch-up resistance increases. This tendency stems from the fact that in order for the parasitic bipolar transistor to turn on, it is necessary to accumulate base charge.

When a trigger current is injected into the substrate 1, this current forward biases the active base region of the lateral transistor 0, but even if the current increases further, the lateral transistor 0 does not turn on immediately. This is because the trigger current is the base charge Q of the lateral transistor 0.
This is because it is used to accumulate. If the trigger current is cut off before this accumulation is sufficient, latch-up will not occur. Further, even after the lateral transistor 0 is turned on, the same process as described above is necessary for the vertical transistor 9.

[Problem to be solved by the invention]

The conventional semiconductor device is configured as described above, and the CM
The parasitic bipolar transistors 9 and 10 that originally occur inside the OS 4M structure combine to form a thyristor structure, and for example, when the power supply voltage VDD is turned on, the substrate bias potential ■BB temporarily becomes a positive potential due to capacitive coupling. By rising, the power supply voltage V - ground voltage■
A latch-up phenomenon occurs in which an excessive current flows between the semiconductor integrated circuit devices, which not only interferes with the operation of the semiconductor integrated circuit device but also thermally destroys the device itself.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a semiconductor integrated circuit device that can prevent the latch-up phenomenon caused by the parasitic thyristor inside the C'MO8 structure. do.

[Means for solving task i]

In the present invention, a first well of a second conductivity type is formed in a semiconductor substrate of a first conductivity type, a drain region and a source region of a first conductivity type are provided in the first well, and a first insulated gate is formed. A field effect transistor is formed, a drain region and a source region of a second conductivity type are provided in the semiconductor substrate, a second insulated gate field effect transistor is formed, and a substrate potential is applied to the semiconductor substrate. ,
A first reference potential is applied to the first well and the source region of the first insulated gate field effect transistor, and a second group Qf position is applied to the source region of the second insulated gate field effect transistor. In the semiconductor device to which a A potential was applied to the second well to give

[Effect]

In the semiconductor device according to the present invention, a pn junction capacitor is formed between the semiconductor substrate and the second well, and a reverse bias potential is applied to the pn junction, so that a trigger current that causes latch-up is injected. In this case, a portion of the trigger current also flows into the junction capacitance and charges are accumulated in the junction capacitance, which makes it difficult for the transistors forming the parasitic thyristor to turn on, thereby preventing latch-up from occurring. .

〔Example〕

FIG. 1 is a diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device shown in FIG. 1 is different from the conventional device shown in FIG. An N-type diffusion region 12 for obtaining ohmic contact is formed in the upper layer of the type well 11, and a ground potential VSS is applied through the N-type diffusion region 12. Note that the other configurations are the same as the conventional example.

FIG. 2 is a diagram showing an equivalent circuit of the semiconductor integrated circuit device of FIG. 1. The circuit shown in FIG. 2 is different from the conventional circuit shown in FIG. This is because a PN junction capacitor 1CSub has been added. Other points are the same as the conventional example.

Next, a description will be given of the operation when a trigger current that causes latch-up is injected into the semiconductor substrate 1 due to the substrate bias potential vBB rising to a positive potential when the power supply potential VDD is turned on, for example. This trigger current biases the base region of the lateral NPN transistor 10 in the forward direction as in the conventional case, but even if the current increases further, the NPN transistor 10 does not turn on immediately. That is, while this trigger current flows into the base region of the lateral NPN transistor 10 and is used to accumulate base charge, it is also consumed to charge the PNN junction sub at the same time, and compared to the conventional example, the trigger current flows into the capacitor C3UB. The lateral NPN transistor 10 becomes difficult to turn on as much as the current flows, and latch-up is prevented from occurring.

Furthermore, there is no need to introduce a new manufacturing process to form the capacitor C5ub according to the present invention, and the capacitor C5ub can be formed simultaneously using the conventional 0MO8 forming process.

In order to more reliably prevent latch-up, the area of the N-type well 11 fixed at the VB578 position for forming the capacitor fllCsub according to the present invention is reduced to the area of the N-type well 2 fixed at the power supply voltage vDD level. It is desirable to set it larger than the area.

In the above embodiment, an N-type well 2 is provided in a part of a P-type semiconductor substrate 1 to form an 0MO8 structure, but a P-type well 2 is provided in a part of an N-type semiconductor substrate to form an 0MO3 structure. The same problem as above occurs also when forming the film. In this case, another P-type well is formed in a part of the N-type semiconductor substrate other than the P-type well, and a PNN junction capacitance is formed between the P-type well and the semiconductor substrate. A potential is applied to the P-type well to provide a reverse bias to the PNN junction capacitance.

〔Effect of the invention〕

As described above, according to the present invention, a PN junction capacitor is formed between the semiconductor substrate and the second well, and a reverse bias potential is applied to the PN junction, which reduces the trigger current that causes latch-up. Even when a current of 1 is injected, turn-on of the transistor constituting the parasitic thyristor can be suppressed, and latch-up can be prevented from occurring.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a diagram showing an equivalent vii path of the semiconductor integrated circuit vt arrangement of FIG. 1, and FIG. 3 is a diagram showing a conventional semiconductor integrated circuit device. ! FIG. 4 is a schematic diagram showing an example of an integrated circuit device, and FIG. 4 is a diagram showing an equivalent circuit of the semiconductor integrated circuit device of FIG. In the figure, 1 is a P-type semiconductor substrate, 2 and 11 are N-type wells, 3 and 4 are P-type diffusion regions, and 6.7 is an N-type diffusion region. Note that the same reference numerals in each FIG. 4 indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2

Claims (1)

[Claims] (1) A first well of a second conductivity type is formed in a semiconductor substrate of a first conductivity type, a drain region and a source region of a first conductivity type are provided in the first well, and a first insulated gate electric field is formed. an effect transistor is formed, the semiconductor substrate is provided with a drain region and a source region of a second conductivity type to form a second insulated gate field effect transistor; a substrate potential is applied to the semiconductor substrate; 1
a first reference potential is applied to the well of the well and the source region of the first insulated gate field effect transistor, and a second reference potential is applied to the source region of the second insulated gate field effect transistor. In the apparatus, a second well of a second conductivity type is formed in a part of the semiconductor substrate, and a potential is applied to apply a reverse bias to a pn junction formed by the semiconductor substrate and the second well. A semiconductor integrated circuit device, characterized in that a voltage is applied to the second well.