JPH01211159A - Clock matching device for computer - Google Patents

Abstract

PURPOSE:To highly-accurately match the clock of a computer in a short processing time by correcting a time with the use of time data received from a master CPU and the data operated from the delay time of receipt with a slave CPU. CONSTITUTION:When a push button switch 7 is operated, and an interrupting signal to match the clock is generated, a master CPU 5 reads the time data when an interruption processing part 8 receives the signal from a clock mechanism 2, and accumulates them to a buffer 9. Next, a transmission processing part 10 transmits the accumulated clock data to respective slave CPUs 6. When the CPU 6 receives the interrupting signal, it reads the time data with the use of the clock mechanism 2, and accumulates them to a buffer 12. When the time data are sent from the processing part 10, a reception part 13 receives them, accumulates them to a buffer 14, and simultaneously informs a delay detecting part 11 of the reception. The detecting part 11 reads the received time from the mechanism 2, obtains the difference of the data in the buffer 12, obtains the delay time, adds it to the time data in the buffer 14, and obtains the correct time data.

Description

[Detailed description of the invention] [Industrial application field]

This invention provides a plurality of central processing units (hereinafter referred to as CPUs)
This invention relates to a computer clock adjustment device that adjusts the time of a clock mechanism built into each CPU in a computer distributed system in which CPUs are connected via a network.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional computer clock adjustment device. In the figure, 1 indicates a plurality of distributed CPs.
2 is a clock mechanism built into each of these CPUIs, 3 is a console connected to each of these CPUIs, and 4 is a network that connects these CPUIs to form a computer distributed system. Here, time data is the most popular key that indicates the order of state changes, and it also has the function of expressing quantitative timing such as time, so it is important to understand the occurrence of events and device access. , data transmission/reception, task run/wait tracing, etc. Therefore, each distributed CPU
Each of I has a built-in clock mechanism 2 as shown. Next, the operation will be explained. Here, in a computer distributed system, the time at which data is transmitted and received between each CPU 1 is an important key that indicates the order of operations, and it is an absolute requirement that the clock mechanism 2 of each CPU I is accurately matched. Therefore, if the transmission delay cannot be ignored, it is impossible to send and receive time data over the network 4 and adjust the time of the clock mechanism 2. By inputting time data, the time of each clock mechanism 2 was individually adjusted.

[Problem to be solved by the invention] Conventional computer clock adjustment devices are configured as described above, so manual intervention is required to adjust the clock, and it is not possible to completely eliminate errors in time data due to keystroke errors, etc.; When the number of CPUIs is large, there are problems such as a large amount of time required to adjust the clock. This invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a computer clock adjustment device that can adjust the clock tower in a short time without human intervention. [Means to solve the problem]

A computer clock adjustment device according to the present invention includes an interrupt signal generator that provides an interrupt signal for clock adjustment to a main CPU and a slave CPTJ, and causes the main CPU to perform an interrupt process for reading time data at the time when the interrupt signal is generated. Department and
The slave CPU is provided with a transmission processing unit that transmits the time data to the slave CPU, and the slave CPU includes a time data receiver unit that receives the time data, and a delay time from the reception time of the interrupt signal to the reception time of the time data. This device includes a delay detection section that detects the delay time, and a calculation section that outputs time data calculated from the delay time and the time data to the clock mechanism.

[For use]

The computer clock adjustment device according to the present invention controls the main CPU when an interrupt signal is generated from the interrupt signal generator.
The U reads the time data of the clock mechanism at the time when this interrupt signal is generated and sends it to the slave CPU, and the slave CPU detects the delay time from when the interrupt signal is generated until it receives the time data, and By correcting the time of the clock mechanism using the time data calculated based on the delay time and the received time data, it eliminates human intervention from setting the computer clock and prevents errors in time data due to keystroke mistakes etc. , reducing processing time.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 2 is a clock mechanism, 3 is a console, and 4 is a network, which are the same or equivalent parts to those in the conventional system denoted by the same reference numerals in FIG. 4, and detailed explanations thereof will be omitted. Further, 5 is a main cPU that sends time data for clock adjustment, 6 is a slave CPU that adjusts the time of the built-in clock mechanism 2 based on the time data from the main CPU 5,
Reference numeral 7 designates a push button switch as an interrupt signal generator that provides an interrupt signal for clock adjustment to the main CPU 5 and slave CPU 6. Furthermore, FIG. 2 is a block diagram showing the main parts of the upper CPU 5, and FIG. 3 is a block diagram showing the main parts of the slave CPU 6. In both figures, 2 is the clock mechanism, and 7 is the push button switch. It is. Further, in FIG. 2, reference numeral 8 denotes an interrupt processing unit that receives an interrupt signal generated by the pushbutton switch 7 and reads time data of the clock mechanism 2, and 9 a buffer that stores the time data read by the interrupt processing unit 8. Reference numeral 10 denotes a transmission processing section that transmits the time data accumulated in this buffer 9 to the slave CPU 6, and in FIG. a delay detection unit for detecting a delay time until receiving time data of 12;
13 is a time data receiving unit that receives the time data from the transmission processing unit 10; 14 is the time received by the time data receiving unit 13; A reception data buffer 15 stores the time data calculated based on the time data stored in the reception data buffer 14 and the delay time detected by the delay detection section 11 and stored in the buffer 12. This is a calculation unit that outputs to the clock mechanism 2. Next, the operation will be explained. When the pushbutton switch 7 is operated and an interrupt signal for clock adjustment is generated,
In the main CPU 5, the interrupt processing unit 8 that receives the interrupt signal reads the current time data from the clock mechanism 2 and stores it in the buffer 9. Thereafter, the transmission processing section 10 is activated and transmits the time data accumulated in the buffer 9 to each slave CPU 6. On the other hand, in the slave CPU 6, when the delay detection section 11 receives the interrupt signal, it reads the current time data from the clock mechanism 2 and temporarily stores it in the buffer 12. Thereafter, when time data is sent from the transmission processing section 10 of the main CPU 5, the time data reception section 13 receives it and stores it in the reception data buffer 14. At the same time, this time data receiving section 13 notifies the delay detecting section II that this time data has been received. Upon receiving the notification, the delay detection unit 11 reads the reception time of the time data from the clock mechanism 2, calculates the difference between the time data and the time data stored in the buffer mechanism 2, and calculates the difference as the delay time. It is stored again in the buffer 12. Here, this delay time corresponds to the time from when an interrupt signal for clock adjustment is generated until the time data is received, that is, the data transmission time from the main CPU 5 to the slave CPU 6. Therefore, the calculation unit 15 adds the delay time stored in the received data buffer 14 to the time data stored in the received data buffer 14,
By presetting the time data of the addition result in the clock mechanism 2, the time data of the clock mechanism 2 of the slave CPU 6 accurately matches the time data of the clock mechanism 2 of the main CPU 5, and the clock adjustment is completed. In the above embodiment, a pushbutton switch was used as the interrupt signal generator, but any other device other than the pushbutton switch may be used as long as it can detect events for which the accuracy of the clock is negligible. However, the same effect as in the above embodiment can be obtained.

【Effect of the invention】

As described above, according to the present invention, an interrupt signal generator that generates an interrupt signal for clock adjustment is provided, and the main
The PU reads the time data of the clock mechanism at the time when the interrupt signal is generated from this interrupt signal generator and sends it to the slave CPU.
The slave CPU detects the delay time from when the interrupt signal is generated until it receives this time data,
Since the time of the clock mechanism is corrected by the time data calculated based on the delay time and the received time data, human labor is removed from setting the computer clock, and errors in time data due to keystroke errors etc. can occur. This has the effect of providing a computer clock adjustment device with high accuracy (short processing time).

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a computer clock adjustment device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the main parts of its main CPU, and FIG. 3 is a block diagram showing the main parts of its slave CPU. , FIG. 4 is a block diagram showing a conventional computer clock adjustment device. 2 is a clock mechanism, 4 is a network, 5 is a main CPUυ, 6 is a slave CPU, 7 is an interrupt signal generator (push button switch), 8 is an interrupt processing section, 10 is a transmission processing section, 11 is a delay detection section, 13 15 is a time data receiving section, and 15 is a calculation section. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. 3rd 15th performance

Claims (1)

[Claims] In a computer distributed system in which a plurality of central processing units each having a clock mechanism are connected via a network, a computer clock adjustment device that adjusts the time of the clock mechanism of each central processing unit, wherein one of the central processing units
One is a main central processing unit and the other is a slave central processing unit, an interrupt signal generator is provided which gives an interrupt signal for clock adjustment to the main central processing unit and the slave central processor, and the main central processing unit is connected to the an interrupt processing unit that reads time data from the clock mechanism at the time when an interrupt signal is generated from an interrupt signal generator; and a transmission processing unit that transmits the read time data to the slave central processing unit;
The slave central processing unit includes a time data receiving section that receives the time data from the transmission processing section, and a period from receiving the interrupt signal from the interrupt signal generator to receiving the time data at the time data receiving section. a delay detection unit that detects the delay time of the clock mechanism; and a calculation unit that outputs time data calculated based on the time data received by the time data reception unit and the delay time detected by the delay detection unit to the clock mechanism. A computer clock adjustment device that is characterized by a