JPH01209956A - Resonance type converter - Google Patents

Abstract

PURPOSE:To enhance an efficiency by employing a FET element as a switching element of a parallel resonator, and starting supplying of a driving voltage to the element within a period of generating a parallel resonance pulse. CONSTITUTION:A DC/DC converter using a resonance converter switches a parallel resonator 1 formed of resonance capacitor CR and coil 12a by a FET transistor 2. The coil 12a employs the primary side coil of an output transformer 12. An oscillator 4 is provided in a driver 3 for driving the FET 2, thereby generating a pulse signal P1 of predetermined duty to be supplied to the base of a driving transistor 5. The FET 2 is started to be driven within a period for generating a resonance pulse, thereby starting supplying of a current to the coil 12a without time delay immediately after a resonance pulse is eliminated when a load current is increased to eliminate a damper period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a resonant converter that utilizes an LC parallel resonance phenomenon, and is particularly suitable for use in a device where the load current fluctuates.

[Summary of the invention]

A FET element is used as a driving element of the LC resonant circuit, and the FET element is used as the driving element of the LC resonant circuit.
By starting driving the element and gradually allowing the drive voltage to reach a predetermined voltage value, the load and
This is a resonant converter that allows stable driving even when the current and resonance pulse width fluctuate.

[Conventional technology]

Resonant type converters are known that convert electrical energy using parallel resonance between a coil and a capacitor. Figure 5 shows D using a conventional resonant converter.
A main part circuit diagram of the C-DC converter, and FIG. 6 is an equivalent circuit diagram of a resonant converter.

In this DC-DC converter, the drive transistor 21 of the drive circuit 20 intermittents the current flowing through the primary coil of the drive transformer 22.
A current ill having a waveform as shown in the operating waveform chart A in FIG. 7 is intermittently passed through the secondary coil of the motor. This current i is supplied to the base of the switching transistor 23, and the switching transistor 23 is turned on only during the period when the current i3 is flowing to the base.

The switching transistor 23 has a collector connected to the power supply line through the primary coil 24a of the output transformer 24, and an emitter that is grounded.

A resonance capacitor C1 is connected in parallel with the above-mentioned secondary coil 24a.
is connected, the negative side coil 24a and the capacitor C
11 forms a parallel resonant circuit 25.

When the switching transistor 23 is turned on at time t in the operating waveform diagram shown in FIG. 7, the positive side of the power supply E, the negative side coil 24a, and the transistor 23 (switch S?)
, the negative side of power supply E becomes a closed loop. As a result, the primary coil 2 passes through this closed loop as shown in FIG.
A coil current i+ (collector current tc) flows through 4a. As shown in FIG. 7B, this current it (ic) starts flowing from a time point t when a damper current i4, which will be described later, stops flowing, and thereafter increases linearly with time.

When the base current i@ is no longer supplied at time t in FIG. 7, the transistor 23 is turned off (switch S7 is opened). Therefore, the collector current IC stops flowing, and the parallel resonant circuit 25 becomes an independent circuit. However - next coil 2
A current ig due to the inertia of the inductance 4a flows in the same direction and charges the resonance capacitor C11.

As the current 12 flows and is charged, the capacitor C,
The terminal voltage V of I increases as shown in FIG. 7C. On the other hand, the current 12 gradually decreases as the terminal voltage V increases, and becomes zero when the terminal voltage vP reaches its peak at time t4, as shown in Figure 7.

The charge stored in the resonant capacitor CII is discharged through the primary coil 24a, and a resonant current i flows in the opposite direction as shown in FIG. Due to this discharge, the terminal voltage V of the resonant capacitors C and I gradually decreases as shown in FIG. 7C, while the reverse current i gradually increases as shown in FIG.

When the terminal voltage of the capacitor returns to its original value at time t0,
The back electromotive force that tries to cause current to flow in the same direction is the primary coil 2.
4a, and this back electromotive force causes the damper diode D+ to conduct (switch So in FIG. 6 closes).

Therefore, a damper current i4 in the same direction as the resonance current i3 flows as shown in FIG. 7E, and the parallel resonance vibration of the parallel resonance circuit 25 is converged.

Such a cycle is repeated, and the high voltage pulse generated by the resonant circuit 25 is boosted by the output transformer 24 and taken out from the secondary coil 24b. Then, the signal is rectified and smoothed by a rectifying diode D2 and a capacitor Cu, and then supplied to the load 26.

In order to drive the parallel resonant circuit, ideally, as shown in the operating waveform diagram A in FIG. All that is required is to turn on the transistor 23. However, due to variations in the capacitance and inductance of the parallel resonant circuit 25, the pulse width of the resonant pulse 27 may widen and overlap with the leading edge of the drive period, as shown by the broken line in FIG. 8B. In this case, a phenomenon called a kamitsuki phenomenon occurs in which the electric charge stored in the resonance capacitor C11 flows to the ground, so that a predetermined output cannot be obtained. This clumping phenomenon also occurs when the oscillation cycle of the drive pulse fluctuates and the drive period widens. Conventionally, this phenomenon has been prevented by delaying the start of operation of the switching transistor by dt and turning it on, as shown in FIG. 8C.

[Problem to be solved by the invention]

Current 1 flowing through the resonant coil 24a as the load increases
1, j4 increases as shown by the broken line in the eighth diagram, the damper period disappears.

Therefore, as shown by the arrow 28 in FIG. 8E, the resonance capacitor Cm is charged during the delay dtO after the resonance pulse 27 disappears, and the driving of the resonance coil 24a is delayed. For this reason, conventional resonant converters have the disadvantage that when the load current increases, the conversion efficiency deteriorates and the output decreases.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to enable stable driving even when load current, resonance pulse width, etc. fluctuate.

[Means to solve the problem]

The resonant converter of the present invention includes a parallel resonant circuit 1 including a capacitor C11 and a coil 12a or LV, an FET element 2 for driving the parallel resonant circuit 1, and a damper diode D1 for damping the parallel resonance, and a half period of the resonant period. A drive circuit 3 is provided which supplies the FET element 2 with a drive voltage (drive pulse P2) consisting of an off period W1 shorter than that of the FET element 2 and an on period W3 having a rising slope at the leading edge.

[Effect]

By starting to drive the FET element 2 during the period in which the resonance pulse 27 is generated, when the load current increases and the damper period disappears, the current is applied to the resonance coil without a time delay immediately after the resonance pulse disappears. begins to flow. Therefore, there is no loss of efficiency due to drive time delays.

At the start of driving, the parallel resonant circuit 1 is driven by reducing the gate input voltage ves of the FET element-2. If the voltage Vr, s is small, the resistance value between the drain and source is large, so even if the drive is started within the period when the resonance pulse 27 is generated, the charge stored in the resonance capacitor C1I through the FET element 2 will be reduced. The Kamitsuki phenomenon in which the electric current is discharged is alleviated.

When the current t+'(to) flowing through the resonant coil 12a becomes large, the gate-source voltage VCS has become sufficiently large, so that insufficient drive does not occur.

〔Example〕

FIG. 1 is a circuit diagram of a main part of a DC-DC converter circuit using a resonant converter according to an embodiment of the present invention. In this resonant converter, a parallel resonant circuit 1 consisting of a resonant capacitor C11 and a resonant coil 12a is switched by a transistor 2 (FET). Resonant coil 12a'
The primary coil of the output transformer 12 is used.

FET)-transistor 2 has its source electrode grounded and its drain electrode connected to the non-grounded side of parallel resonant circuit 1.

An oscillator 4 is provided in a drive circuit 3 for driving the FET transistor 2, and the oscillator 4 generates a pulse signal P with a predetermined duty and supplies it to the base of the drive transistor 5. The pulse signal P is the second
As shown in A of the operational waveform diagram in the figure, the pulse is generated with a period T and has a pulse width W.

(corresponding to the OFF period of the drive) is narrower than the width W2 of the resonance pulse 27 (FIG. 2B) generated in the parallel resonance circuit 1.

That is, when the inductance of the resonant coil 12a of the resonant circuit 1 is L1 and the capacitance of the resonant capacitor CR is C, the width W2 of the resonant pulse 27 is w, =π, 1. Therefore, the pulse width Wl is, for example, 0.9π, ρ7
A pulse signal P is generated so that .

The drive transistor 5 has an emitter that is grounded, and a collector that is connected to the positive electrode of a power source 6 through a resistor R0 having a large resistance value. Therefore, the drive transistor 5 operates during the high level period W of the pulse signal PI.
It is turned on at 1 and turned off at other times. Therefore, the low level period W1 (off period of transistor 2) of the drive pulse P2 taken out from between the resistor R0 and the collector and applied to the gate electrode of the FET transistor 2 resonates as shown in FIG. 2C. This is shorter than the period W2 in which the pulse 27 is generated.

Therefore, the FET transistor 2 is turned on while the resonance pulse 27 is generated, and remains on for a period indicated by W3. This on period W3 corresponds to the resonance pulse 27 shown in FIG. 2B.
This is longer than the occurrence interval W4.

FET) There is an internal capacitance C6 between the gate electrode and drain electrode of run raster 2 and between the gate electrode and the lease electrode.
゜, C11S exist, respectively. Therefore, the drive pulse P2 rises with a time constant determined by Ro, CGII, and c@s. In this embodiment, since the resistance value of the resistor R0 is increased, the rising time constant becomes large, and the drive pulse P2 rises with a gentle slope as shown in FIG. 2C.

Note that the slope of the rise of the voltage Vli1 is determined so that the drive does not become insufficient when the current i flowing through the resonance coil 12a becomes large. That is, the forward transfer conductance gl, which is the ratio of the change in the drain current I Out to a predetermined change in the gate-source voltage VIN, is given by the equation ouL. Therefore, the input voltage VI is greater than the slope corresponding to i+/gva, which is the slope obtained by dividing the current 11 flowing through the resonance coil 12a by the forward transfer conductance g.
The time constants (Re, CGD, and Ccs) are determined so as to give N.

Drive pulse P2 is applied and PET) run raster 2
When the on/off operation is performed, the parallel resonant circuit 1 is driven and the parallel resonant pulse 27 is generated as described above. This pulse voltage 27 is output from the secondary coil 12b of the transformer 12.
The voltage is rectified and smoothed using a diode D2 and a capacitor Cu to obtain a DC voltage.

If the load increases while operating in this way,
In the second diagram, the load current increases as shown by the broken line. Therefore, from the damper current i4 to the drain current i,
The position at which the damper switches to may fluctuate and the damper period may disappear. However, in the resonant converter of the embodiment, when the generation of the resonant pulse 27 ends, the FET1-run raster 2 is already driven with a small gate-source voltage ves. Therefore, immediately after the resonance pulse disappears, current starts flowing through the resonance coil 12a without any delay. Therefore, there is no reduction in efficiency due to drive time lag.

Even if the drive voltage is applied to the FET before the end of the resonance pulse 27, the drive voltage VGS is raised slowly as described above, so the drive pulse P! The run raster 2 (FET) does not turn on completely until a predetermined time has elapsed after the FET is applied.

Therefore, for a while after the drive voltage is applied,
The resistance value between drain and source is extremely high.

Therefore, due to variations in the circuit constants of the parallel resonant circuit l,
Even when the pulse width of the parallel resonance pulse 27 is widened, the charge stored in the resonance capacitor C11 is hardly discharged through the run raster 2 (FET). Therefore, even if the parallel resonant circuit l is driven at time t1 when the parallel resonant pulse 27 is generated, most of the charge stored in the resonant capacitor CR can be discharged through the resonant coil 12a, and a stable output can be obtained. It will be done.

Even if the circuit constant of the resonant circuit 1 varies in a decreasing direction and the parallel resonant pulse 27 becomes narrower by about 10%, the overlamp state between the resonant pulse 27 and the drive pulse P2 is maintained.

FIG. 3 shows a circuit diagram of a main part of a horizontal output circuit using the resonant converter of this embodiment. In this circuit, the CRT deflection coil is used as the parallel resonance coil.

are using. For this reason, coil L for parallel resonance.

If the power source VCC is directly connected to the power source VCC, the raster will be displaced due to the average input current, so the power source vec is supplied through a separate path through the horizontal ratio quadrature 7 to the primary coil 7a.

The capacitor CA connected in series with the resonant coil (deflection coil) Ly blocks direct current, and is charged by the power supply current flowing through the negative side coil 7a, forming the resonant coil and effectively functioning as a series power supply. doing.

Furthermore, a Zener diode IO is connected between the gate electrode of the FET run raster 2 and the ground to suppress the maximum value of the voltage VGs to a constant Zener voltage value.

The operation when used as a horizontal output circuit is the same as described above, and the parallel resonance circuit 1 can be efficiently driven by turning on the FETl-run raster 2 during the period in which the parallel resonance pulse 27 is generated. The snapping phenomenon does not occur. Therefore, as shown in FIG. 2F, the deflection coil L was used as a resonance coil.

A sawtooth current iR consisting of current 'I, 11% 13.14 can be passed satisfactorily. In addition, in the horizontal output circuit, the resonant pulse voltage vP generated in the parallel resonant circuit l
is boosted by the horizontal ratio quadrature 7, taken out from the secondary coil 7b, rectified and smoothed through a rectifying diode D, and then applied to, for example, the anode of a CRT.

FIG. 4 is a circuit diagram showing a modification of the drive circuit. In this example, the collector of the pnp type drive transistor 14 and the collector of the npn type drive transistor 15 are commonly connected, and the emitter of the transistor 14 is connected to the power source V.
CC is connected, and the emitter of the transistor 15 is grounded. Also, commonly connected collector and FET)
A parallel circuit including a resistor Ro and a diode D is provided between the gate electrode of the run raster 2 and the gate electrode of the run raster 2.

Therefore, when the pulse signal P3 is applied to the base of each transistor 14, 15, the low level of the pulse signal P turns on the transistor 14 and turns off the transistor 15. Therefore, the collector current flows through the resistor R0, and the voltage generated there serves as the drive pulse PK of the FET)
Applied to the gate electrode of run raster 2. As described above, the drive pulse P2 rises with a time constant determined by Ro and C15CGs.

When the pulse signal P is inverted to a high level, the transistor 14 is turned off and no collector current flows through the resistor R0, and the transistor 15 is turned on and the diode D becomes conductive. Therefore, the potential of the gate electrode of the FET run raster 2 instantly becomes the ground potential, and the drain current to (coil current 1+) is abruptly cut off. That is, the rise of the drive pulse P2 becomes steep. Note that the high level period and low level period of the pulse signal P are opposite to those of the pulse signal P described above.

In the above embodiment, the time constant circuit is constructed using the capacitance between the electrodes of the FET run raster 2, but the time constant circuit may be constructed by providing an independent capacitor.

Alternatively, the rise of the pulse signal P1 generated by the oscillator 4 may be sloped before being applied to the drive transistor 5, and the output of the transistor 5 may be amplified by a linear amplifier and supplied to the gate electrode of the FET1-run raster 2.

〔Effect of the invention〕

As described above, the present invention uses an FET element as a switching element of a parallel resonant circuit, and starts supplying a drive voltage to the FET element during a period in which a parallel resonant pulse is generated in the parallel resonant circuit. Therefore, since the parallel resonant pulse and the drive voltage overlap, when the load current increases and the damper period disappears, current starts flowing through the resonant coil immediately after the end of the resonant pulse, causing a time lag in the drive. Does not occur. Moreover, even if the circuit constant of the parallel resonant circuit varies toward the smaller side and the pulse width of the parallel resonance decreases, the overlap state is guaranteed.

Therefore, even when the load current increases, stable output can be obtained without reducing conversion efficiency.

Furthermore, since the rise of the drive voltage has a slope, the resistance value between the drain and source of the FET element increases for a while after starting the drive. Therefore, even if the resonant pulse and the drive voltage overlap, especially if the circuit constant of the resonant circuit is varied to the extent that the overlap period becomes long enough,
There is no reduction in output due to invalid discharge of the charge charged in the resonance capacitor. Further, when the coil current becomes large, a sufficiently large drive voltage is applied to the FET element, so that insufficient drive does not occur.

Therefore, according to the present invention, the conflicting disadvantages of the clumping phenomenon and drive delay are simultaneously eliminated, and a converter with extremely high efficiency can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of the main parts showing one embodiment of the resonant converter of the present invention, Fig. 2 is an operation waveform diagram for explaining the operation of each part, and Fig. 3 is an embodiment different from Fig. 1. FIG. 4 is a circuit diagram of a main part of a resonant converter showing a modified example of the drive circuit, FIGS. 5 to 8 show a conventional example, and FIG.
6 is an equivalent circuit diagram of FIG. 5, and FIGS. 7 and 8 are operating waveform diagrams. In addition, in the symbols used in the drawings, l・−・−・・−・−・・−・−Parallel resonant circuit 2−・−
・・・・・−・・・FET) Run raster 3・・・・
・-・-・-・・----Drive circuit 12 a
SL y--------One resonance coil CR・----
・・・・−Resonance capacitor D, −1・・−1−−−
--- It is a damper diode.

Claims (1)

[Claims] A parallel resonant circuit of a capacitor and a coil, an FET element that drives the parallel resonant circuit, a damper diode that damps the parallel resonance, an off period shorter than half the parallel resonant period, and a rising edge at the leading edge. and a drive circuit that supplies the FET element with a drive voltage consisting of an on period having a slope.