JPH01205678A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To reduce the area of a comparator in a chip by using one comparator so as to discriminate to which of plural stages of levels the brightness belongs. CONSTITUTION:An electric charge is generated when a light is radiated to a photoelectric conversion section and the electric charge is stored in a storage section. On the other hand, the luminous quantity radiated to the photoelectric conversion section is monitored by a brightness monitor means, the generated electric charge is stored in a storage means, a signal in response to the quantity of the stored charge is outputted from an output means and inputted to one input of the comparator 45. On the other hand, a reference voltage generating circuit RVC generates plural stages of reference voltages and they are inputted to the other input of the comparator 45. Thus, the comparator 45 compares the plural reference voltages with the output from the output means 10-2 to decide to which or plural stages the brightness corresponds. Thus, the area of the comparator in the chip is reduced considerably.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a solid-state imaging device used in a camera automatic focus detection device or the like.

<Prior art> In a solid-state imaging device, the charge generated in the photoelectric conversion unit is accumulated in the storage unit and integrated, but if the amount of light incident on the photoelectric conversion unit is small, the integration time becomes longer, which causes inconvenience. There are many cases. Therefore, a common method is to install a photodiode for brightness monitoring to monitor the amount of light irradiated to the photoelectric conversion unit, and when the brightness is low, the output from the storage unit is multiplied by a multiplier according to the brightness. .

Conventionally, such solid-state imaging devices have been designed to manually input signals representing brightness from a photodiode for brightness monitoring to multiple comparators to determine which of multiple levels the brightness belongs to. be. (Unexamined Japanese Patent Publication No. 6
0-125817 Publication) <Problems to be Solved by the Invention> However, in a structure in which brightness is determined by a plurality of comparators as in the above-mentioned conventional solid-state imaging device, the area occupied by the comparators on the chip becomes extremely large. However, there is a problem in that other circuit components cannot be sufficiently mounted on the chip.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the area occupied by the comparator on a chip by making it possible to determine which of a plurality of levels luminance belongs to using a single comparator.

<Means for Solving the Problems> In order to achieve the above object, the solid-state imaging device of the present invention has the following features:
As illustrated in Figure 1.8, there is a photoelectric conversion section (FD) that generates charges corresponding to the light incident on each pixel, and a storage section (ST) that accumulates the charges generated in the photoelectric conversion section (PD). ), a brightness monitor means (9) that generates a charge according to the amount of incident light and monitors the light m irradiated to the photoelectric conversion unit (PD), and a charge generated in the brightness monitor means (9). an accumulating means (10-1) for accumulating a charge, an output means (10-2) for outputting a signal corresponding to the amount of charge accumulated in the accumulating means (10-1), and a plurality of reference voltage levels. a plurality of base outputs from the base 2A voltage generation circuit (RVC);
The present invention is characterized in that a single comparator (45) for comparing the output from the output means (10-2) and determining the brightness in a plurality of levels is formed on the same chip.

<Operation> When the photoelectric conversion unit (PD) is irradiated with light, an electric charge is generated,
This charge is stored in the storage section (ST). - On the other hand, the amount of light irradiated to the photoelectric conversion unit (PD) is measured by the brightness monitor means (9)
monitored by The charges generated in the brightness monitor means (9) are accumulated in the accumulation means (10-1), and a signal corresponding to 9 of the accumulated charges is outputted from the output means (10-2) and sent to one comparator (45). ) - to be powered by the power of all people. On the other hand, Ki Q7! A plurality of levels of base Q voltages are generated in the voltage generating circuit (RVC), and these are input to the other input of the comparator (45). Therefore, one comparator (45) compares the plurality of reference voltages and the output from the output means (10-2) to determine which of the plurality of brightness levels. Photoelectric conversion unit (PD) created on the same chip in this way
, a brightness monitor means (9), and a reference voltage generation circuit (RV
C) and one comparator (45), the brightness is determined into multiple levels.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

First, a first example will be described. FIG. 1 shows the configuration of an image sensor (13) manufactured as a COD.

(1) is a photodiode array consisting of a plurality of photodiodes (PD) as photoelectric conversion means that generate charges according to the amount of incident light, and (ST) is an accumulation section that accumulates charges generated by the photodiodes (PD). , (B.G.
) is a field-effect transistor (hereinafter referred to as a field-effect transistor), which is a gate provided between a photodiode (PD) and a storage section (ST).
It is called FET. ), and this barrier gate (BG) connects the photodiode (PD) and the storage section (ST) when voltage is applied, and transfers the charge generated in the photodiode (PD) to the storage section (ST). On the other hand, when no voltage is applied, the photodiode (P
D) and the storage section (ST) are separated, and the photodiode (P
Stop the charge generated in step D) from flowing into the storage section (ST). In addition, (RG) is a transfer register that transfers charge from left to right in the drawing by two-phase drive, and (SH) is a storage unit (ST
) and a transfer register (RG). This transfer gate (SH) connects the storage section (ST) and the transfer register (RG) when a voltage is applied, and transfers the charge accumulated in the storage section (ST) to the transfer register (RG). When not applying, the storage section (ST) and transfer register (RG) are separated to prevent charges accumulated in the storage section (ST) from flowing into the transfer register (RG). Further, (RGtCC) is an integral clear gate consisting of a gate FET. This integral clear gate (RGICG
) connects the transfer register (RG) and overflow drain (ODI) when voltage is applied, and before integration,
Photodiode (PD) and storage section (ST) of each pixel
) is discharged from the transfer register (RG) to the overflow train (ODI). The overflow drain (ODI) is connected to the power supply voltage VDD and has the lowest potential.

On the other hand, an overflow gate (OG) is provided between the photodiode (PD) and the overflow drain (OD2).
No voltage is applied to G), and the potential is always fixed to be lower than the potential of the barrier gate (r3G) when no voltage is applied. The charge of each pixel transferred to the transfer register (RG) is sequentially transferred to the capacitor (8-1) from the right side in the drawing by transfer locks φ, φ. The capacitor (8-1) is connected to the FE prior to the charge being transferred.
The OSR8 signal applied to the gate of T(8-3) resets charging to +π source and U voltage. Thereafter, the potential of the capacitor (,8-1) decreases from the charging voltage by the transferred charge. The voltage between the terminals of this capacitor (8-1) is taken out as an OS signal by a buffer (8-2). Although (8-1) has been described here as a capacitor for convenience of explanation, it can be replaced with an I)N junction of a diode, and when the circuit is integrated, this capacitor is manufactured as a diode. Hereinafter, the same applies when referring to a capacitor. - On the plurality of photodiodes (r'D) at the ends of the photodiode array (1), a light-shielding AQ film (1-ri) is provided in order to take out the black base fermentation image output, which will be described later.

The photodiode array (1) detects pixels necessary for the automatic focus detection system using blocks on both sides except for the central area.
) corresponds to unused pixels that are unnecessary for the automatic focus detection system. Therefore, the center photodiode (FD) of the photodiode array (1) corresponding to the unused pixel is removed, and the output processing of the brightness monitor photodiode (9), which will be described later, is placed in this removed area. A part of the circuit for this purpose is inserted (see Figure 21).

In addition, in order to control the integration time of the image sensor (13), a brightness monitoring photodiode (9) is provided as a brightness monitoring means for monitoring the amount of light incident on the photodiode (PD). There is.

This brightness monitor photodiode (9) has an elongated shape because it is formed across two blocks on both sides of the photodiode array (+) that detects the pixels necessary for the automatic focus detection system. 8. In addition, this brightness monitoring foot diode (9) is provided with a film A (film (9
-1) is shielded from light. A part of the circuit for output processing of this brightness monitor photodiode (9) is connected to the second
As shown in Figure 1, the photodiode (PD) of the photodiode array (+) is inserted in the removed center.

As mentioned above, the luminance monitoring photodiode (9) has an elongated shape, and when its length is ρ and the output is taken out from one end, the length Q and the response time τ are generally
The relationship τ■Q2 holds true, and the longer the length Q, the more rapidly the responsiveness deteriorates. Therefore, in order to prevent responsiveness from deteriorating, a photodiode for brightness monitoring (
The output is taken from near the center of 9). For this reason,
Compared to the case where a contact is provided at the end of the photodiode (9), the response time is as shown in the following equation. /4.

A capacitor (10-1) serving as a storage means is connected to the brightness monitor photodiode (9), and prior to integration of the image sensor (I3), FF:T(IQ
When the AGCR8 signal is applied to the gate of -3), the capacitor (to-1) is charged to the power supply voltage VDD. After the A G CRS signal is removed, the potential at the capacitor (to-H) drops due to the charge generated in response to light irradiation. This potential is applied to the buffer (10-
2) and is output as the AGCO8 signal.

The compensation diode (11) is provided to remove the dark output of the brightness monitoring photodiode (9), and a light-shielding AQ film (11-1) is provided thereon. This compensation diode (11) is designed to obtain the same amount of output as the dark output of the brightness monitor photodiode (9), but if it has the same structure as the brightness monitor photodiode (9). This requires the same area as the brightness monitoring photodiode (9), resulting in an increase in depth size. Therefore, as shown in FIG. 7(a), this compensating diode (11) consists of a large number of parts separated from each other and arranged at regular intervals, and these parts are divided into P-type parts. By embedding it in the dark area, the length (peripheral length) La of the PN junction on the surface, which is the source of the dark output, is increased, and the same amount of dark output can be achieved with a smaller size than the brightness monitor photodiode (9). It is designed to provide the following.

The compensation diode (11) is connected to the capacitor (12-■
). This capacitor (12-■) is connected to the FET (12-3) prior to integration of the image sensor (13).
) is charged to the power supply voltage VDD by the AGCR9 signal applied to the gate. However, after the AGCRS signal is removed, the potential of the capacitor (I2-1) gradually decreases due to the dark output charge of the compensation diode (11). This potential is output as a DO3 signal via a buffer (12-3). This concludes the description of the configuration of the image sensor (13).

Next, the overall hardware configuration will be explained along the block diagram of FIG. (14) in the middle of FIG. 2 is a microcomputer (μCom) which is a control means for controlling the drive of the image sensor (I3).

The image sensor control section (16) of this microcomputer (I4) controls the image sensor (I3), which will be described later.
Two signals MD, , MD for switching between two modes
In addition to outputting two signals NB, , NB, for giving the output of 2 and the operation timing, the TINT signal indicating whether the integration is completed or not and the A/D of the image sensor output are output from l10) < buffer (22). An ADT signal which is a logical sum with an ADS signal indicating the start of conversion is input, and a gain information Gl, 03 signal is input using signal lines of the NB, , NB, signals.

The circuit on the left side of the above microcomputer (I4) is
It is constructed on a 1-chip IC. Among these, the above I1
The 0 buffer (22) has the following functions. That is, a function of ORing the TINT signal and ADS signal and outputting it to the microcomputer (I4) as an ADT signal;
NB, , NB + when input by switching the human output of the signal line of the signal.

A signal of N B is manually input from the microcomputer (14), and when outputting it, G1. The function of outputting the G3 signal to the microcomputer (I4), the signal level of the microcomputer (I4), the frequency dividing circuit (+9), the integration time control section (20), the signal processing timing generation section (2I
) and a signal level in a circuit such as a transfer lock generating section (30).

On the other hand, the mode selection circuit (23) is a circuit that decodes the MD, , MD2 signals and selects one of the following four modes. MD, -“L”.

In the case of MD, -“L”, the mode selection circuit (23) is ■N
Set only the l signal to "■]" and select INN mode.

The INI mode is a mode for initializing the image sensor (13). MD, = “L”.

When M D t = “H”, the mode selection circuit (23)
■ Bind only the NT signal to "i-1" and select the INT mode. The INT mode is a mode in which the image sensor (13) performs integration. MD, - “I”, MD, - “I”
1", the mode selection circuit (23) sets only the DDI signal to "I" and selects the DDI mode. The DDI mode is a mode for starting reading of the image sensor (13), and the mode selection circuit (23) sets only the DDI signal to "I" and selects the DDI mode. .This is also a mode in which sample bolding of early black pixels described below is performed using the NB signal.In the case of MD, -“■]”, MD, -“L”, the mode selection circuit (23) selects only the DD2 signal. "I1" and select DD2 mode. In DD2 mode, the image sensor (+3) is read out, and the read and processed output of the image sensor (13) is sent to the A/D of the microcomputer (14). This is the mode for transmitting to the converter (15).The operation and function of each mode will be described later.

The above frequency dividing circuit (19) is a microcomputer (14)
The basic clock CP generated in the clock generating section (18) of
The image sensor (13) transfer lock φ1. The clock φ that is the source of φ. At the same time,
Integral time control section (20) and signal processing timing generation section (
21), a timing clock φ for synchronizing with the clock φ0 is generated.

The above clock φ. is sent to the transfer lock generation section (30), where S sent from the integral time control section (20)
H times signal RG I CG times signal clock φ.

As a result, the clock φ8. φ, and serves as a transfer lock for the image sensor (13). The integration time control unit (20) uses the clock φ sent from the frequency dividing circuit (19) based on the timing signals NB, NB, sent from the microcomputer (14) when in the INI-E-mode and INT mode. The AGCR5 signal, the BG multiplied signal, the SH multiplied signal RGICG signal are generated in synchronization with the above signal, and the integration start operation is performed. Each of the above signals is applied to each part of the image sensor (I3) shown in FIG. In addition, the integral time control section (
20) is the integration completion signal VFLG from the brightness determination circuit (24), which is a subtraction means, which becomes "L" - "H" when the integration of the image sensor (13) becomes appropriate, or the mode selection circuit (23) Timing signal N B transmitted when the DDI signal from 1. N B
t, a BG multiplied signal is generated and the integration is completed.

Furthermore, this integration time control section (20) is configured so that the DDI signal is “
When the timing signal NB is high, the timing signal NB.

NB generates a signal times SH and performs an operation to start reading the output from the storage section (ST). At this time, a signal for obtaining luminance information, which will be described later, an SH multiplied signal, and φa, φb, and φC1φd signals are transmitted to the luminance determination circuit (24). The brightness determination circuit (24) is an image sensor (
13) Monitor the amount of light irradiated to the image sensor (13) by the AGCO9 signal and DOS signal sent from
When it is determined that the integral has reached an appropriate level, VF
A function to invert the LG signal and convert the integration to VFLG at low brightness.
In the case of a signal inverter, it has a function of determining the level of integration and outputting G], G3 signals for switching the gain of the image sensor (13) according to the determined level.

AGC differential amplifier circuit (25) is an image sensor (13)
This circuit amplifies the output signal O8 sent from.

In this AGC differential amplifier circuit (25), the FET (8) of the image sensor (13) is turned on by the 09RS signal.
-3), the potential O8 immediately after the capacitor (8-1) is charged is sampled and held by the R9S/H signal sent from the signal processing timing generator (21), and then this potential O8 is transferred to the capacitor according to the lock. (8
The difference between the potential O8 of the capacitor (8-1) which has dropped due to the generated charge of each pixel transferred to the OB subtraction AGC differential amplifier circuit (26 ). The gain during amplification of the OB subtraction AGC differential amplifier circuit (26) is determined by the brightness determination circuit (24)
It is switched by the G3 signal output from the G3 signal. O above
The B subtraction AGC amplifier circuit (26) performs differential amplification between the output of the black-based parrot pixel and the output of a normal pixel without Aρ light shielding, that is, an effective pixel, and samples and holds the output V os'. Since a photodiode (PD) always has an output in the dark, a photodiode (PD) with Af2 light shielding is used.
) is used as a black reference pixel and is used as the base pixel of the dark output, and the value obtained by subtracting the black reference pixel component from the output of the normal pixel is used as the output of the image sensor (I3). The above OB subtraction AGC amplifier circuit (26)
Since the output Vos' from the AGC differential amplifier circuit (25) is repeatedly input in synchronization with the transfer lock,
OSS sent from the signal processing timing generator (21)
/HSS/Up, the level of the signal output Vos' of the effective pixel is sampled and held, and the output Vos' is output while the black reference pixel is being output by the OBS/H signal sent from the signal processing timing generator (21). Hold the sample. The OB subtraction AGC amplifier circuit (26) converts the sampled and held black reference pixel output level Vos' from the sampled and held effective pixel signal output level Vos'.
is subtracted, and multiplied by a gain switched by the G3 signal output from the brightness determination circuit (24), and outputted as a signal Vos below the analog reference voltage V ref.

The temperature detection section (27) detects the temperature using a resistance divider circuit shown in FIG. This resistance divider circuit (27
) includes a diffused resistor (32) formed by diffusion and a resistor (33) made of polysilicon (Poly-3i), which are designed to have the same resistance value at room temperature. Since each of the resistors (32) and (33) has a different temperature coefficient, the output V TMP outputted from their connection point via the buffer (34) depends on the temperature with V ref/2 as the center. . In addition, the analog switch (
31) is T5Tn= "t," in DD2 mode.
Therefore, the current consumption is reduced by turning off the analog switch (31).

On the other hand, the analog switch (28) shown in FIG.
The analog switch (29) is turned on when the mode is DD2-"I-1", and conversely, the analog switch (29) is turned on when DD2="I-1". With this, when using DD2 mote,
The signal Vos is output as the output Vout, and the signal VTMP is output as the output Vout except in the DD2 mode.

The above signal Vout is input to the A/D converter (15) in the microcomputer (14), where A/D conversion of the analog output on the lower voltage side than the analog reference layer pressure Vref is started with the ADT signal, and the gain is being converted to digital data. This concludes the explanation of the hardware configuration.

Next, the operation of each mote of the image sensor (13) described above will be explained in detail.

First, the initialization mode will be explained.

The microcomputer (14) is MDI-"I7".

When MI)2-“■7” is output, the mote selection circuit (2
3) sets only the INI signal to "I-1" and notifies the integration time control section (20) that it is the initialization mode (INI mode). INI MOTE is an image sensor.
After turning on the power of J-(13), immediately connect the image sensor (1
3) This is a mode for discharging unnecessary charges. After the image sensor (13) is turned on, it has a potential well (F11 diode (PI)) and a storage section (S
Unnecessary charges are accumulated in each of the transfer registers (RG) and the image sensor (I3
) needs to be started up so that it can be used.

Therefore, in order to quickly discharge unnecessary charges, the INI mode was set, and the potential structure of the image sensor (I3) was changed to the structure shown in FIG. 3.

Hereinafter, the potential diagram in FIG. 3 and the time chart in FIG. 4 will be explained. In FIG. 3(a), from the left side are an overflow drain (OD2), an overflow gate (OG), and a photodiode (PD).

barrier gate (BG), storage section (ST), transfer game)
(S H), transfer register (IIG), integral clear gate (RG I CG), overflow drain (O
Dl). When voltage is applied to the barrier gate (BG), f3 sending gate (SH), integral clear gate (RGICG), and transfer register (RG) (φ1 is applied to the transfer register (RG)), the 3
As shown in figure (b), PD>BG>ST>SH>RG
The potential is designed so that >RG I CG > ODl, and the photodiode 0'r)), the storage part (
ST), the unnecessary charges in the transfer register (r?G) are discharged to the overflow [hood drain (ODl)] at this time. This operation will be explained along time chart 1.

The state in FIG. 4(a) corresponds to FIG. 3(a).

At this time, NF2. -I,", NH4-- In the "L" state, no voltage is applied to the barrier gate (BG), transfer gate (Sll), and integral clear gate (rtctcc), and the photodiode (1)D).

Unnecessary charges are accumulated in each section of the storage section (ST) and transfer register (RG). When both N 131 and N Bx are "L", the integral time control section (20) that controls the image sensor (13) does not perform any operation on the image sensor (13).

The microcomputer (14) is NF2. -“■1”.

When N T3 is output as −“I7”, the integral time control unit (2o) receives the clock φ sent from the frequency dividing circuit (19).

In synchronization with, 5II=
“I-T”.

r3G-“H”, IIGICG-“■]” are output to the image sensor (I3). Furthermore, S H signal, RG
The ICG double signal is also sent to the transfer lock generation unit (30), and the SH double signal clock φ is sent to the transfer lock generation unit 11 (30). The OR output of RG is transferred to lock φ1, and RG
ICG signal and φ. In the case of ST-1-“I]” and RGICG-“I]”, the image sensor (13 ), and the image sensor (13) is locked to SH, BG, FtGI.
CG, φ1. As shown in FIG. 3(b), each signal φ causes the photodiode (FD) and the storage section (S
T), drain unnecessary charges from the transfer register (RG).

The microcomputer (14) then calculates N B r =
After outputting “I””, NB, = “l(”, NB, -L
”.

N 132 - Output “II”. In response to this, the integral time control section (20) sets the clock φ. Synchronize with 5I-
1 signal and BG double signal “L” (Figure 3 (C),
Figure 4(C)). On the other hand, in the transfer lock generation unit (30), the transfer lock φ1 starts to move as the S I-1 signal returns to “L”, and the transfer lock φ is at “L”.

At this time, the bottom step difference between the transfer register (rtG) and the overflow drain (ODI) increases, promoting the discharge of unnecessary charges from the transfer register (RG), and completely discharging them to the overflow drain (ODI) (third
Figure (d), Figure 4 (d)). Also, at this time, since the transfer lock φ remains stopped at "L", another transfer register (RG) adjacent to the above transfer register (RG) and to which the transfer lock φ is applied. − register (
RG) will not flow in.

After the timer measures that a predetermined period of time has elapsed, the microcomputer (14) controls NB, NF2 . Together “
■Return to 7''. The integral time control unit (20) thereby synchronizes with φ. and sets the RG I CG multiplied signal to “L”. Then, the voltage applied to the RGICG terminal of the image sensor (13) becomes zero, and this integral clear gate (R
GICG) is closed. At the same time, in the transfer lock generating section (30), the RG I CG double signal becomes "17", so the transfer lock φ2 also starts moving (Fig. 3(e)).
, Fig. 4(e)). With this, one cycle of unnecessary charge discharge operation is completed.

Normally, when initializing the image sensor (13), the above-described unnecessary charge discharge operation is repeated several cycles, and then the initialization mode is ended.

In the present invention, the structure in which an integral clear gate (RGICG) is connected to each register (I(G)) eliminates the need to discharge unnecessary charge from each register (RG) by transferring it from the register (RG). It would be possible to shorten the time for one cycle of one unnecessary charge discharge operation and shorten the time allocated to the initialization mode.

Next, the second mode, the integral mode, will be explained.

The microcomputer (14) is MD, -"Shi".

When MD2-“T-1” is output, the mode selection circuit (2
3), only the INT signal is set to “H”, and the integration time control section (
20) to notify that it is in integration mode (INT mode). In the INT mode, the image sensor (13) starts integrating and ends the integration during high brightness.

The operation will be explained by l() in FIGS. 5 and 6. The starting operation of integration is the operation of discharging unnecessary charges during initialization, and the operation of 1
Exactly the same except for the 00 signal. BG times signal NB,=
“H”, NBt-“L” are microcomputer (14
) is output, the integral time control section (20) outputs φ. (
In the figure, it is the period when φ1 is rising.
11". This is the same as in the INl mode. However, if the microcomputer (14) outputs NB, -"L", NB2 - "I(", I
φ in NI mode. synchronized with the BG double signal “L” again.
”, but in INT mode, the BG double signal “[■
”.The BG double signal remains “L” at the end of the integration described later.
” becomes.

At the time of Fig. 5(C) and Fig. 6(c), the transfer gate (SH
When the gate voltage of the photodiode ( The charges generated in the PD) flow into the storage section (ST) and begin to be accumulated in the storage section (ST), and integration is started in the image sensor (13).

On the other hand, the time point at which the integration ends is monitored by the output of the brightness monitoring photodiode (9). Below, brightness 'I'
The operation of the l+ constant circuit (24) will be explained, and the operation for completing the integration will be explained.

The integration time control section (20) outputs the AGCIS signal to the image sensor (13) at the same timing as the SI-1 signal at the start of integration. As shown in Figure 1, AGC
The Rs signal is transmitted through the FET (
The gate of FET (10-3) is connected to the capacitor (12-1) which is connected to the compensation diode (11).
+2-3). By applying the AGCRS signal, the capacitor (It)
-1) and (11-1) are charged to approximately the power supply voltage VDD. AGCR9 signal goes “L” at the same timing as SH double signal
At this point, the power supply is cut off, and from this point on, the brightness monitoring photodiode (9) generates a charge according to the irradiated light 1, and the capacitor (10-■) connected to it generates a charge according to the irradiated light 1.
The potential begins to drop in response to the generated charge. On the other hand, the compensation diode (II) generates a charge due to its dark output, and the capacitor (12-1) connected to it generates a charge.
Also, its potential begins to drop in response to the generated charge. Each potential is outputted to the analog circuit shown in FIG. 8 of the brightness determination circuit (24) in FIG. 2 via each buffer (1o-2) and (I2-2). In Figure 8, AGCO9
The signal is manually input to the positive input of an operational amplifier (hereinafter referred to as an operational amplifier) (43), and
The O8 signal is input to the negative input of the operational amplifier (43), and the differential output is output from the operational amplifier (43). The output V 43 of the operational amplifier (43) is expressed by the following formula.

V43-Vref (DOS AGCOS) This output v43 is the luminance judgment means - comparator (45
) is input to the negative input.

On the other hand, the positive voltage of the comparator (45) is the FET (46°47.
A constant voltage generated by resistance division according to 48.49) is supplied. During integration, only φd is “H”, FET (49) is turned on, and the supplied constant voltage is V.
4e-(Vref-vth). Comparator (4
5) output is “I-1” when V 43 < V 4e
becomes. That is, Vref - (DOS - AGCOS) < Vref - Vt
When hDO8-AGCOS>Vth, it becomes "I1".

(DOS-AGCOS) indicates a voltage dropped due to light irradiation from the brightness monitoring photodiode (9) (the dark output component is compensated by the output of the compensation diode (11)). Immediately after the start of integration, the amount of light irradiated to the brightness monitor photodiode (9) is insufficient, and DOS-
AGCO9=O, and the output of the comparator (45) (
VFLG) is set to L”.During integration, (DOS-A
At the point when GCOS) becomes greater than the voltage v th, the integration for the image sensor (13) becomes appropriate, and the output (VFLG) of the comparator (45) changes from "L" to "I".
-1". As shown in the time chart of FIG. 6, the integral time control section (20) controls the comparator
When the output VFLG of 45) is inverted, the BG double signal “
■ When the BG double signal becomes “L”, as shown in Fig. 5 (c
), the potential of the barrier gate (BG) is smaller than that of the photodiode (PD), preventing the charge generated in the photodiode (I'D) from flowing into the storage section (ST). , storage section (ST
) is held when the VFLG signal becomes "II", that is, the I3G signal becomes "L", and the integration ends. The charge generated after the completion of integration is transferred to the photodiode (
PD), and as the accumulation progresses, Figure 5 (e)
As shown in FIG. 2, it crosses the overflow gate (OG), which has a lower potential than the barrier gate (BG), and is discharged to the overflow train (OD2), so it does not flow into the storage section (ST).

Further, the integration time control unit (20) sets the BG multiplied signal to "L" and simultaneously sets the TINT signal to "L", and notifies the microcomputer (14) of the inversion of the TINT signal via the ADT terminal. This concludes the explanation of the integration start operation in the integration mode and the integration end operation during high brightness.

Next, the third mode, data read mode 1 (DDI
mode).

The microcomputer (I4) is M D +-“I(”
.

When MDt="II" is output, the mode selection circuit (23
), only the DDI signal is set as “■!”, and the integral time control section (
20) to notify that it is in DDI mode. The DDl mode is a mode in which the integration is completed when the luminance is low, and the reading of each pixel data of the image sensor (13) is started.

First, the integration termination operation at low brightness will be explained based on the time chart of FIG. 22. When the subject brightness is low, it may take a long time until the brightness determination circuit (24) determines that the appropriate integration time has been reached. If integration is performed for a long time, the dark output increases, leading to deterioration of the S/N ratio. Furthermore, an extremely long integration time is inconvenient from a system perspective.

For example, when used in a focus detection device for a camera, the focus detection cycle becomes long, resulting in the inconvenience that the focus detection cannot follow the movement of the subject. For this reason, the longest allowable integration time is set in the microcomputer (14) in advance, and if the 'rlNT signal output to the ADT terminal has not been inverted after this time, the MD, = “H” 1MD, - “T-1” is output, DD
Shift to I mode and perform the operation of completing the integration in DDI mode. In the DDI mode, the integral time control section (20)
l'3. = “To ■”.

N [32-“L” signal to microcomputer (1
4), the BG multiplied signal “r” is immediately set. As a result, as in the previous case, the potential of the barrier gate (BG) shown in FIG.
The charge becomes higher, and the charge generated in the photodiode (PD) stops flowing into the storage section (ST), and the integration ends (FIG. 22).

Next, the operation to start reading out each pixel data of the image sensor (13) will be explained. Regardless of whether the brightness is low or high, the microcomputer (14
) outputs N B +-"[-(", Nip, -"L", the integral time control section (20) locks the transfer φ.

Synchronize and transfer lock φ. generates the S H signal pulse at the timing of "g" (Figure 6 or Figure 22)
. As a result, as shown in FIGS. 5(f) and (g), a pulse voltage is applied to the SII gate of the image sensor (13), and each pixel stored in each storage section (ST) Signal charges are transferred to the transfer register (rtG). After that, transfer lock φ1. The signal charge of each pixel is transferred and read out by φ. The signal charges accumulated in each storage section (ST) are transferred to the transfer register (r(G)) by the microcomputer (14) in DD! mode: NB, = "■■", NB, = "L" This is performed when the transfer register (RG) is output, but at this time, it is necessary that the transfer register (RG) returns from the unsteady state after the start of integration and becomes a steady state.

In a steady state, each transfer register (RG) has a dark charge of 23
It is accumulated as shown in the figure. This dark charge is the sum of the dark charge generated in the potential well of each transfer register (CnG) and the dark charge of the previous stage register that is sequentially transferred. At the start of integration, the integral clear gate (RG I
Apply a voltage to the gate terminal of the transfer register (CG) and transfer the voltage to the gate terminal of the transfer register (CG).
The integral clear gate (RGICG) between the transfer register (RG) and the overflow drain (ODI) is turned on, and all dark charges in the transfer register (RG) are cleared. After the integral clear gate (RGICG) is turned off, each time the transfer lock φ1 passes one period, the dark charge of the transfer register CRG (from the left side of FIG. 23) becomes a steady state. It takes a time equal to the number of pixels (N) x one transfer lock cycle (T) until all transfer registers (RG) return to a steady state.

When an SH pulse is generated in an unsteady state, the dark charge component of the transfer register (RG) in the charge taken out as an output may be in an unsteady state depending on the pixel, so that a correct signal cannot be taken out. For this reason, the SI (pulse is generated at least after the RGICG signal goes from "H" to L), and then the number of pixels x one transfer lock cycle (NXT
) must have passed.

At high brightness, the integration is often completed within one period (NxT), but since the integration is terminated by closing Pariage 1-(13G), it is delayed after one period (NxT), and S I-1 It is possible to make the pulse generation wait.

Next, regarding the processing of the read pixel output, FIG.
This will be explained below with reference to FIG.

The signal charge of each pixel of the image sensor (13) is φ1−
At the timing of "L", φ2-"I]", it is transferred to the capacitor (8-1) shown in FIG. In the signal processing timing generation section (21), prior to transferring this signal charge,
As shown in FIG. 12, φ1−“I−(”, φ, −
Emit O3I'tS signal pulse at "L" timing,
This pulse is applied to the gate of the PET (8-3) shown in FIG. 1 to charge and reset the capacitor (8-1) to approximately the power supply voltage. φ, −“L”.

When the signal charge is transferred at the time when φ, - "I4", the voltage of this capacitor (8-1) decreases due to the signal charge, and the output O8 of the image sensor (13) becomes the first
The output is as shown in Figure 2. The AGC differential amplifier circuit (25) uses the R9S/H signal sent from the signal processing timing generator (21) to set the voltage level at the time of reset to the FET (52), capacitor (53),
It is stored by a sample bold circuit consisting of a buffer (51) and input to the plus input of an operational amplifier (54). On the other hand, the O8 signal is input to the negative input of the operational amplifier (54) via the buffer (50), and the FET (
Gl input to the gate of 5'5.56, 57.58)
.

The output differentially amplified with the gain determined by the G2 signal (see FIG. 11) is output from the operational amplifier (54) as Vos' (see FIG. 12).

Next, the determination of the integral level will be explained.

If the integration is forcibly terminated when the brightness is low, the level of the pixel output of the image sensor (13) will naturally fall to the level at the appropriate time. Therefore, in this case, the level of integration is detected using the multiple luminance determination circuit (24), and a gain is applied to the output of the image sensor (13) according to the result to ensure that the output is always at an appropriate level. I'm trying to get it.

The following will explain the brightness determination analog circuit of FIG. 8, the pulse timing chart of FIG. 9, the brightness determination logic circuit of FIG. 1O, and the truth table of FIG. 24. Note that the brightness determination circuit (23) is constituted by this brightness determination analog circuit and the brightness determination logic circuit. As shown in FIG. 8, the operational amplifier (43) outputs an output V43-Vref- (DOS-AGCO3) according to the amount of light to be detected, and one comparator (45) which is a brightness determination means
is input to the negative input of When determining the integration time, φd is applied as shown in FIG. 9, and the FET (49) of the base voltage generation circuit (RVC) is turned on.
The positive input of the comparator (45) is (Vref-V
th) is input. Now, when the SH pulse occurs, latch 1 (73) and latch 2 (74) in Figure 1O are activated.
, latch 3 (75) are all reset. after that,
As shown in FIG. 9, when the φC pulse is generated, the FET (48) in FIG. 8 is turned on, and the comparator (45)
The positive human power is (Vref-Vth/2). Here, if DOS-AGCO8)>Vth
/2, the output VFLG of the comparator (45) is “i
-(", the output of the AND gate (70) shown in Figure 1O becomes "I-1", and the latch 1 (73)
is set. Then, as shown in FIG.
When the b pulse occurs, the FET (47) in Fig. 8 turns on, and the positive input of the comparator (45) receives (V r
er-V th/4) is input. Here, if DOS-AGCO9)>Vth/4, the output VFLG of the comparator (45) is “L”.
l'', and in Figure 1O, the AND gate (71)
The output becomes "I1" and latch 2 (74) is set. Furthermore, as shown in FIG. 9, when the φa pulse is generated, FE'r (46) in FIG. 8 is turned on, and the positive human power of the comparator (45) is
r −V th/ 8 ) is manually generated. Kokote, (D
If OS-AGCO9)>Vth/8, the output of the comparator (45) V F L G
becomes “[-1”, and the AND gate (7
2) becomes "Ize", and latch 3 (75) is set. In each of the above cases, Gl and G3 signals are generated according to the truth table of Fig. 24. Based on this signal, the gain is They are selected as shown in the following table, and Vos at a substantially appropriate level can be obtained for each.

In this way, by sequentially turning on the FETs (49, 48, 47, 46), the basic voltage generation circuit (RVC)
generates multiple reference voltages, one comparator (45) can judge the brightness at multiple stages, and the image sensor (
I3) The number of comparators formed on the same chip can be reduced.

The FET (44) shown in FIG. 8 is a switch for supplying power to the resistance divider circuit, that is, the bracket voltage generating circuit (RVC) only in the TNT mode and the DDI mode. This FET (li4) allows the base voltage generation circuit (RVC) to be energized only when brightness determination is necessary, reducing current consumption. This current consumption saving effect is
At high brightness, the integration time becomes shorter than the readout time, so it becomes larger.

As shown in FIG. 11, the signal Vos' is FE'r(60
), a capacitor (62), and a buffer (64).
It is input to the minus input of (65). This signal Vos
The bolding of ' is the signal processing timing generation section (21
) to φ1-“■,” and φ2-“+(”) by the OSS/I■ pulse signal generated at the timing of the signal charge transfer. Also, the signal Vos' is the PET (59)
, a capacitor (61), and a buffer (63). This sample bold circuit performs sample bolding of the output of the black pixel subjected to the AQ light shielding shown in FIG. The pulse that provides the sample and hold timing is OBS/
I-1 signal, which is generated in the sequence shown below.

1] from the INT mote, as shown in Figures 2 and 12.
) After shifting to the I mode, an ADS signal that provides timing for starting A/D conversion appears in the ADT signal. The microcomputer (14) measures the timing of sample and hold of the black-based pixel output while monitoring this signal. The microcomputer (14) outputs NB1-“H” and NB2-“H” while outputting the dark output pixel, and the signal processing timing generation unit (21) thereby outputs the OBS/H signal as “I-”. 1”. Subsequently, the microcomputer (14) outputs N13, -“L”, NB, -“I]” until the next ADS signal rises,
This allows the signal processing timing generation section (21) to
Set the S/H signal to "L". As a result, the FET (59), capacitor (61), and buffer (6) shown in FIG.
The sample bold circuit consisting of 3) holds the manually inputted black base pixel output and inputs it to the negative input of operational amplifier 2 (65). After sampling and holding the black reference pixel, the output of operational amplifier 2 (65) is subtracted by the amount corresponding to the held black reference pixel output, and
) ~(68) (7) G3. connected to the gate. The signal G4 is amplified by the signal defined by the signal G4 (distinction table 11) and output as the signal Vos (FIG. 12).

As shown below, the output signal O8 of the image sensor (13)
is A, GC differential amplifier circuit (25) and OB subtraction AGC
Double sampled in the differential amplifier circuit (26),
The reset level is subtracted from the signal level, a signal not affected by reset noise is extracted, and the black level is subtracted from the signal not affected by reset noise, and the dark output is calculated from the output of 6 pixels. removed output V
os is obtained. Furthermore, this output Vos is applied to the output O8 of the image sensor (I3) by the AGC differential amplifier circuit (25) and the OB subtraction AGC differential amplifier circuit (26).
It is created by applying a gain of x8 to x64 as shown below, depending on the average level of each pixel output.

Next, the gain of the operational amplifier (54) of the AGC differential amplifier circuit (25) and the gain of the operational amplifier (65) of the OB subtraction AGC differential amplifier circuit (26) shown in FIG. 1i will be described. Here, for the output O8 of the image sensor (I3), x8. x16. In order to switch the gain of
(65) performs two-stage gain switching. In this case, the operational amplifiers (54) and (65) always have an offset problem. When applying gain in two stages, the first stage gain is GNI, the second stage gain is GN2,
If the offset of each operational amplifier is ΔV, the input is vi1, and the output is Vo, the output is expressed by the following formula.

Vo-((Vi+△V)xGNl+△V)xGN2-V
i X GNI X GN2+△V −(GNI
GN2 + GN2)-(v1+△V) x GNI
xGN2+ΔVxGNIf the total gain GNIXGN2 of the 22-stage operational amplifier does not change, an offset due to GN2 appears in the second term (ΔVXGN2) of the above equation.

That is, the smaller GN2 is, the smaller the total offset will be.

Therefore, the first stage gain GNI is the second stage gain GN2.
The offset can be suppressed by choosing higher than , but even with this measure the offset remains. For this reason,
As shown in FIG. 11, the operational amplifier 2 (65) in the latter stage performs a level shift based on a voltage that has dropped in potential by a diode (99 months) from the reference voltage V ref, so that A/D conversion is possible at all times. The offset is the reference voltage Vre
It is made to come out on the lower voltage side than f.

After sampling and holding the signal representing the black reference pixel, the OB subtraction AGC differential amplifier circuit (26) outputs a signal representing the second black reference pixel subjected to Ae light shielding before outputting the signal representing the effective pixel. are doing. Since the previously bolded black reference pixel is subtracted from the output representing this second black reference pixel, the reference voltage V
You will get an output that matches rer. However, since the output of the operational amplifier 2 (65) always has an offset Vo (Tset) on the lower voltage side than the reference voltage V ref, the output becomes (Vref - Voffset).
Upon conversion, a signal corresponding to V of fset is obtained as digital data. Thereafter, the output of the effective pixel is subtracted by this VofTset by the calculation of the microcomputer (14).
14) is substantially the same as the data with the offset component removed.

Next, the DD2 mode will be explained.

In the DD2 mode, the image sensor (13) is not caused to perform any active operation.

Therefore, NB1 connected to I10 buffer (22)
．． Switch the human output of the NB2 signal, output the G1 signal to NB, the G3 signal to NB2, and output the G3 signal to the microcomputer (
14), the gain information of the output of the image sensor (13) is notified. This I10 switching is performed by the DD2 signal.

Only in the DD2 mode, the signal output as Vout is the output Vos of the image sensor (13).

The pixels used in this system are image sensors (I3)
are pixels detected in two separate regions of
No photodiode (PD) is provided between the two regions. When outputting the output of these pixels to the A/D converter (15) as Vout, there are problems that will be explained later, so by switching between DD2 mode and DD1 mode,
Vos is output as Vout only when valid pixels are output. The output Vos' of the AGC differential amplifier circuit (25) is the output component Vo corresponding to the optical signal when the effective pixel is output.
s' (sig) and the dark output component V os' (dark
) (V os' −V os'
(sig) + Vos' (dark)). OB
V os' (d
ark) is subtracted, and Vos=Vref-GN2 x(Vos'-Vos'(
dark)) to the A/D converter (15).

At this time, the output of the pixel from which the photodiode (PD) has been removed becomes Vos'-0 because there is no output corresponding to the optical signal and no dark output component. Here, when Vos' (dark) is subtracted by the OB subtraction AGC differential amplification (26), Vos = Vref - GN2 x (Q - Vos' (da
rk))>Vref, and Vos is lower than the reference voltage Vref, which is A/D convertible.
The voltage becomes higher than rer, which may exceed the dynamic range of A/D conversion and cause damage to the A/D conversion section (15). For this reason, except for outputs from effective pixels, the analog switches (28) and '(29) are switched to always output an A/D convertible temperature detection output VTMP. In this way, only when outputting effective pixels, DD2-“
By outputting Vos as "I]" and outputting VTMP as DD2-"L" when an invalid pixel is output, the A/D conversion is always within the dynamic range of A/D conversion.
I am trying to perform D conversion.

This concludes the explanation of the DD2 mode and the explanation of the first embodiment.

Next, a second embodiment will be described in which the means for removing the dark output component in the first embodiment is modified. here,
Only the differences from the first embodiment will be explained with reference to the block diagram in FIG. 14 and the circuit diagram of the AGC differential amplifier circuit in FIG. 15.

First, the block diagram of FIG. 14 showing the second embodiment and the block diagram of FIG.
As shown by the differences in the block diagram of FIG. 2 illustrating an embodiment of the analog reference voltage V re
It differs from the first embodiment in that the signal "l" is output from the AGC differential amplifier circuit (125). Also, in FIG. 14, the OB subtraction AGC differential amplifier circuit in the first embodiment is removed. has been done.

The operation of the second embodiment will be explained with reference to FIG. As in the first embodiment, the image sensor (13) outputs the output of the black pixels prior to outputting the effective pixels. Here, A
(, FET (159) in C differential amplifier circuit (125),
A sample and hold circuit consisting of a capacitor (+61) and a buffer (163) samples and holds the output of the black reference pixel using the OBS/H pulse. In the first embodiment, the bolded output is the opamp 2 (65
), and subtraction was performed using operational amplifier 2 (65), but in the second embodiment, the held output is output as V ref''.This V ref
r' is supplied to the A/D converter (115) as an analog reference voltage, and the A/D converter (+15) A/D converts the input voltage using this voltage as a reference.

That is, in order to take the difference between the input Vout and the reference voltage V rer' and convert it into a digital value, an A/D converter (
This is equivalent to subtracting the black reference pixel output within +15).

In addition, the output of the black reference pixel, which is sampled and held by the sample-and-hold circuit consisting of the FET (160), the capacitor (162), and the buffer (164), and the output of each effective pixel are the outputs of the operational amplifier 2 (165). Since these differentials are taken within the A/D converter (+15), the offset of operational amplifier 2 (165) is completely removed. Therefore, in the second embodiment, the dark output of the image sensor (13) is removed and the operational amplifier 2 (+6
5) Offset removal is performed.

Next, a third embodiment will be described with reference to FIGS. 16, 17, and 18. This third embodiment differs from the first and second embodiments in the dark output removal means.

First, let us look at the block diagram of the third embodiment (Fig. 16) and
Differences from the block diagram of the embodiment (FIG. 2) will be described below.

In the third embodiment, the sample and hold pulse 0I3S/H of the black reference pixel is manually input to the A/D converter (215), and the OE subtraction AGC differential amplifier circuit is removed.

In this third embodiment, the subtraction of the black reference pixel is performed within the A/D converter (2+5).

FIG. 18 shows the A/D converter (215), and this Δ/D
The conversion unit (2t 5> has an A/D conversion circuit (20G) and an internal circuit provided on the same chip. 18th
In the figure, the output of the image sensor, which is manually inputted as Vin, consists of the output of the black reference pixel and the subsequent effect pixel. The output of the black reference pixel is output from FET (20
1), capacitor (202) and buffer (203)
Sample and hold is performed by a sample bold circuit consisting of: After that, the effective pixel output manually input is subtracted by the sampled and held black reference pixel output by an operational amplifier (205), and then sent to an A/D conversion circuit (206).
is input to.

FIG. 17 shows an AGC differential amplifier circuit (225).

In the first embodiment, there was a sample bold circuit for the output of the black reference pixel, but in the third embodiment, this is removed. Further, as in the second embodiment, since the black reference pixel output and the effective pixel output are output from the same operational amplifier (165), the offset of this operational amplifier (+65) is completely canceled.

Next, a fourth example in which the dark time output removing means is different from the above-mentioned embodiment.
An example will be explained. FIG. 19 is a hardware block diagram according to the fourth embodiment. This is a block diagram of the third embodiment, which is different from FIG.
The difference is that the A/D converter (315) is not manually inputted, and the AGC differential amplifier circuit (225) is
The configuration is exactly the same as that of the embodiment.

FIG. 20 shows the A/D converter (315), and this A/D converter (315) is shown in FIG.
The D conversion section (315) includes an A/D conversion circuit (405) and an internal circuit provided on the same chip. While the image sensor (13) is outputting the black reference pixel, an OBS/H pulse is given to the A/D converter (315), and the black 71 i"4 input to the terminal Vin.
Pixel output is FET (401), capacitor (402)
, and a buffer (403). The bolded black reference pixel output is input to the A/D conversion circuit (405) as an analog reference voltage (V rer' ). after that,
As in the second embodiment, the effective pixel output of the image sensor (13) input to the terminal Vin is subtracted by the held black reference pixel output (Vrcf''), and then the A/D
converted. This removes the dark output component.

<Effects of the Invention> As is clear from the above, the solid-state imaging device of the present invention has the following effects:
A photoelectric conversion section, an accumulation section for accumulating charges generated in the photoelectric conversion section, a brightness monitoring means for monitoring the amount of light irradiated onto the photoelectric conversion section, and an accumulation means for accumulating the charges generated in the brightness monitoring means. , an output means for outputting a signal corresponding to the amount of charge accumulated in the accumulation means, a reference voltage generation circuit for generating multiple levels of reference 7Ii pressure, and an output from the reference voltage generation circuit and the output means. Since a single comparator is created on the same chip to compare the output of This allows a single comparator to determine brightness in multiple levels, and the area occupied by the comparator on the chip can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the image sensor in the solid-state imaging device of the present invention, FIG. 2 is a block diagram of the fixed imaging device of the first embodiment of the invention, and FIG. 3 shows the potential structure of the image sensor at the time of initialization. 4 is a time chart of the signal in the initialization mode of the first embodiment, FIG. 5 is a diagram showing the potential structure of the image sensor in the integral mode, and FIG. 6 is a time chart of the signal in the integral mode. Fig. 7 is a structural diagram of a compensation diode, Fig. 8 is a circuit diagram of a luminance judgment analog circuit, Fig. 9 is a time chart of signals during luminance judgment,
Fig. 1O is a circuit diagram of the brightness determination logic circuit, Fig. 11 is a circuit diagram of the AGC differential amplifier circuit and the OB subtraction AGC differential amplifier circuit in the first embodiment, and Fig. 12 is a circuit diagram of the 4-type circuit related to pixel output processing. l, chart, Figure 1:3 is a circuit diagram of the temperature detection section, Figure 14 is a block diagram of the solid-state imaging device of the second embodiment, Figure 15 is a circuit diagram of the AGC operated amplifier circuit of the second embodiment, FIG. 16 is a block diagram of the solid-state imaging device of the third embodiment, FIG. 17 is a circuit diagram of the A, G C operational amplifier circuit of the third embodiment, and FIG. 18 is a circuit diagram of the A/D conversion section. 1
FIG. 9 is a block diagram of the solid-state imaging device of the fourth embodiment, and FIG.
The figure shows the circuit diagram of the A/'I) conversion section of the fourth embodiment, and the circuit diagram of the second embodiment.
Figure 1 is a structural diagram of the image sensor, Figure 22 is a time chart of the toll signal in the integration mode of the fourth embodiment, and Figure 23 is a diagram of the structure of the image sensor.
This figure is a diagram for explaining the transfer of dark charges, and FIG. 24 is a diagram showing a truth table of a brightness determination logic circuit. PD...photodiode, BG...barrier gate,
ST...Storage unit, SH...Shift gate, R, G.
...Transfer register, RG I CG... Integral clear gate, 14... Microcomputer, 20 - Integration time control section, 23... Mode selection circuit, 24... Brightness determination circuit, 30... Transfer The part where the lock occurs. Patent Applicant: Minolta Camera Co., Ltd. Agent: Patent Attorney: Mr. Yu and 2 others Page 3 (a) (G) Peripheral Table Lb 7 Figure Circumference La LaM7.7Lb

Claims (1)

[Claims] (1) A photoelectric conversion section that generates charges corresponding to the light incident on each pixel; an accumulation section that accumulates the charges generated in the photoelectric conversion section; and a storage section that generates charges according to the amount of incident light and A brightness monitor means for monitoring the amount of light irradiated to the conversion section; an accumulation means for accumulating the charge generated in the brightness monitor means; and an output means for outputting a signal according to the amount of charge accumulated in the accumulation means. , a reference voltage generation circuit that generates reference voltages in multiple stages; and a comparator that compares the multiple reference outputs from the reference voltage generation circuit and the output from the output means to determine the brightness in multiple stages. A solid-state imaging device that is created on the same chip.