JPH01204581A - Picture data storage device - Google Patents

Abstract

PURPOSE:To use an address of a memory means with split through simple circuit constitution by switching the least address data of a written address data of a picture data into a picture selection data and giving the result to the memory means. CONSTITUTION:When a picture selection data supplied from an address switching circuit 53 via a picture selection data input terminal 66 is controlled to be supplied to a memory 9 by the control data supplied from a system controller by the operation of the 3rd operation switch 33, the data at the least address data output terminal CO of an H counter 51 in the address data formed by counters 51, 52 is switched into a picture selection data and fed to the memory 9. Thus, the address of the memory 9 storing the picture data digitizing the input video signal is used with split.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B1 Overview of the invention C9 Prior art 1 Problems to be solved by the invention 1 Means for solving the problems F1 Effect G. Example (Gl-1) Camera to which the present invention is applied Structure of integrated VTR (Figures 1 to 3) (Gl-2) Operation of titler circuit (Figure 1) (G2)
Application Example 81 Effects of the Invention A, Industrial Application Field The present invention relates to an image data storage device that stores image data using memory means.

B9 Summary of the Invention The present invention provides an image data storage device that stores image data formed by digitizing an input video signal in a memory means, in which the lowest address data of write address data of the image data is switched to image selection data. By providing the address to the memory means, the address of the memory means can be divided and used with a simple circuit configuration.

C6 Prior Art-i An image data storage device is known in which image data formed by digitizing an input video signal is stored in a memory means.

In this image data storage device, by switching the write address data supplied to the memory means,
The following image data storage devices have been conventionally used to divide and use the addresses of the memory means.

That is, this image data storage device, as shown in FIG. A memory 83 to which image data is supplied and an address input 1 (
A(1-An) is provided with an address counter 84 that supplies write address data of the image data, an image selection terminal 85 to which image selection data is supplied, and the highest data output terminal (Cn) of the address counter 84. is selectively connected to the most significant address input terminal (80) of the memory 83 by an address switching circuit 86. Further, the clock input Fi+(ct) of the address counter 84 is clocked.

K) and the sampling clock of the A/D conversion circuit 82 9.
The input terminal (SCK) is a clock input terminal 87 to which a clock pulse of a predetermined frequency fs is supplied, and a frequency divider circuit 87 which outputs a clock pulse of a frequency '74 fs obtained by dividing the frequency fs of this clock pulse by two. are selectively connected by a sampling switching circuit 89.

In the image data storage device having such a configuration, the sampling switching circuit 89 selects the clock input terminal 87 side, so that the clock input terminal (CLK) of the address counter 84 and the sampling clock of the A/D conversion circuit 82 are switched. A clock pulse of the frequency fs is supplied to the input terminal (SCK). At this time, the address switching circuit 86 connects the most significant address input terminal (An) of the memory 83 and the most significant data output terminal (Cn) of the address counter 84. Further, the A/D conversion circuit 82 has the signal input terminal 81
The video signal supplied through the memory 83 is digitized at the frequency fs of the clock pulse and is supplied as image data to the image data input terminal (Din) of the memory 83. The address counter 84 generates address data at the timing of the clock pulse of the frequency fs and supplies it to the address input terminals (AO to An) of the memory 83.

Therefore, the image data is written to the address of the memory 83 specified by the address data.

Further, the sampling switching circuit 89 is connected to the frequency dividing circuit 8.
By selecting the 8 side, the above address counter 8
4 clock input terminal (CLK) and the above A/D conversion circuit 8
A clock pulse with a frequency of %fs is supplied to the sampling clock input terminal (SCK) of No.2. At this time,
The address switching circuit 86 connects the most significant address input terminal (An) of the memory 83 and the image selection terminal 85. Further, the A/D conversion circuit 82 digitizes the video signal supplied via the signal input terminal 81 at a frequency of 3 fs of the clock pulse, and inputs the digital signal to the image data input terminal (Din) of the memory 83 as image data. supply This image data is two times the image data generated by the clock pulse of the frequency fs.
is the amount of data. Further, the address counter 84 generates address data at the timing of the clock pulse of the frequency +Afs. This address data is supplied to the address input terminals (AO to An) of the memory 83 after the most significant address data is switched to image selection data supplied to the image selection terminal 85. Therefore, the image data r is sent to the image selection end 85.
When lJ is supplied, the highest address is rl
", and when the image selection data r□J is supplied to the image selection terminal 85, the highest address is written to the lower address of the memory 83 indicated by fQJ. .

In this way, this image data storage device switches the highest address data to image selection data.
The address of the memory 83 can be divided into two and used.

In this image data storage device, the image data can be outputted from the data output terminal (Dout) by giving the same read address data as the write address data to the memory 83. This image data is transferred to a digital-to-analog (D/A) conversion circuit 90.
The signal is converted into an analog signal and output from a signal output terminal 91.

D6 Problems to be Solved by the Invention Incidentally, in the above-described image data storage device, when storing image data by dividing the address of the memory 83 into two, the sampling clock input terminal (SCK) of the A/D conversion circuit 82 is ) and a clock input terminal (CLK) of the address counter 84 with a clock pulse obtained by dividing the frequency fs by two, a frequency dividing circuit 8 and a sampling switching circuit 89 are provided.

However, the image data storage device has the frequency divider circuit 88
The circuit scale becomes large due to the presence of the sampling switching circuit 1589 and the sampling switching circuit 1589, and since these circuits cause a delay in the clock pulse, the timing at which the address data is generated by the address counter 84 is also delayed.
When a video system including this image data storage device is configured, there are problems such as difficulty in synchronizing with other signals.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention provides a novel configuration that has a simple circuit configuration, prevents the clock supplied to the address counter from being delayed, and can divide and use addresses of memory means. The purpose of the present invention is to provide an image data storage device.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides means for digitizing an input video signal at a sampling frequency fs to form image data, and a memory for storing the image data. means, address generating means for counting clocks of the sampling frequency fs to generate address data for writing the image data to the memory means, and least significant side address data of the address data generated by the address generating means. and address switching means for switching to image selection data and applying it to the memory means.

F1 action In the image data storage device according to the present invention, the memory means for storing image data obtained by digitizing an input video signal is improved by replacing the lowest address data of the address data generated by the address generation means with image data. Address is split. The above address generation means is
Address data is generated by counting clocks of sampling frequency fs used to digitize the input video signal.

G. Embodiment (GLI) Configuration of a camera-integrated VTR to which the present invention is applied (Figs. 1 to 3) The embodiment described below with reference to the drawings is a camera-integrated 8 IrnV equipped with a titler function. In TR, the present invention is applied to a storage device for image data serving as a title image signal.

As shown in FIGS. 2 and 3, the camera-integrated 8m VTR includes an imaging section 10 that photographs a subject image, and a recording section that records the video signal obtained by the imaging section 10 in a predetermined format of 8+n+n video. 20 is the device body 3
0. In addition, as shown in the external perspective view of Fig. 3, this camera-integrated 8mm VTR has the following features:
An imaging lens 35 that guides the image light to the solid-state imager 1 of the imaging section 10 is provided, and the imaging section 10
1. An electronic viewfinder 40 for monitoring the most visible subject image, etc., and various operation switches 31 and 32.
．． 33 and the like are provided on the device main body 30.

As shown in the block diagram of FIG. A CCD that operates based on a synchronization signal that
It is driven by a drive circuit 3 and supplies an imaging output of a subject image obtained in the solid-state image 1 to an imaging processing signal circuit 4.

The imaging signal processing circuit 4 forms an imaging signal representing a subject image from the imaging output from the solid-state imager 1, and supplies the signal to the NTSC encoder 6 via the impose circuit 5.

The NTSC encoder 6 forms an NTSC video signal from the image pickup signal representing the subject image and supplies it to the electronic viewfinder 40 and the recording section 20 that performs a recording operation in a predetermined format of 8 mm video. At the same time, it is supplied to an analog-to-digital (A/D) conversion circuit 7.

The A/D conversion circuit 7 is supplied with a sampling clock of a predetermined frequency rs from a clock generation circuit (not shown), and uses this sampling clock to convert the luminance signal (Y) of the video signal into a digit to generate image data of a predetermined bit. form.

This image data is sent to the memory 9 via the titler circuit 8.
It is now written to .

The memory 9 is composed of a static RAM that can store all the image data for one image formed by the A/D conversion circuit 7, and can be stored even if the main power is cut off. A backup 'IJX' is supplied from a lithium battery 11 so that the stored data will not be lost.

As shown in FIG. 1, the titler circuit 8 is comprised of a data switching circuit 50, an H counter 51, a v counter 52, an address switching circuit 53, and the like.

Of these, the data switching circuit 50 is formed of a parallel data switching circuit, and the memory 9
are connected via the image data input/output terminal group 71, the A/D conversion circuit 7 is connected via the image data input terminal group 61, and the digital/analog (D/A) conversion circuit 12 are connected via an image data output terminal group 62.

The H counter 51 is formed of a counter with a predetermined focus for forming horizontal address data, and its clock input terminal is connected to the clock input terminal 63, and its reset input terminal is connected to the horizontal synchronization input terminal. 64, and furthermore, the lowest address data output terminal (CO)
is connected to the address switching circuit 53, and the other address data output terminal groups (C1 to Cn) are connected to the upper output terminal group (A) of the horizontal address data output terminal group 72.
hl to Ahn) to the memory 9. Here, the clock input terminal 63 is supplied with a clock pulse having the same frequency fs as the sampling clock supplied to the A/D conversion circuit 7 from a clock generation circuit (not shown).

Further, the V counter 52 is formed of a predetermined focus counter for forming vertical address data,
Its clock input terminal is connected to the horizontal synchronization input terminal 64, its reset input terminal is connected to the vertical synchronization input terminal 65, and the address data output terminal group (GO-C
n) is connected to the memory 9 via a group of vertical address data output terminals 73. Note that synchronization signals are supplied from the synchronization signal generation circuit 2 to the horizontal synchronization input terminal 64 and the vertical synchronization input terminal 65, respectively.

The address switching circuit 53 connects the lowest address data output terminal (CO) of the H counter 51 to the lowest output terminal (Aha) of the horizontal address data output terminal group 72.
) and the image selection data input terminal 66 are selectively connected, and the switching control data is supplied together from the control data input terminal 67.

Further, the titler circuit 8 is connected to a registration operation designation input terminal 68 to which the first operation switch 31 provided on the device main body 30 is connected, and the second operation switch 32. A designation input terminal 69 for insertion operation is provided, and the third operation switch 33
Data is supplied from a system controller (not shown) connected to the image selection data input terminal 66 and the control data input terminal 67, respectively. Further, in this titler circuit 8, a control data output terminal group 74 for supplying image data writing/reading instruction data, etc. is connected to the memory 9, and also supplies an operation control signal to the above-mentioned impose circuit 5. A control signal output terminal 70, a drive power input terminal 75, a ground terminal 76, and the like are provided.

The D/A conversion circuit 12 converts the predetermined bits of image data supplied from the titler circuit 8 into analog form to form a title image signal, and supplies the title image signal to the impose circuit 5.

Further, the above-mentioned impose circuit 5 is connected to the above-mentioned titler circuit 8.
The title image signal is inserted into the output signal of the imaging signal processing circuit 4 under the operation control of the image pickup signal processing circuit 4.

(Gl-2) Operation of the Kuytler circuit (Fig. 1) The titler circuit 8 is operated by each of the operation switches 31, 32, and 33.
The operation is as follows.

First, the first operation switch is an operation designation switch for the registration operation, and when the first operation switch 31 is operated while photographing arbitrary characters, illustrations, etc. drawn on the panel 100 with the imaging section 10, The titler circuit 8 supplies the write instruction data to the memory 9, and also causes the data switching circuit 50 to output the write instruction data to the A/D.
The conversion circuit 7 and the memory 9 are connected, and the image data formed by the A/D conversion circuit 7 is written into the memory 9.

At this time, the H counter 51 receives the clock pulses supplied through the clock input terminal 63 while being reset every horizontal scanning period by the horizontal synchronization signal supplied through the horizontal synchronization input terminal 64. By counting, horizontal address data is formed. Further, the v counter 52 is reset every l vertical scanning period by the vertical synchronization signal supplied via the vertical synchronization input terminal 65, and receives the horizontal synchronization signal supplied via the horizontal synchronization input terminal 64. By counting, vertical address data is formed.

Here, the address data formed by each of the counters 51 and 52 is transferred to the address switching circuit 53 by control 1 data supplied from the system controller (not shown) by operating the third operation switch 33. is the lowest address data output terminal (C
When the data of O) is controlled to be supplied to the memory 9, the data is supplied to the memory 9 as is.

Therefore, all of the image data for one sheet outputted from the A/D conversion circuit 7 is written to the address of the memory 9 designated by the address data.

Further, the address data formed by each of the counters 51 and 52 is transferred to the image selection data input terminal of the address switching circuit 53 by control data supplied from a system controller (not shown) by operating the third operation switch 33. When the image selection data supplied via 6G is controlled to be supplied to the memory 9, the data at the lowest address data output terminal (CO) of the II counter 51 is switched to the image selection data. The data is supplied to the memory 9 mentioned above. Data rOj or data 1rlJ is applied to the image selection data input terminal 66 as image selection data by a system controller (not shown) by operating the third operation switch 33. Therefore, when data WOJ is given as the image selection data to the memory 9, -000, . . . 000. -010. -0
1o, -・100. -400°..., the horizontal address data whose lowest data is I'QJ, and the horizontal address data whose lowest data is flJ are supplied so that two consecutive pieces of the same data are supplied, Furthermore, when data fIJ is given as the image selection data,
-001, -001, -011, -011, -411
, -411, ..., the lowest data is "IJ
The horizontal address data of is supplied so that two consecutive pieces of the same data are provided, with the lowest data skipping the horizontal address data of fi. Therefore, the image data outputted from the A/D conversion circuit 7 is written twice in duplicate to each address of the memory 9 specified by the horizontal address data, and only the image data written later is written to the address of the memory 9 specified by the horizontal address data. It is stored in memory 9.

In this way, the image data is thinned out to 2 and stored in the memory 9, and the image selection data selects the lowest data of the horizontal address data as fQ4 or rIJ.
By doing so, the image data thinned out in the above 2 can be stored one by one. That is, the image selection data r is stored in the memory 9 at the first registration operation.
At the time of Oj, the image data for the title image is supplied to the memory 9, and in the next registration operation, the image selection data "1" is
j, the image data of title image B is stored in the memory 9.
As shown in Table 1, the image data for the title image and the image data for the title image B are alternately written in correspondence with the horizontal addresses.

Table 1 Note that it goes without saying that the image data of the title image written to the memory 9 may be formed by capturing an image of a landscape, a person's face, etc., in addition to the characters and illustrations drawn on the panel. .

Next, the second operation switch 32 is an operation designation switch for the insertion operation, and this titler circuit 8 is connected to the second operation switch 32.
When the operation of the operation switch 32 is accepted, the read control data is supplied to the memory 9, the same read address data as the write address data is given to the memory 9, and the data switching circuit 50 supplies the read control data to the memory 9. and the D/A conversion circuit 12 are connected, image data is read from the memory 9, and the D/A conversion circuit 12 is connected.
It is supplied to the conversion circuit 12. The image data read from the memory 9 is converted into an analog signal by the D/A conversion circuit 12, and inserted into the output signal of the imaging signal processing circuit 4 by the impose circuit 5 as a title image signal.

As described above, in the above embodiment, when the address of the memory 9 is divided into two and used, a clock pulse obtained by dividing the frequency fs by two is sent to the address counter of the A/D conversion circuit as in the conventional example. 51, there is no need for a frequency dividing circuit or a sampling switching circuit. Therefore, in the above embodiment, the circuit scale can be reduced compared to that using a conventional image data storage device, and the clock pulses supplied to the H counter 51 can be supplied to the frequency dividing circuit or the sampling circuit. Since there is no delay due to the switching circuit, there is no delay in the generation timing of the address data, and this camera integrated 8 mm V
Synchronization with other signals used for TR can be easily achieved.

(G2) Application example If the titler circuit 8 is configured to switch the N-bit lowest address data to image selection data and provide it to the memory 9, it is possible to write two image data to the memory 9. is possible. Further, the image data written to and read from the memory 9 may be serial data obtained by binarizing the luminance signal (Y). Further, the titler circuit 8 is connected to the second
By operating the operation switch 32, image data for two images may be read out, and the image data may be subjected to data processing to output image data that becomes a variety of title images.

Note that the present invention is not limited to the above-described embodiments, but can be applied to various devices that use memory means to store image data formed by digitizing a video signal.

H0 Effects of the Invention In the present invention, by replacing the lowest address data of the address data generated by the address generation means with image data, the address of the memory means for storing the image data obtained by digitizing the input video signal is divided. Ru. The address generating means generates address data by counting clocks having a sampling frequency fs used to digitize the input video signal.

Therefore, the image data storage device according to the present invention can divide and use the address of the memory means by switching the image selection data, and moreover, unlike the conventional image data storage device, it does not require a frequency division circuit or a sampling switching circuit. Since these circuits are not required, the circuit size is small, and since the clock supplied to the address counter is not delayed by these circuits, the timing of address data generation is not delayed and can be easily synchronized with other signals. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a titler circuit of a camera-integrated VTR to which the present invention is applied, FIG. 2 is a block diagram showing the configuration of the camera-integrated VTR, and FIG. FIG. 4 is a perspective view of the external appearance of a body type VTR, and FIG. 4 is a block diagram showing the configuration of a conventional image data storage device. 7...A/D conversion circuit 8...Quitler circuit 9...Memory 51...H counter 53...Address switching circuit

Claims (1)

[Scope of Claims] Means for digitizing an input video signal at a sampling frequency fs to form image data; memory means for storing the image data; and means for counting clocks at the sampling frequency fs to store the image data in the memory means. It consists of an address generation means for generating write address data for the image data, and an address switching means for switching the lowest address data of the address data generated by the address generation means into image selection data and supplying it to the memory means. Image data storage device.