JPH01196179A - Field-effect transistor - Google Patents
Field-effect transistorInfo
- Publication number
- JPH01196179A JPH01196179A JP2231688A JP2231688A JPH01196179A JP H01196179 A JPH01196179 A JP H01196179A JP 2231688 A JP2231688 A JP 2231688A JP 2231688 A JP2231688 A JP 2231688A JP H01196179 A JPH01196179 A JP H01196179A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- gate
- electrode
- source
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 claims abstract description 5
- 150000002739 metals Chemical class 0.000 claims abstract 2
- 238000000034 method Methods 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 239000007769 metal material Substances 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、短ゲート長でもリーク電流の小さな電界効果
トランジスタに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor with a small leakage current even with a short gate length.
［従来技術と問題点コ
従来の電界効果トランジスタ（以下ＦＥＴという）は第
２図に模式的に示すような構造ををしている。[Prior Art and Problems] A conventional field effect transistor (hereinafter referred to as FET) has a structure as schematically shown in FIG.
図示のように、高抵抗基板６上番こイオン注入法や、エ
ピタキシャル法により電流チャンネルをなす活性層５が
形成される。この活性層５の両端にソース電極１、ドレ
イン電極４が形成され、それらの中間にゲート電極１２
が形成される。As shown in the figure, an active layer 5 forming a current channel is formed on a high-resistance substrate 6 by ion implantation or epitaxial method. A source electrode 1 and a drain electrode 4 are formed at both ends of this active layer 5, and a gate electrode 12 is formed between them.
is formed.
この種のトランジスタでは、ドレイン電流を制御するた
めのゲート下の空乏層（断面で示す）７が、ソース、ト
レイン間に電圧を印加した時には、ドレイン側に偏り、
ドレイン電流をピンチオフする際に、空乏層７は活性層
５と高抵抗基板６との界面に一点（正確には紙面に垂直
な線）で接触するのみて、リーク電流が大きくなってし
まう。これは特に短いゲート長をもつＦＥＴでは、その
特性を大幅に劣化させるということになる。In this type of transistor, when a voltage is applied between the source and the train, the depletion layer 7 under the gate (shown in cross section) for controlling the drain current shifts toward the drain side.
When pinching off the drain current, the depletion layer 7 contacts the interface between the active layer 5 and the high-resistance substrate 6 at only one point (more precisely, a line perpendicular to the plane of the paper), resulting in an increase in leakage current. This results in a significant deterioration of the characteristics of FETs, especially those with short gate lengths.
［発明の構成］
本発明は、上記短いゲート長をもＦＥＴにおいて、ピン
チオフ時に生じるリーク電流を抑制する目的でなされた
ものであって、ソースからドレインに向かって少なくと
も２種類の金属を用いてゲート電極を作製し、ドレイン
電流を制御するように構成したものである。[Structure of the Invention] The present invention has been made for the purpose of suppressing the leakage current that occurs at the time of pinch-off in an FET with the above-mentioned short gate length. An electrode was fabricated and configured to control drain current.
以下第１図に模式図で示す実施例により本発明を説明す
る。The present invention will be explained below with reference to an embodiment shown schematically in FIG.
第２図と同一部分は同一符号で示す。The same parts as in FIG. 2 are indicated by the same reference numerals.
高抵抗基板６の上に電流チャンネルを形成する活性層５
がイオン注入法や、エピタキシャル法により形成され、
活性層５の両端にソース電極１とドレイン電極４が形成
される。これらの中間において、電極１側の第１のゲー
ト金属材料はドレイン電極４側の第２ゲート金属材料に
比べ、半導体材料に対するショットキー障壁高さが高く
なるように選定される。Active layer 5 forming current channels on high resistance substrate 6
is formed by ion implantation method or epitaxial method,
A source electrode 1 and a drain electrode 4 are formed at both ends of the active layer 5 . In between these, the first gate metal material on the electrode 1 side is selected so that the Schottky barrier height with respect to the semiconductor material is higher than that of the second gate metal material on the drain electrode 4 side.
ＦＥＴではゲート電極直下の空乏層厚を変化させること
で、ドレイン電流を制御する。In an FET, the drain current is controlled by changing the thickness of the depletion layer directly under the gate electrode.
空乏層厚Ｗは、
で表現できる。ここで、φＢ ニジヨツトキー障壁高さ
、■ｇ！：実効ゲート電圧、Ｃ：定数電界効果トランジ
スタの動作時には、ソースとドレインに電位差が印加さ
れる。この時、実効ゲート電圧■２は、ソースドレイン
の方向の位置によって変化する。このため前述したよう
な空乏層断面の偏りが生じる。The depletion layer thickness W can be expressed as follows. Here, φB Nijiyotsutoki barrier height, ■g! : Effective gate voltage, C: Constant When a field effect transistor operates, a potential difference is applied between the source and the drain. At this time, the effective gate voltage (2) changes depending on the position in the source-drain direction. This causes the depletion layer cross section to be biased as described above.
このとき、■１の変化を補償するようにショットキー障
壁高さφ８を変化させることで、偏った空乏層断面を修
正し、ドレイン電流をピンチオフする時のリーク電流を
極力少なくすることが可能となる。At this time, by changing the Schottky barrier height φ8 to compensate for the change in ■1, it is possible to correct the biased depletion layer cross section and minimize the leakage current when pinching off the drain current. Become.
［実施例］
半絶縁性ＧａＡｓ基板上にＳｉを加速電圧１２０ｋｖ
。[Example] Accelerating Si on a semi-insulating GaAs substrate at a voltage of 120 kv
.
ドーズ量３ Ｘ １０１１０１２ａでイオン注入した後
で、活性化アニールを８５０℃／２０ ｍｉｎ （Ａ
Ｓ雰囲気中）で行い、表面にＡｕＧｅＮｉ合金によるソ
ース、ドレイン電極を設けた。After ion implantation with a dose of 3 x 1011012a, activation annealing was performed at 850°C/20 min (A
Source and drain electrodes made of an AuGeNi alloy were provided on the surface.
これに、ソース電極１側の第１ゲート金属としてＡ Ｌ
Ｉ Ｎ第２ゲート金属ＡＩを用いてゲート電極を作製し
た。ゲート長はＡｕ及びＡ１部分の和として、１μｍ１
ゲ一ト幅は２００μｍである。ソースとドレイン間電圧
を２，５■とした時のゲート電圧に対するドレイン電流
の相関を第３図に示す。図中、白丸で示した相関が本発
明のＦＥＴの特性であり、黒丸で示したものが従来のＡ
！のみを用いたゲート電極をもっＦＥＴの相関特性を示
す。In addition, A L is added as the first gate metal on the source electrode 1 side.
A gate electrode was fabricated using IN second gate metal AI. The gate length is 1 μm as the sum of Au and A1 parts.
The gate width is 200 μm. FIG. 3 shows the correlation between the drain current and the gate voltage when the source-drain voltage is 2.5 .mu.m. In the figure, the correlation shown by the white circle is the characteristic of the FET of the present invention, and the correlation shown by the black circle is the characteristic of the conventional A
! This shows the correlation characteristics of an FET with a gate electrode using only a gate electrode.
本発明に基（相関の方がゲート電圧によるドレイン電流
のピンチオフがクリアに行われることが確認できる。Based on the present invention, it can be confirmed that pinch-off of the drain current due to the gate voltage is performed more clearly in the correlation method.
［発明の効果コ
以上説明したように通常のＦＥＴに比べて、そのピンチ
オフ特性が向上するので、■族、 ｍ−ｖ族、Ｉｔ−Ｖ
Ｉ族などの半導体を用いた高速デバイス、ＩＣ，光ＩＣ
の系に利用することができる。[Effects of the invention] As explained above, the pinch-off characteristics are improved compared to ordinary FETs, so
High-speed devices, ICs, optical ICs using semiconductors such as Group I semiconductors
It can be used for the system.
第１図は本発明の一実施例を模式的に断面構造で示す。
第２図は、従来のＦＥＴを模式的に図面で示す。
第３図はゲート電圧に対するドレイン電流の相関を本発
明によるものと従来のものと対比して示す。
１・・・ソース電極、２・・・第１の金属によるゲート
電極、３・・・第２の金属によるゲート電極、４・・・
ドレイン電極、５・・・活性層、６・・・高抵抗基板、
７・・・空乏層断面、８・・・ソース−ドレイン電源、
９・・・ゲート電圧源、ｌＯ・・・ソース−ドレイン電
流計、１１・・・配線、又は配線パッド。
賽１ 図
Ｒ
堪虻 ０ 缶ハ
′１！１．３ 目
Ｏｌ；５
￥
く ８吠
７Ｌ にソ
ゲート電圧（Ｖ）FIG. 1 schematically shows a cross-sectional structure of an embodiment of the present invention. FIG. 2 schematically shows a conventional FET. FIG. 3 shows the relationship between the drain current and the gate voltage in comparison with the present invention and the conventional one. DESCRIPTION OF SYMBOLS 1... Source electrode, 2... Gate electrode made of a first metal, 3... Gate electrode made of a second metal, 4...
Drain electrode, 5... active layer, 6... high resistance substrate,
7... Depletion layer cross section, 8... Source-drain power supply,
9... Gate voltage source, lO... Source-drain ammeter, 11... Wiring or wiring pad. Dice 1 Figure R Enjoy 0 Can Ha'1!1.3 Eye Ol;5 ￥ Ku 8-7L Sogate voltage (V)
Claims (1)
高さの異なる金属を用いたゲート電極を設け、ソース−
ドレイン電流をしゃ断する空乏層の分布を制御すること
を特徴とする電界効果トランジスタ。(1) Provide a gate electrode using metals with different Schottky barrier heights in the direction of the source-drain current, and
A field effect transistor characterized by controlling the distribution of a depletion layer that blocks drain current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2231688A JPH01196179A (en) | 1988-02-01 | 1988-02-01 | Field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2231688A JPH01196179A (en) | 1988-02-01 | 1988-02-01 | Field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01196179A true JPH01196179A (en) | 1989-08-07 |
Family
ID=12079326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2231688A Pending JPH01196179A (en) | 1988-02-01 | 1988-02-01 | Field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01196179A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2700890A1 (en) * | 1993-01-27 | 1994-07-29 | Fujitsu Ltd | A field effect composite transistor device having a Schottky electrode. |
| DE19523333A1 (en) * | 1994-12-09 | 1996-06-13 | Mitsubishi Electric Corp | Bipolar semiconductor device |
| CN107785437A (en) * | 2017-10-31 | 2018-03-09 | 沈阳工业大学 | A kind of bracket shape grid-control source and drain resistive formula two-way switch transistor and its manufacture method |
-
1988
- 1988-02-01 JP JP2231688A patent/JPH01196179A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2700890A1 (en) * | 1993-01-27 | 1994-07-29 | Fujitsu Ltd | A field effect composite transistor device having a Schottky electrode. |
| DE19523333A1 (en) * | 1994-12-09 | 1996-06-13 | Mitsubishi Electric Corp | Bipolar semiconductor device |
| CN107785437A (en) * | 2017-10-31 | 2018-03-09 | 沈阳工业大学 | A kind of bracket shape grid-control source and drain resistive formula two-way switch transistor and its manufacture method |
| CN107785437B (en) * | 2017-10-31 | 2020-05-29 | 沈阳工业大学 | Bracket-shaped grid-control source-drain resistance-variable bidirectional switch transistor and manufacturing method thereof |
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