JPH01194354A - Semiconductor light detector - Google Patents

Abstract

PURPOSE:To make it possible to read out a signal charge rapidly and stably without unread charge even in the case of a sudden change of the amount of incidence of light exposure, by making an optical signal reader by the use of a junctiongate-type FET. CONSTITUTION:When an address signal S is applied to an n-type semiconductor layer 23, a gate of a junction gate-type FET 26, at the level of H, a p-n junction made of the layer 23 and p-type semiconductor layers 21, 22 and 24 is biased in the reverse direction and a depletion layer spreads out in the layer 24. Therefore, a signal charge photoelectrically converted by a photo diode 25 is temporarily stored in a photo diode junction capacitance 27. When the signal S sent via a signal line 9 is applied to the gate (layer 23) of the FET 26 under this condition, a signal charge channel is formed since the reverse bias applied to the p-n junction is reduced and the depletion layer spread out in the layer 24 gets smaller. Because of this, the signal charge which has been stored in the capacitance 27 is sent forth into the layer 21 and starts flowing into a load resistance 12. Therefore, a rapid read-out of an optical signal is available.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor photodetection device that functions as a photoelectric conversion section and an optical signal readout section of a solid-state imaging device used in a position detection device, an optical character reading device, etc. It is related to.

[Conventional technology]

Figure 3 shows a plasma coupled semiconductor device (PCD: Plasma
sma Coupled Device) as a shift register for scanning.
(A) is a plan view, (B) is a sectional view taken along line bb, and (C) is an equivalent circuit diagram.

A highly concentrated n-type semiconductor layer 2.5 and a p-type semiconductor layer 3.4 are formed on the surface of the n-type silicon substrate 1.
The type semiconductor layer 3.4 is formed deeper than the n-type semiconductor layer 2.5. A photodiode 7 is constituted by the n-type silicon substrate 1 and the p-type semiconductor layer 4, and a pnp transistor 8 is constituted by the n-type semiconductor layer 3.4 and the n-type semiconductor layer 5, each having a collector, an emitter, and a base. ing. The signal line 9 is a signal line for transmitting an address signal S from a PCD shift register (not shown) to the base of the pnp transistor 8, that is, the n-type semiconductor layer 5, and the signal line 10 is a signal line for extracting signal charges to the outside. It is a line. The capacitance indicated by the symbol 11 is the junction capacitance fa c ph of the photodiode 7, and the resistance indicated by the symbol 12 is
This is an externally attached load resistance R. In addition, “BC is n
This is a DC bias applied between the type semiconductor layer 2 and the ground.

In this semiconductor photodetector, signal charges photoelectrically converted by the photodiode 7 are temporarily stored in the photodiode junction capacitor 11. At this time, address signal S
(negative polarity pulse from high level to low level) is pn
p) When applied to the base of the transistor 8, that is, the n-type semiconductor layer 5, the signal charge stored in the photodiode junction capacitor 11 flows out to the load resistor 12.

A more detailed look at this signal read operation is as follows. When the address signal S is applied to the n-type semiconductor layer 5, the difference in voltage between the n-type semiconductor layer 5 and the n-type silicon substrate l is almost negligible because the two form a so-called high-low junction. It is consumed in the n-type silicon substrate 1 under the n-type semiconductor layer 5. Therefore, the potential of the n-type silicon substrate 1 directly under the n-type semiconductor layer 5 (hereinafter referred to as channel H) becomes lower than that of other parts of the n-type silicon substrate 1, and the n-type semiconductor layer 4 Signal charges injected into the substrate 1 are concentrated in the channel H. Most of it flows into the n-type semiconductor layer 3 without flowing into the n-type semiconductor layer 5, and contributes to the output signal.

[Problem to be solved by the invention]

By the way, the p-type semiconductor layer composed of the n-type semiconductor layer 4 and the channel H
When considering an n-junction, if a sufficient signal charge is accumulated in the photodiode junction capacitor 11 and the potential difference between the two is large, the series resistance is small and the signal charge can be read out at high speed. However, if the potential difference between the n-type semiconductor layer 4 and the channel H is small, the series resistance increases, and the reading speed of signal charges decreases rapidly.

Therefore, when considering one read operation, the potential difference between the n-type semiconductor layer 4 and the channel H gradually decreases in the process of reading out the charges accumulated in the n-type semiconductor layer 4, and the read speed decreases. . Therefore, there is a limit to increasing the successive output speed.

Also, it is necessary to set the readout time for one pixel in advance,
When the exposure amount changes suddenly, it may become impossible to read out all the signal charges stored in the photodiode junction capacitor 11 within the preset readout time, resulting in problems such as poor output tracking. was there.

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, the semiconductor photodetection device of the present invention provides a second
A conductive type semiconductor region is used as a source, and a semiconductor region of the same conductive type (second conductive type) formed integrally with this region on the surface of the semiconductor substrate is used as a drain, and is formed at the boundary between these source and drain regions shallower than the source and drain regions. A junction gate type field effect transistor having the first conductivity type semiconductor region as a gate serves as an optical signal readout section. Further, the source region is arranged in a plane so as to surround the drain region.

[Effect]

When the spread of the depletion layer directly under the gate is narrowed by changing the voltage applied to the gate, the signal charge accumulated in the source region due to photoelectric conversion quickly flows to the drain. Further, if the source region is arranged in a plane so as to surround the drain region, the gate width can be increased, the channel resistance is lowered, and the time for reading signal charges is further shortened.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG.
is a plan view, (B) is a bb cross-sectional view, and (C) is a plan view.
is an equivalent circuit diagram. Note that the same or corresponding parts as in FIG. 3 are given the same reference numerals, and detailed explanation thereof will be omitted.

On the surface of the n-type silicon substrate 1, an n-type semiconductor layer 21.2 is formed.
2.24 and an n-type semiconductor layer 2.23 are formed by diffusion. Although the n-type semiconductor layers 21, 22, and 24 are formed deeper than the n-type semiconductor layer 2.23, the impurity concentration is higher in the n-type semiconductor layer 2.23. In addition, the same figure (B)
As can be seen, the n-type semiconductor layers 21, 22, and 24 are integrally formed regions.

Structurally, it is a junction gate field effect transistor 26 in which the n-type semiconductor layer 22 is the source, the n-type semiconductor layer 21 is the drain, and the n-type semiconductor layer 23 is the gate. It has become an area. Also,
pn made of an n-type silicon substrate l and an n-type semiconductor layer 22
A photodiode 25 is constructed using the junction. The capacitance indicated by the reference numeral 27 in the same figure (C) is the junction capacitance ffi C,h of the photodiode 25.

Next, the operation of this embodiment will be explained.

When the address signal S applied to the n-type semiconductor layer 23, which is the gate of the junction gate field effect transistor 26, is at a high level, the n-type semiconductor layer 23 and the n-type semiconductor layer 21 .
The pn junction formed by 22 and 24 is in a reverse bias state, and a depletion layer expands in the n-type semiconductor layer 24. Therefore, the signal charge photoelectrically converted by the photodiode 25 is temporarily stored in the photodiode junction capacitor 27. In this state, when the address signal S (negative polarity pulse from high level to low level) sent via the signal line 9 is applied to the n-type semiconductor layer 23 which is the gate of the junction gate field effect transistor 26. , the reverse bias of the pn junction formed by the n-type semiconductor layer 23 and the n-type semiconductor layers 21, 22, and 24 becomes shallower, and the depletion layer that had spread in the n-type semiconductor layer 24 becomes narrower and becomes a path for signal charges. A channel is formed. As a result, the optical signal charge accumulated in the photodiode junction capacitor ff127 is discharged at once to the n-type semiconductor layer 21 and flows out to the load resistor 12. Therefore, optical signals can be read out at high speed.

By the way, in this embodiment, the photodiode junction capacitance ff
There is a possibility that the signal charges accumulated in the photodiode 127 will flow out to the n-type semiconductor layer 23 as well, but this leakage of signal charges can be prevented by reducing the junction capacitance of the photodiode 25 and the channel of the junction gate field effect transistor 26. This can be achieved by adjusting the values of resistance, etc. This will be explained below.

Now, the signal charge is accumulated in the photodiode junction capacitor 1n27 to the saturation state, and the address signal S is applied to the gate (n-type semiconductor layer 23) of the junction gate field effect transistor 26.
The moment when it was added to

At this time, if the potential at point B is lower than the potential at point A in FIG. and flows to the load resistor 12. Therefore, first, consider the potentials at points A and B, respectively. The voltage Vt of the address signal S applied to the n-type semiconductor layer 23, which is the gate of the junction gate field effect transistor 26, is normally about 400 mV. Further, the n-type semiconductor layer 22 which is the source of the junction gate field effect transistor 26
The potential of the pn junction formed by the n-type semiconductor layer 23 serving as the gate is about 800 mV. Therefore, the potential at point A is about 1200 mV of the total potential. On the other hand, the potential at point B is R, which is the channel resistance of the junction gate field effect transistor 26, and R, which is the load resistance 12.
It is expressed as the product of the sum of L and the signal current I. Therefore, when the maximum signal current is l ph (Iaa x ), 1 (
n+ax) is efficiently taken out.

FIG. 2 is a diagram showing another embodiment of the present invention, and FIG.
A) is a plan view, and (B) is a sectional view.

This embodiment has a structure in which a p-type semiconductor layer 31, which is the drain of a junction-gate field-effect transistor 26, is surrounded by an n-type semiconductor layer 32, which is a gate electrode, as shown in the figure. effect transistor 26
The channel resistance R8h is reduced by widening the gate width. By having such a structure, the above (
1) Equation can be more easily realized.

Although the above embodiments have been described using an n-type silicon substrate, a substrate of the opposite conductivity type can also be used, and the material is not limited to silicon.

Further, in the above embodiments, each semiconductor layer is formed by diffusion, but ion implantation or other techniques may be used.

〔Effect of the invention〕

As explained above, according to the semiconductor photodetection device of the present invention, since the optical signal readout section is composed of a junction gate field effect transistor, the optical signal readout section can be used at high speed regardless of the amount of signal charge accumulated in the photoelectric conversion section. can be read out. Therefore, even when the amount of incident light changes rapidly, signal charges can be read out quickly and stably without leaving anything unread.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing another embodiment, and FIG. 3 is a diagram showing a conventional semiconductor photodetecting device. 1... N-type silicon substrate, 9... Signal line, 10...
・Signal line, 12...Load resistance, 21.22.24...
-p-type semiconductor layer, 23...n-type semiconductor layer, 25...
Photodiode, 26... Junction gate field effect transistor, 27... Photodiode junction capacitance, 3
]...p-type semiconductor layer, 32...n-type semiconductor layer. Patent applicant Hamamatsu Photonics Co., Ltd. Representative Patent Attorney
Yoshikima Shio for Hase
1) Tatsuya Figure 1 Embodiment Figure 1 Prior art

Claims (1)

[Claims] 1. A semiconductor photodetection device comprising a photoelectric conversion section and an optical signal readout section, comprising a semiconductor substrate of a first conductivity type and a semiconductor region of a second conductivity type formed on the surface thereof. A photodiode is used as a photoelectric conversion section, a second conductivity type semiconductor region constituting the photodiode is used as a source, and a semiconductor region of the same conductivity type formed integrally with this region on the surface of the semiconductor substrate is used as a drain, the boundary between these source and drain regions. A semiconductor photodetector device in which an optical signal readout section is a junction gate field effect transistor whose gate is a first conductivity type semiconductor region formed at a depth shallower than a source/drain region. 2. The semiconductor photodetecting device according to claim 1, wherein the source region is arranged in a plane so as to surround the drain region.