JPH01192209A - Phase shifter - Google Patents

Abstract

PURPOSE:To obtain a phase shifter not causing any deviation to a phase difference by providing a 2nd phase shift circuit having a 2nd low-pass filter receiving an input signal and causing a phase lag theta2 of 45 deg. phase difference with respect to the phase lag theta1 of a 1st low-pass filter and a 2nd amplifier doubling the phase delay in the output of the 2nd low-pass filter. CONSTITUTION:The 1st low-passs filter 4a comprising a resistor 2a and a capacitor 3a is interposed between a noninverting input of a 1st operational amplifier 5a and an input terminal 1 in a 1st phase shift circuit 8a. A resistor 2a and a capacitor 3a are selected for the low-pass filter 4a to provide a prescribed phase lag theta1 (preferably 22.5 deg.). Then the constants of the resistor 2b and the capacitor 3b are selected in the low-pass filter 4b to cause a phase lag theta2 (=theta1+45 deg., preferably 67.5 deg.) giving a phase difference of 45 deg. to the phase lag theta1 of the low-pass filter 4a. Thus, in case of circuit integration, even if there exists any dispersion in the characteristic of the components included in the low-pass filters, the dispersion is canceled at an objective phase difference and a phase difference of 90 deg. is set accurately.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase shifter used, for example, to generate a phase difference for creating a color signal for a color television, and particularly to prevention of variations in the phase difference. It is something.

[Conventional technology]

FIG. 3 is a circuit diagram schematically showing a conventional phase shifter. In the figure, 1 is an input terminal, and this input terminal 1 is connected to a resistor 2. A signal that is connected to the positive input terminal of an operational amplifier 5 via a low-pass filter 4 consisting of a capacitor 3 and has a predetermined phase difference with respect to the output from an output terminal 6 that is directly connected to the input terminal 1. is obtained from the output terminal 7 of the operational amplifier 5.

The conventional phase shifter is configured as described above, and the signal input to the input terminal 1 passes through the low-pass filter 4 to have a predetermined phase delay, and then is transferred to the input terminal 1 by the operational amplifier 5.
The signal is amplified to the level when it is input to the output terminal 7, and is output to the output terminal 7. On the other hand, since the output terminal 6 outputs a signal equal to the signal input to the input terminal 1, when this signal is used as a reference, the output signal obtained from the output terminal 7 of the operational amplifier 5 has a phase difference due to the low-pass filter 4. The signal has a phase difference corresponding to the delay. The above phase difference is determined by the resistor 2 of the low-pass filter 4. Resistance value of capacitor 3.

It is set to a desired value by changing the capacity ffi value.

[Problem to be solved by the invention]

In the conventional phase shifter as described above, resistor 2 and capacitor 3
Variations in the resistance and capacitance values of the two will directly appear as a shift in phase difference. In other words, when this conventional phase shifter is integrated into an IC, there will be a maximum variation of ±20% in resistance and capacitance values, and this will cause the phase difference of the obtained phase shifter to vary by ±5°. This results in variations in degree, and this poses a problem, such as causing color shift when used to create color signals for color television, for example.

This invention was made to solve these problems, and the purpose is to obtain a phase shifter that does not cause a shift in phase difference even if the resistance value and capacitance value vary due to the use of an IC. shall be.

[Means to solve the problem]

The phase shifter according to the present invention includes a first low-pass filter that receives an input signal and generates a predetermined phase delay θ1, and a first amplifier that doubles the phase delay of the output of the first low-pass filter. a first phase shift circuit having a phase shift circuit that receives the input signal and has a phase delay of 45° with respect to a phase delay θ1 of the first low-pass filter;
a second phase shift circuit having a second low-pass filter that produces a phase delay θ2 of a phase difference of and a second amplifier that doubles the phase delay of the output of the second low-pass filter; It is something that

[Function] In this invention, the same input signal is used in the first . When applied to the second phase shift circuit, the first phase shift circuit outputs an output signal with a phase delay of 2θ1 relative to the input signal, and the second phase shift circuit outputs an output signal with a phase delay of 2θ2 relative to the input signal. Output signals are obtained respectively, and when the negative output signal is used as a reference, the other output signal is obtained as a signal with a phase difference of 90°. Since the variation in the characteristics of the elements included in the second low-pass filter is the same as the variation in the characteristics of the elements included in the second low-pass filter, the variation in the phase delays 2θ1 and 2θ2 described above will also be the same, and therefore there will be no variation in the obtained phase difference. Does not occur.

〔Example〕

FIG. 1 is a circuit diagram schematically showing an embodiment of a phase shifter according to the present invention. As is clear from FIG. 1, this embodiment has two phase shift circuits 8a and 8b for one input terminal 1.
It is configured by connecting.

The first phase shift circuit 8a includes a resistor 2a and a capacitor (
A first low-pass filter 4a consisting of a capacitor>3a,
An input resistor 9a is inserted between the positive input terminal of the first operational amplifier 5a and the input terminal 1 described above, and has a resistance value equal to the resistor 2a of the first low-pass filter 4a. Connected between the negative input terminal of the amplifier 5a, and further connected between the negative input terminal and the output terminal 7a.
A feedback resistor 10a having the same resistance value is connected between the two. The resistance and capacitance values of the resistor 2a and capacitor 3a of the first low-pass filter 4a are set so as to have a predetermined phase delay θ1 (preferably 22.5°).

On the other hand, similarly for the second phase shift circuit 8b, the resistor 2b
A second low-pass filter 4b consisting of a capacitor 3b and a capacitor 3b is inserted between the non-inverting input terminal of the second operational amplifier 5b and the input terminal 1 described above. An input resistor 9b having the same resistance value as the resistor 2b is connected between the input terminal 1 and the inverting input terminal of the operational amplifier 5b, and a feedback resistor 10b having the same resistance value is further connected between the inverting input terminal and the output terminal 7b. It is configured as follows. In the second low-pass filter 4b described above, the phase delay θ1 of the first low-pass filter 4a is
Phase delay with a phase difference of 5°・θ2 (=θ1+45°
, preferably 67.5°).
Resistance value of capacitor 3b.

Capacity value is set.

Next, the operation of the above embodiment will be explained.

In the first phase shift circuit 8a of FIG. 1, the resistor 2a.

The resistance values of the input resistor 9a and the feedback resistor 10a are R1, the capacitance value of the capacitor 3a is 01, the input voltage that can be applied to the input terminal 1 is ■1, and the voltage at the non-inverting input terminal of the first operational amplifier 5a is ■ The voltage at the inverting input terminal is V-1, and the voltage at the output terminal 7a is VO.

The current flowing from the input resistor 9a through the feedback resistor 10a is 1
Then, first, Vl −V□ −2R1l ...(
1) v, -7V□ =R1+...
(2) holds true. Therefore, from equations (1) and (2), v, −
v□ = 2 (V--V□) ... (3)
holds, and from this V, -2V--V, ... (3a
) is guided. In addition, since the first phase shift circuit 8a constitutes a feedback type amplifier circuit, (4)
The relational expression holds true, and substituting equation (4) into equation (3a) yields Vo-2v, -V-...(5). From this, the gain G1 of the first phase shift circuit 4a becomes G1-vo/vl-2V+/V--1 (6). By the way, if the frequency of the input signal v0 is ω, then holds true in the first low-pass filter 4a, so
Substituting equation (7) into equation (6), one = [-R+ (jω
C1) ] /[R+(jωC1) 1 = (1-jωR1C1) /(1+jωR,C,) (8) is derived. Also, since the first low-pass filter 4a has a phase delay of G1, tanθ − (Z)CIRl ・(9)
holds true. Substituting this equation (9) into equation (8), G=
(cosθI J Stnθ1)/ (CO3θ
+j sinθ1)-cos2θ -5in”θ -2jcosθ1sinθ1 ・-(10). Therefore, −1 ...(1
1) is obtained. Also, the output signal ■ for the input signal Vi
The phase difference φ1 is = jan2θ1 (12), and from this, φ −2θ1 (13) can be found.

Similarly, 1G21-1 (14) is obtained for the gain G2 of the second phase shifter 4b, and the phase difference φ2 between the output signal V and the input signal V in the second phase shifter 4b Also φ2-202
...(15).

As mentioned above, the phase lag G2 of the second low-pass filter 4b
is set as θ2-θ1+45° (16), so the phase difference φ between the output terminals 7a and 7b is φ=2(θ2-θ1) =90° (17).

In addition, the resistance value when the phase shifter of this example is made into an IC,
If the variation in capacitance value is +20%, the above phase difference φ
(when the variation is +20%), +20 and φ (when the variation is -20%) are tan
(ωCt Ri
6° (However, R and C are the resistors 2 in the second phase shift circuit 8b.
b, input resistance 9b, feedback resistance 10b and capacitor 3
b resistance value and capacitance value), and even if the resistance value and capacitance value vary by ±20%, a signal with a phase difference of 90° can be extracted with a maximum deviation of 1.4°.

In addition, in this embodiment, the first. a second low-pass filter 4a,
4b phase delay θ, θ2, θ1-22.5°,
Since θ2=67.5° is selected, the deviation of the phase difference φ with respect to variations in resistance value and capacitance value is also minimized for the following reason. First, tanO-ωC1Rl-x1
...(18) tanO2=ωC2R2-x2
...(19), and X and X2 are each (αX 1
GG)% deviation, the deviation of θ and θ is Δθ,
Assuming Δθ2, from equations (18) and (19), tan (θ +Δθ )−(1+α)xl...(2
0) jan (θ + Δθ )−(1+α)×2...
(21) holds true. Assuming that Δθ, Δθ, and α are infinitesimally small (2G), the left side of equation (21) is Taylor expanded to obtain Δθ.

Leaving up to the first order of Δθ2, tanO+(Δθ1) sec θ1-(1+α)
Xl ・・−(22) tanO×(Δθ
2) SeCθ2 = (1+α)×2 (23). Substituting equations (18) and (19) into equations (22) and (23), Δθ = αxCO82θ 1 1 1 ... (24) Δθ −a
x 2cos θ2·(25) is obtained. Therefore, the suspension Δφ where the phase difference φ deviates from 90° is Δφ=2(Δθ −Δθ1) =2α(x cos θ −x cos
θ1)...(26) Here, since θ −θ1=45°, (26
) Substituting equations (18) and (19) into equation Δφ−2α
[tanO2CO3θ2 - tanOCO32θ] = 2a (sin θ2 CO2O3 - sin θ cos θ1) = a (sin (2θ, ,) - sin (2θ1)] - a
[5in(90°+2θ1) -sin(2θ1)] 1-α[CO3(2θ1)+5tn(2θ1)]...
−(27). Therefore, the value of θ1 that minimizes 1Δφ1 for the same α can be found from d. From this, tan (2θ1)-1 (29) is derived, and finally θ1=22.5@(θ2-67.5@).

By the way, in the above embodiment, 5a, 9a, 10a (5b,
In some cases, a capacitor for preventing oscillation is added to each feedback amplifier consisting of the feedback amplifiers 9b and 10b, which may cause a phase shift due to the added capacitor.

Therefore, as a configuration that does not require such an oscillation prevention capacitor, a differential amplifier may be used in place of the above-described operational amplifiers 5a and 5b, as shown in FIG.

In FIG. 2, transistors 15, 16, 81 and resistors 11 to 13, 103 form one differential amplifier 18, and similarly, a total of four differential amplifiers 18, 26, .
33.41 is used.

Further, 42 is a circuit for supplying a reference potential to the differential amplifier 26.41 mentioned above, and is composed of resistors 43, 107, 108 and transistors 46, 47, 85, 86. 50 is a positive potential power source, 51 is a negative potential power source, and 52 is a ground line. Furthermore, this circuit includes a transistor 53.
．． 56.59°62.77~80 and resistance 91.99
101 are provided, and a bias input is given to the bases of the transistors 77 to 86 from the input terminal 66.

Here, to explain the function of this differential amplifier 18.26, the signal input to terminal 1 is transmitted to the transistor 53.56.
The emitter follower output is inputted to the base of the transistor 15 via the emitter follower output, and the signal passed through the first low-pass filter 4a consisting of the resistor 2a and the capacitor 3a is similarly inputted to the base of the transistor 16 via the transistor 59. Here, with the gain determined by the ratio of the resistance value of the load resistor 11 to the sum of the emitter resistance value of the transistor 15.16 and the resistance value of the resistor 12.13, the signal input to the base of the transistor 15 is in reverse phase. Further, the signal inputted to the base of the transistor 16 is amplified to the positive phase, vector-combined and outputted to the terminal 67. In addition, a signal input to the base of the transistor 15 is amplified to the positive phase with a gain determined by the resistance value of the load resistor 19, and a signal input to the base of the transistor 16 is amplified to the negative phase, and the signal input to the terminal 69 is amplified to the reverse phase. Combined and output.

In the remaining differential amplifiers 33 and 41, the signal input from terminal 1 and the signal applied via transistor 62 from second low-pass filter 4b formed by resistor 2b and capacitor 3b are differentially input. It is said that
The same operation as above is performed for these differential inputs.

- As an example, resistors 11, 19, 92 are the same, resistors 12
．． 13. If 93 to 98 are the same and the phase lag of the first low-pass filter is set to 22.5 degrees and the phase lag of the second low-pass filter is set to 61.5 degrees, the terminal 67 When the phase of the output signal is Oo, the terminal 69 has a 1
A signal with a phase of 90° is output to the terminal 68 of 80°.

Therefore, by taking out the output from the terminals 68 and 69, for example, a signal with a phase difference of 90' can be obtained. Then, resistors 2a, 2b and capacitors 3a, 3b are integrated into IC.
Even with variations in the resistance value and capacitance ff1II, the shift of the phase difference of 90° can be suppressed. Further, since a capacitor for preventing oscillation is not required, no phase shift occurs due to this.

(Effects of the Invention) As described above, according to the present invention, the first phase shift circuit includes the first low-pass filter having a phase delay θ1, and the second low-pass filter having a -phase delay θ2. One input signal is given to each of the second phase shift circuits, and the phase is delayed 2θ from the two phase shift circuits.

Since it is configured to output as a 2θ2 signal and obtain a phase difference of 2(θ - θ1) - 90'' between these outputs, there will be variations in the characteristics of the elements included in the low-pass filter when integrated into an IC. Even if the variation is reflected in the output of each phase shift circuit, the variation included in the output of each phase shift circuit is canceled out in the phase difference to be obtained, and the effect is that the phase difference of 90' can be set accurately.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of a phase shifter according to the present invention, FIG. 2 is a circuit diagram showing another embodiment of the phase shifter, and FIG.
The figure is a circuit diagram showing a conventional phase shifter. In the figure, 1 is an input terminal, 2a, 2b are resistors, 3a,
3b is a capacitor, 4a and 4b are the first . The second low-pass filters 5a, 5b are respectively connected to the first . The second .degree. operational amplifiers, 8a, 8b, respectively, are connected to the first .degree. This is a second phase shift circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts. 1: Input jIIh CH 2a, 2b: Resistance Figure 1 Figure 3 Procedural Amendment (Voluntary) Date of 1939 To the Commissioner of the Japan Patent Office Mo1 Scroll 1, Indication of Case Japanese Patent Application No. 63-017784 2,
Name of the invention Phase shifter 3, Representative of the person making the amendment Moriya Shiki 5, "Detailed description of the invention column" of the specification to be amended 6, Contents of the amendment (1) Page 7, line 15 of the specification rvo-2v+-v-...(5)'', rvo-2v
ya-v1...(5)". (2) "r -2v+/v--1...(6)" on page 7, line 19 of the specification is replaced by r-2V
/v, -1...(6)". that's all

Claims (1)

[Claims] (1) A first low-pass filter that receives an input signal and generates a predetermined phase delay θ_1, and a first amplifier that doubles the phase delay of the output of the first low-pass filter. a second low-pass filter that receives the input signal and generates a phase lag θ_2 having a phase difference of 45 degrees with respect to the phase lag θ_1 of the first low-pass filter; a second amplifier that doubles the phase lag of the output of the low-pass filter; and a second phase shift circuit having a second amplifier.