JPH01192166A - Photodetector - Google Patents
PhotodetectorInfo
- Publication number
- JPH01192166A JPH01192166A JP63016672A JP1667288A JPH01192166A JP H01192166 A JPH01192166 A JP H01192166A JP 63016672 A JP63016672 A JP 63016672A JP 1667288 A JP1667288 A JP 1667288A JP H01192166 A JPH01192166 A JP H01192166A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- photodiode
- film
- film transistor
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010408 film Substances 0.000 claims abstract description 47
- 239000010409 thin film Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 238000010030 laminating Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 8
- 238000000206 photolithography Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- SIKJAQJRHWYJAI-UHFFFAOYSA-N Indole Chemical compound C1=CC=C2NC=CC2=C1 SIKJAQJRHWYJAI-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Thin Film Transistor (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
“１〒！利用分野〉
本発明は、ファクシミリやＯＣＲの光電変換部に組み込
まれる受光素子に関するものであり、とくに原稿に密着
した形で読み取る密着型イメージセンサに適用されるも
のである。Detailed Description of the Invention 1. Field of Application The present invention relates to a light receiving element incorporated in a photoelectric conversion unit of a facsimile or OCR, and is particularly applicable to a contact type image sensor that reads a document in close contact with it. It is something that
〈従来技術およびその問題点〉
最近、ファクシミリ等の原稿読み取り装置を小型化する
ために密着型イメージセンサの開発が活発に進められて
いる。これは原稿の幅と同じ長さの長尺−次元イメージ
センサを内蔵する光電変換デバイスである。従来のＣＣ
ＤやＭＯＳ型のＩＣイメージセンサを有する光電変換系
では原稿をイメージセンサ上に投影する縮小レンズ系を
必要としにその光路長確保のために装置内に大きな空間
を有しており、装置の小型化が難しい欠点があった。と
ころが、上述の密着型イメージセンサでは、この縮小レ
ンズ系が不要でイメージセンサと原稿がほぼ密着し、そ
のため装置の大幅な小型化が達成される。<Prior Art and its Problems> Recently, contact image sensors have been actively developed in order to miniaturize document reading devices such as facsimiles. This is a photoelectric conversion device that incorporates a long-dimensional image sensor whose length is the same as the width of the document. Traditional CC
A photoelectric conversion system with a D or MOS type IC image sensor requires a reduction lens system to project the original onto the image sensor, and a large space is required within the device to ensure the optical path length. There were drawbacks that made it difficult to adapt. However, in the above-mentioned contact type image sensor, this reduction lens system is not necessary, and the image sensor and the document are brought into close contact with each other, thereby achieving a significant reduction in the size of the apparatus.
従来の密着型イメージセンサの構成例を第２図に示す。An example of the configuration of a conventional contact type image sensor is shown in FIG.
この方式は、絶縁性基板１０上の光導電膜１１に蓄積し
た電荷を、電界効果トランジスタなどのアナログスイッ
チ１２を走査して順次読み出すものであり、走査回路１
３を構成するシフトレジスタと絶縁性基板１０上のアナ
ログスイッチ１２の間を画素ごとに接続している。In this method, charges accumulated in a photoconductive film 11 on an insulating substrate 10 are sequentially read out by scanning an analog switch 12 such as a field effect transistor.
The shift register configuring 3 and the analog switch 12 on the insulating substrate 10 are connected for each pixel.
さらに、従来の受光素子の構造を詳細に説明するために
、受光素子の断面図を第３図に示す。Furthermore, in order to explain the structure of a conventional light receiving element in detail, a sectional view of the light receiving element is shown in FIG.
第３図において、受光部であるフォトダイオードは、絶
縁性基板２０上に、下部電８ｉ２１、光導電膜２２、上
部電極２３を順次積層して構成されている。In FIG. 3, the photodiode serving as a light receiving section is constructed by sequentially laminating a lower electrode 8i21, a photoconductive film 22, and an upper electrode 23 on an insulating substrate 20.
一方、アナログスイッチである薄膜トランジスタは逆ス
タガー構造をとっており、上記同一絶縁性基板２０上に
、ゲート電極２４、ゲート絶縁膜２５、高抵抗半導体９
２６を順次積層し、さらに上記高抵抗半導体膜２６上に
、低抵抗半導体膜２７及び第一、第二主電極２８．２９
をパターニング形成して構成しである。ここで、フォト
ダイオードの前記上部電極２３と薄膜トランジスタの前
記第一主電極２８は一体化され配線を兼ねている。On the other hand, a thin film transistor, which is an analog switch, has an inverted staggered structure, in which a gate electrode 24, a gate insulating film 25, a high resistance semiconductor 9
26 are sequentially laminated, and further on the high resistance semiconductor film 26, a low resistance semiconductor film 27 and first and second main electrodes 28 and 29 are formed.
It is formed by patterning. Here, the upper electrode 23 of the photodiode and the first main electrode 28 of the thin film transistor are integrated and also serve as wiring.
しかしながら、上記薄膜トランジスタはスイッチング速
度が極めて遅く密着型イメージセンサに応用した場合、
その読取速度は、上記薄膜トランジスタのスイッチング
速度に律速され、スイッチ素子としては特性が不十分で
あった。However, the above-mentioned thin film transistor has an extremely slow switching speed and when applied to a contact type image sensor,
Its reading speed was determined by the switching speed of the thin film transistor, and its characteristics as a switching element were insufficient.
このため、マトリクス配線としてスイッチング回数を低
減する等の対策が必要となっており、この方法も実用化
にはなお問題があった。Therefore, it is necessary to take measures such as reducing the number of times of switching by using matrix wiring, and this method still has problems in its practical application.
一方、高速スイッチングが可能な薄膜トランジスタも考
案されている。On the other hand, thin film transistors capable of high-speed switching have also been devised.
上記薄膜トランジスタは縦型薄膜トランジスタと称され
、その基本的素子構造を第４図に示す。The thin film transistor described above is called a vertical thin film transistor, and its basic element structure is shown in FIG.
上記薄膜トランジスタは、絶縁性基板３０に対しほぼ垂
直方向に電流が流れる縦型構造を有し、ドレイン及びソ
ース等の主電極領域３１．３２の間に高抵抗半導体薄膜
３３がはさまれた多層構造の側面にゲート絶縁膜３４、
ゲート電極３５が順次形成され、チャネル長しが前記高
抵抗薄膜の厚みでほぼ決められる構造を有している。The thin film transistor has a vertical structure in which current flows almost perpendicularly to the insulating substrate 30, and has a multilayer structure in which a high-resistance semiconductor thin film 33 is sandwiched between main electrode regions 31 and 32 such as a drain and a source. A gate insulating film 34 is provided on the side surface of the
Gate electrodes 35 are sequentially formed, and the structure has a structure in which the channel length is approximately determined by the thickness of the high-resistance thin film.
しかしながら、上記構造を有した縦型薄膜トランジスタ
は、ドレイン及びソース等の主電極領域３１．３２が絶
縁性基板３０に対し三次元方向に積層されているため主
電極の取り出しが比較的困難で、多層配線をともなうた
め、配線間のショート等の欠陥が問題とされていた。However, in the vertical thin film transistor having the above structure, the main electrode regions 31 and 32 such as the drain and source are stacked three-dimensionally on the insulating substrate 30, so it is relatively difficult to take out the main electrodes, and the multilayer Since wiring is involved, defects such as short circuits between wirings have been a problem.
〈発明の目的〉
本発明は、上述の従来の受光素子の問題点に鑑みてなさ
れたもので、高速スイッチングが可能で、しかも歩留り
の良い受光素子を提供することを目的とする。<Objective of the Invention> The present invention has been made in view of the problems of the conventional light receiving element described above, and an object of the present invention is to provide a light receiving element that is capable of high-speed switching and has a high yield.
く問題点を解決するための手段〉
すなわち本発明は、絶縁性基板上に共通透明電極、光導
電膜、個別金属電極を順次積層して構成されたフォトダ
イオードと、前記フォトダイオードと基板を同一とし、
前記個別金属電極を第一主電極として共用し、高抵抗半
導体膜、第二主電極を順次積層した多層体の側面から基
板表面にかけてゲート絶縁膜及びゲート電極を設けてな
る縦型薄膜トランジスタの２つを一体的な構造をもたせ
て形成した事を特徴とする受光素子である。Means for Solving the Problems> In other words, the present invention provides a photodiode configured by sequentially laminating a common transparent electrode, a photoconductive film, and individual metal electrodes on an insulating substrate, and a photodiode configured by sequentially laminating a common transparent electrode, a photoconductive film, and an individual metal electrode on an insulating substrate, and a method in which the photodiode and the substrate are the same. year,
Two vertical thin film transistors in which the individual metal electrode is shared as a first main electrode, and a gate insulating film and a gate electrode are provided from the side surface of a multilayer body in which a high-resistance semiconductor film and a second main electrode are sequentially laminated to the substrate surface. This is a light-receiving element characterized by having an integral structure.
〈発明の構成〉
第１図には、本゛発明による受光素子の構造が示されて
いる。<Structure of the Invention> FIG. 1 shows the structure of a light receiving element according to the present invention.
絶縁性基板１上に、共通透明電極２、光導電膜３、個別
金属電極４を順次積層して構成されたフォトダイオード
と、前記同一絶縁性基板１上に形成された下層より前記
個別電極と共用する第一主電極４、高抵抗半導体膜５、
第二主電極６とからなる積層薄膜と、フォトダイオード
とは反対側の前記第−及び第二主電極４．６の間に露出
する前記高抵抗半導体膜５の表面上に設けられたゲート
絶縁膜７とゲート電極８とより成る縦型薄膜トランジス
タを一体的に構成した構造を有している。A photodiode is constructed by sequentially laminating a common transparent electrode 2, a photoconductive film 3, and an individual metal electrode 4 on an insulating substrate 1; A shared first main electrode 4, a high resistance semiconductor film 5,
A gate insulator provided on the surface of the high-resistance semiconductor film 5 exposed between the laminated thin film consisting of the second main electrode 6 and the second and second main electrodes 4.6 on the side opposite to the photodiode. It has a structure in which a vertical thin film transistor consisting of a film 7 and a gate electrode 8 is integrally constructed.
次に、上記受光素子の外部回路との接続について第Ｎり
第２図を用いて説明する。上記縦型薄膜トランジスタは
アナログスイッチ１２に対応し、ゲート電極８は走査回
路１３に接続する。この時上記ゲート電極８はフォトダ
イオードと反対方向に容易に取り出す事が可能である。Next, the connection of the light receiving element to an external circuit will be explained using FIG. The vertical thin film transistor corresponds to the analog switch 12, and the gate electrode 8 is connected to the scanning circuit 13. At this time, the gate electrode 8 can be easily taken out in the opposite direction to the photodiode.
一方、第二主電極６は読み出し回路１４に接続する。こ
の時、第二主電極６は、フォトダイオードの上部を経由
し、上記ゲート電極８の引き出°し側とは反対側に位置
するフォトダイオード側に配線を引き出す、ここで上記
第二主電極６と第一主電極４との間のシ四−トの防止の
ために両電極間に絶縁膜９を設けている。さらに、フォ
トダイオードは通常バイアスを印加して使用するため、
共通透明電極２は電圧源１５に接続する。この時、上記
共通透明電極２は各素子ごとに分離する必要はなく第１
図前方又は後方に引き出すことは容易である。On the other hand, the second main electrode 6 is connected to the readout circuit 14 . At this time, the second main electrode 6 leads out the wiring to the photodiode side located on the opposite side to the lead-out side of the gate electrode 8 through the upper part of the photodiode. An insulating film 9 is provided between the electrodes 6 and the first main electrode 4 to prevent a sheet from forming between the two electrodes. Furthermore, since photodiodes are usually used with an applied bias,
The common transparent electrode 2 is connected to a voltage source 15 . At this time, the common transparent electrode 2 does not need to be separated for each element;
It is easy to pull the figure forward or backward.
上述のごとく、本発明ではフォトダイオードと高速スイ
ッチング可能な縦型薄膜トランジスタを一体化構成する
事により上記目的を実現するものである。As described above, the present invention achieves the above object by integrating a photodiode and a vertical thin film transistor capable of high-speed switching.
〈発明の実施例〉 本発明の実施例を第１図を参照して詳述する。<Embodiments of the invention> An embodiment of the present invention will be described in detail with reference to FIG.
まず、ガラス、セラミック等絶縁性基板ｌ上に共通透明
電極２としてＤＣスパッタリング法等により２０００人
程度０厚みに酸化インジウムスズ（以下ＩＴＯと称する
）を被着後フォトリソグラフィー法により前記ＩＴＯを
共通電極形状、にパターニングする。First, indium tin oxide (hereinafter referred to as ITO) is deposited as a common transparent electrode 2 on an insulating substrate such as glass or ceramic to a thickness of about 2000 by DC sputtering method, and then the ITO is applied as a common electrode by photolithography. Patterning into shapes.
次に、前記共通透明電極ＩＴ０２上に、１００％ＳｉＨ
４をグロー放電によって分解することにより光導電膜と
してインドリンシンク型水素化アモルファスシリコン（
以下１−ａ−５ｉ：Ｈと称する）膜３を厚さ約１μｍに
覆う、この時のパターン形成は、所定形状にエツチング
形成された金属性治具を絶縁性基板１表面の所定装置に
密着して配置して行なう。また、１−ａ−３ｉ：Ｈ膜３
は高抵抗膜のため、成膜後のフォトリソグラフィー法に
よるパターニング工程は必要としない。Next, on the common transparent electrode IT02, 100% SiH
4 was decomposed by glow discharge to produce indoline sink type hydrogenated amorphous silicon (
In this pattern formation, a metal jig etched into a predetermined shape is closely attached to a predetermined device on the surface of the insulating substrate 1. and place it. In addition, 1-a-3i:H film 3
Since this is a high-resistance film, there is no need for a patterning process using photolithography after film formation.
次に、前記１−ａ−５ｔ：Ｈ膜３上に個別金属電極４と
して１−ａ−３ｉ：Ｈ膜とのオーミック特性に優れた金
属例えばＣ「、Ｔｉを電子ビーム蒸着法により被着後フ
ォトリソグラフィー法により各素子ごとに分離された形
状にパターニングする。この時、前記個別金属電極４は
、並列に設置する縦型薄膜トランジスタの第一主電極４
と共用するためフォトダイオードの側面方向の絶縁性基
板１上まで引き出してお く 。Next, a metal having excellent ohmic characteristics with the 1-a-3i:H film, such as C' or Ti, is deposited on the 1-a-5t:H film 3 as an individual metal electrode 4 by electron beam evaporation. The individual metal electrodes 4 are patterned into separate shapes for each element by photolithography.At this time, the individual metal electrodes 4 are connected to the first main electrodes 4 of the vertical thin film transistors installed in parallel.
In order to share it with the photodiode, pull it out to the top of the insulating substrate 1 in the side direction of the photodiode.
さらに、フォトダイオードの個別金属電極４と共用して
いる第一主電極４上に、前記ｉ −ａ −Ｓ ｉ ：
ＩＩ光導電膜３と同様の方法で作製する高抵抗半導体膜
である１−ａ−３ｉ：Ｈ膜５を堆積する。その後、フォ
トリソグラフィー法によりパターニング形成する。Further, on the first main electrode 4 which is shared with the individual metal electrode 4 of the photodiode, the i-a-S i :
A 1-a-3i:H film 5, which is a high-resistance semiconductor film manufactured by the same method as the II photoconductive film 3, is deposited. Thereafter, patterning is performed using a photolithography method.
ここで、前記第一主電極を兼ねた個別金属電極４と後に
作製する第二主電極６の配線への引き出し部のショート
を回避するために、前記個別金属電極４上からフォトダ
イオード側面にか°けて、ＳｉＨ４及びＭＨＩの混合ガ
スをグロー放電分解し絶縁膜９であるＳｉＮ、膜９を堆
積し、その後、フォトリソグラフィー法によりパターニ
ングする。Here, in order to avoid a short circuit between the individual metal electrode 4, which also serves as the first main electrode, and the wiring of the second main electrode 6, which will be fabricated later, the metal electrode 4 is connected from above the individual metal electrode 4 to the side surface of the photodiode. Then, a mixed gas of SiH4 and MHI is decomposed by glow discharge to deposit an SiN film 9, which is an insulating film 9, and then patterned by photolithography.
次に、前記１−ａ−３ｔ：Ｈ膜５及び前記ＳｉＮｘ膜９
に、読み出し回路部への配線を兼ねた第二主電極６を、
ＡＩを材料として電子ビーム蒸着法により堆積しさらに
フォトリソグラフィー法によりパターニングする。Next, the 1-a-3t:H film 5 and the SiNx film 9
, a second main electrode 6 which also serves as wiring to the readout circuit section,
The material is deposited by electron beam evaporation and patterned by photolithography.
続いて、前記第二主電極６上に、ゲート絶縁膜７として
上記絶縁膜９と同様な方法によってＳｉｎ。Subsequently, on the second main electrode 6, a gate insulating film 7 is formed using a method similar to that used for the insulating film 9.
絶縁膜７を堆積及びパターニングする。An insulating film 7 is deposited and patterned.
さらに、前記ゲート絶縁膜７上にゲート電極８としてＡ
Ｉを電子ビーム蒸着法にて被着後、パターニングして作
製する。この時、ゲート電極８作製と同時に走査回路へ
の配線部も作製する。Further, a gate electrode 8 is formed on the gate insulating film 7.
It is manufactured by depositing I by electron beam evaporation and then patterning it. At this time, at the same time as the gate electrode 8 is fabricated, a wiring portion to the scanning circuit is also fabricated.
実施例においては、フォトダイオード部及び縦型薄膜ト
ランジスタ部の各構造については、最も基本的構造で示
したが、各素子の特性向上のために半導体金属界面にブ
ロッキング層や低抵抗半導体層を挿入するなどの構造で
も本発明は有効である。In the examples, the structures of the photodiode part and the vertical thin film transistor part are shown in the most basic structure, but in order to improve the characteristics of each element, a blocking layer or a low-resistance semiconductor layer is inserted at the semiconductor-metal interface. The present invention is also effective with such a structure.
〈発明の効果〉
以上、詳細に説明したように本発明の受光素子は、スイ
ッチング速度の速い縦型薄膜トランジスタをフォトダイ
オードの駆動に使用するため、高速読み取りが可能とな
る。<Effects of the Invention> As described above in detail, the light receiving element of the present invention uses a vertical thin film transistor with a high switching speed to drive the photodiode, and thus enables high-speed reading.
さらに、フォトダイオード素子毎に高速動作可能な縦型
薄膜トランジスタを一体化搭載する事により、従来のマ
トリクス配線、多層配線が不要な、第１図は、本発明の
受光素子の一実施例を示す断面説明図である。Furthermore, by integrating a vertical thin film transistor capable of high-speed operation into each photodiode element, conventional matrix wiring and multilayer wiring are unnecessary. It is an explanatory diagram.
第２図は、−船釣なイメージセンサの一例を示す構成図
である。FIG. 2 is a configuration diagram showing an example of a boat fishing image sensor.
第３図は、従来の受光素子の一例を示す断面説明図であ
る。FIG. 3 is an explanatory cross-sectional view showing an example of a conventional light receiving element.
第４図は、従来の縦型薄膜トランジスタの一例を示す断
面説明図である。FIG. 4 is an explanatory cross-sectional view showing an example of a conventional vertical thin film transistor.
１・・・絶縁性基板 ２・・・共通透、明電極３・
・・光導電膜 ４・・・第一主電極５・・・高抵
抗半導体膜
６・・・第二主電極 ７・・・ゲート絶縁膜８・・
・ゲート電極 ９・・・絶縁膜１０・・・絶縁性基
板 １１・・・フォトダイオード１２・・・薄膜トラ
ンジスタ
１３・・・走査回路 １４・・・読み出し回路１５
・・・電圧源 ２０・・・絶縁性基板２１・・・
下部電極 ２２・・・光導電膜２３・・・上部電極
２４・・・ゲート電極２５・・・ゲート絶縁ｍ
２６・・・高抵抗半導体膜２７・・・低抵抗半導体膜
２８・・・第一主電極 ２９・・・第二主電極３０・
・・絶縁性基板 ３１・・・第一主電極３２・・・第
二主電極 ３３・・・高抵抗半導体膜３４ゲート絶縁
膜 ３５・・・ゲート電極時 許 出 願
人
凸版印刷株式会社
代表者 鈴木和夫
第１図
第２図
第３図
第４図1... Insulating substrate 2... Common transparent, bright electrode 3...
...Photoconductive film 4...First main electrode 5...High resistance semiconductor film 6...Second main electrode 7...Gate insulating film 8...
- Gate electrode 9... Insulating film 10... Insulating substrate 11... Photodiode 12... Thin film transistor 13... Scanning circuit 14... Readout circuit 15
...Voltage source 20...Insulating substrate 21...
Lower electrode 22... Photoconductive film 23... Upper electrode 24... Gate electrode 25... Gate insulation m
26... High resistance semiconductor film 27... Low resistance semiconductor film 28... First main electrode 29... Second main electrode 30.
...Insulating substrate 31...First main electrode 32...Second main electrode 33...High resistance semiconductor film 34 Gate insulating film 35...For gate electrode Application
Representative Kazuo Suzuki, Jintoppan Printing Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
電極を順次積層して構成されたフォトダイオードと、前
記フォトダイオードと基板を同一とし、前記個別金属電
極を第一主電極として共用し、高抵抗半導体膜、第二主
電極を順次積層した多層体の側面から基板表面にかけて
ゲート絶縁膜及びゲート電極を設けてなる縦型薄膜トラ
ンジスタの２つを一体的な構造をもたせて形成した事を
特徴とする受光素子。1) A photodiode configured by sequentially laminating a common transparent electrode, a photoconductive film, and individual metal electrodes on an insulating substrate, and the photodiode and the substrate are the same, and the individual metal electrodes are shared as the first main electrode. However, a vertical thin film transistor is formed by forming a multilayer structure in which a high-resistance semiconductor film and a second main electrode are sequentially laminated, and a gate insulating film and a gate electrode are provided from the side surface to the surface of the substrate to have an integrated structure. A light receiving element characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63016672A JPH01192166A (en) | 1988-01-27 | 1988-01-27 | Photodetector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63016672A JPH01192166A (en) | 1988-01-27 | 1988-01-27 | Photodetector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01192166A true JPH01192166A (en) | 1989-08-02 |
Family
ID=11922804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63016672A Pending JPH01192166A (en) | 1988-01-27 | 1988-01-27 | Photodetector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01192166A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320221B1 (en) | 1998-12-30 | 2001-11-20 | Hyundai Electronics Industries Co., Ltd. | TFT-LCD having a vertical thin film transistor |
| JP2020512678A (en) * | 2017-03-13 | 2020-04-23 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Semiconductor device, array substrate, and method for manufacturing semiconductor device |
-
1988
- 1988-01-27 JP JP63016672A patent/JPH01192166A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320221B1 (en) | 1998-12-30 | 2001-11-20 | Hyundai Electronics Industries Co., Ltd. | TFT-LCD having a vertical thin film transistor |
| JP2020512678A (en) * | 2017-03-13 | 2020-04-23 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Semiconductor device, array substrate, and method for manufacturing semiconductor device |
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