JPH01192099A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a non-volatile memory having the test function of a memory transistor in a short write time by providing a startup time constant change means for a high voltage pulse and a means to generate control signals with different pulse width. CONSTITUTION:When a selection signal STM is set at an 'H', and a gate 25 is closed, and the control signal, the inverse of SPRP is selected, and it is set at an 'L' at a time t1, FETs (Q1-Q3) are turned OFF and a Q4 is turned ON. Since a signal line L1 is grounded via the Q4 though switching capacitor 23 is activated, a high voltage generation circuit 20 rises steeply to a high voltage Vpp by a time constant only of the floating capacity of an output part. When the control signal, the inverse of SPRP is set at the 'H' after the lapse of around the half of the time t1, the Q3 is turned ON, and the capacitor 23 is inactivated, and the Q1 is turned ON, and the output of the high voltage generation circuit 20 is grounded compulsorily. Thus, since it is possible to rise the high voltage Vpp steeply by reducing the pulse width of the control signal, the inverse of SPRP to around the half, it is possible to apply an electric field larger than the ordinary one on the tunnel oxide film of a non-volatile memory device, and to perform the test of the memory transistor in the half time of an ordinary write time.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having a test function such as detecting defects in memory transistors.

(Prior Art) FIG. 3 is a sectional view showing the structure of a memory transistor MQ of a nonvolatile semiconductor memory device. As shown in the figure, P
N+ type scattered layers 1112 are formed at intervals on the surface of the semiconductor substrate 10, and serve as a drain region for the n+ type scattered layer 11 and a source region for the n+ type scattered layer 12. This P-type semiconductor substrate 10 is covered with a gate oxide film 13, and a part of the drain region 11 is thinned to form a tunnel oxide film 13a.
Use as. A floating gate 14 is formed on this gate oxide 11113. Therefore, the 70-ring gate 14 has a structure having four parts only on the tunnel oxide 1113a. A thin oxide film 15 covers the 70-ring gate 14, and a control gate 16 covers the oxide 1!15.

Data is collected into the memory transistor MQ having such a structure by injecting and removing electrons into the floating gate 14.

Electrons are injected into and removed from the floating gate 14 via the floating gate 14 and the tunnel oxide film 13a of the drain region 11@.

When electrons are injected into the floating gate 14, the threshold voltage of the memory transistor MQ increases (erased state).
, when electrons are removed from floating gate 14, the threshold voltage of memory transistor MQ becomes low (programmed state).

The above-mentioned injection of electrons into the control gate 14 of the memory transistor MQ causes the injection of electrons into the control gate 16 of the memory transistor MQ.
By applying a high voltage of VIW and grounding the drain 11 of the memory transistor MQ, the potential of the 70-ting gate 14 is raised to a high potential, and a tunnel current flows from the drain 11 to the 70-ting gate 14. Realize it.

In addition, when drawing electrons from the floating gate 14 to the drain 11, the drain 1 of the memory transistor MQ
1 to the high voltage vPP and the control gate 16 to the ground level.

In this way, in order to change the threshold voltage of the memory transistor MQ, a high voltage v1. must be applied. Therefore, the high voltage VPP boosted by the high voltage switch (not shown) is transferred to the memory transistor M.
It is applied to the control gate 16 or drain 11 of Q.

However, a? If the output of the ti pressure switch is directly applied to the control gate 16 or the drain 11 of the memory transistor MQ, the time constant for the rise of the output waveform of the high voltage VPP is small and rises steeply, causing great damage to the tunnel oxide film 13a. In the worst case, there was a problem that the tunnel oxide film 13a would be destroyed.

Therefore, it is necessary to reduce the damage caused to the tunnel oxide film 13a by setting the rising time constant appropriately, and a high voltage control circuit as shown below is provided.

FIG. 4 is a circuit diagram showing the high voltage control circuit.

In the figure, the output voltage of the high voltage generation circuit 20 is divided by C1/(C
I+02), which is input as a sample signal to the positive input section of the comparator 21 via the connection line L1. On the other hand, the power supply voltage V from 0■. A signal S, which rises steeply to C, is input to the negative input portion of the comparator 21 via the switched capacitor 23 and the connection line L2. In addition, a capacitor C whose one electrode is grounded is connected to the connection line L2.
The other electrode of No. 3 is connected. Furthermore, the output node N2° of the voltage generating circuit 20, the connection line L1. Transistors Q1.L2 each have a source grounded and a control signal PRP applied to the gate. Q2. The drain of Q3 is connected.

・Switched capacitor 23 is connected to signal Sv, connection LL2
A transistor TI connected in series between.

It is composed of a capacitor C4 having one electrode connected between T2 and these transistors TI and T2, and the other electrode being grounded. A 0 clock φ1 inverted clock φ is applied to the gates of the transistors T1 and T2, and a signal S is applied to the drain of the transistor T1.
A connection line L2 is connected to the source of. The switch capacitor 23 acts as a resistance component, and its resistance value is R=1/(λ・C4
). The operation of generating high voltage VPP will be described below with reference to the timing diagram of FIG.

When the -JtXl signal PRP falls and becomes active at time t1, a time constant (R-03=C3/(λ・
C4), the rising edge of the output voltage of the signal Sv is waveform-shaped and input to the negative input section of the comparator 21 as the reference voltage V1.

Therefore, the comparator 21 provides the B voltage generation circuit 20 with the difference between the reference voltage v1 and the sample signal of the high voltage generation circuit 20 described above as the feedback signal S, so that the voltage rises with the same rising waveform as the reference voltage 1. When the output of the high voltage generation circuit 20 rises to the high voltage ■PP level,
The waveform is shaped and becomes rukotoni. Tsumari, VP, = V1X
(CI +C2)/C1.

Then, when the control signal PRP becomes "HII" at time t2 after a period T1 has elapsed from time t, transistors Q2 and Q
3 is turned on, the voltage divider 22 and the switched capacitor 23 are inactivated, and the transistor Q1 is also turned on, so that the output of the high voltage generation circuit 20 is forcibly grounded to the "L" level.

(Problem to be Solved by the Invention) Since the conventional non-volatile semiconductor memory device is configured as described above, the drain or gate of the memory cell transistor always receives a waveform-shaped high voltage with a slow rise when writing data. (2) PP is applied.Therefore, during testing, it is not possible to apply strong stress to the tunnel oxide film of the memory transistor, resulting in the problem that it is difficult to screen for defective memory cells.

In addition, since the rise is slow, the high voltage ■PP generation time must be well set in order to write accurately, resulting in a problem that the loading time becomes long.

This invention was made to solve the above-mentioned problems, and applies strong stress to the tunnel oxide film of the memory transistor as necessary. It is an object of the present invention to provide a nonvolatile semiconductor memory device in which it is possible to select whether or not to write data, and to perform sufficient writing even in a short writing time.

(Means for Solving Problem 111) A nonvolatile semiconductor memory device according to the present invention has a voltage of 1IJ.
The output time of the high voltage pulse whose waveform is shaped by the 111 circuit is determined by the pulse width of the control signal, and the voltage ll1I1
time constant changing means for changing the rising time constant of the high voltage pulse by determining whether or not a waveform shaping function of one circuit is enabled; and i for selectively generating a plurality of signals having different pulse widths as the control signal. and a control signal generating means.

(Operation) The control signal generating means of the present invention selectively generates a plurality of signals having different pulse widths as the control signal, so when the rise of the high voltage pulse is steep, the control signal generating means of the present invention generates a control signal with a relatively long pulse width. When a high voltage pulse is generated and the rise of the high voltage pulse is gradual, a control signal with a relatively short pulse width can be generated.

(Embodiment) Fig. 1 is a circuit diagram showing the vicinity of a high voltage control circuit in a non-volatile semiconductor memory device which is an embodiment of the present invention.Hereinafter, only the parts different from the conventional example shown in Fig. 4 will be described. .

The control signal generating circuit 24 selectively applies either the control signal PRP or the IIJIII signal 5PRP, which has a shorter pulse width than the signal PRP, to the gates of the transistors 01 to Q3.

The control signal generation circuit 24 generates a selection signal! as shown in the figure. 8
Control signals 5PRP and PRP are selectively generated by turning on one of the transfer gates 25 and 26 using sTM. In other words, the selection signal STM is
, the transfer gate 25 is turned on (transfer gate 26 is turned off), and the till tlO signal MSPI
'(Pl! selection L) When the selection signal STM is set to °L'', the transformer 77 gate 26 is turned on (transfer gate 25 is turned off), and the control l signal PPP is selected and generated.

Also, a node N between capacitors C1 and C2 of the voltage divider 22
A transistor Q4 whose source is at ground level is newly connected to the drain of 22, and the control signal STM is applied to the gate of this transistor Q4.

FIG. 2 is a timing diagram showing the operation of the voltage control circuit shown in FIG. 1 when the control signal 5PRP is selected. The operation will be explained below with reference to the same figure.

By setting the selection signal STM to "H" and turning on the transformer 77 gate 25, the control signal 5PRP is selected and generated by the control signal generation circuit 24. This control signal 5P
When RP falls to the 11 L II level at time t, all transistors 01 to Q3 are turned off. Further, since the selection signal STM is H'', the transistor Q4 is turned on.

As a result, the switched capacitor 23 is activated, but
Since the connection line L1 is led to the ground level via the transistor Q4 in the on state, the voltage divider 22 is not activated and the positive input part of the comparator 21 is always "L", and the negative input part of the comparator 21 is connected to the conventional Similarly, the time constant R-C3
A waveform-shaped signal S is applied to. Therefore, the high voltage generating circuit 20 is in an uncontrolled state, and as shown in the figure, the high voltage v1. occurs.

Then, at time t3, after a relatively short period ■2 (about half of m1ilT1 in FIG. 5) has elapsed, 171
When the 1B signal 5PRP becomes “H”, the transistor Q3
When turned on, the switched capacitor 23 is inactivated, and the transistor Q1 is also turned on, so that the output of the high voltage generation circuit 20 is forcibly grounded to the "LH" level.

In this way, the pulse width of the control signal 5PRP is T.

The generation time of the high voltage vPP is reduced to about half that of the conventional one, but the high voltage v3. Since the voltage rises steeply, the electric field applied to the tunnel oxide film 13a of the memory transistor MQ becomes larger than usual, so that the threshold voltage of the memory transistor MQ can be changed, so there is no problem with the dust-containing performance.

Also, when the control signal PPP is selected (the selection signal STM is L'')
, transistor Q4 is turned off, the circuit becomes equivalent to the conventional circuit (FIG. 4), and writing is performed at the timing shown in FIG.

Therefore, during normal write operation, select signal STM is set to "L".
Then, by generating the control signal PPP, only a weak stress is applied to the tunnel oxide film of the memory transistor, so writing is performed without damaging it.On the other hand, when testing the memory transistor, the selection signal STM is set to "H" and the control signal is By generating the signal 5PRP, a relatively strong stress is applied to the tunnel oxide film of the memory transistor, thereby making it possible to easily screen out defective memory transistors. Moreover, the pulse width of the control signal 5PRP during testing is the same as that of the control signal PPP during normal intermission.
Since the test time can be reduced by about half of the required time, the test time can be shortened by shortening the set-up time.

〔Effect of the invention〕

As described above, according to the present invention, the waveform shaping function of the voltage control circuit is disabled by the time constant changing means, the voltage pulse is raised steeply, and the control signal generating means generates a control signal with a relatively short pulse width. Selective generation has the effect of applying strong stress to the tunnel oxide film of the memory transistor in a short write time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the periphery of the voltage control circuit in a nonvolatile semiconductor memory device which is an embodiment of the present invention, and FIG.
The figure is a timing diagram showing the operation of the high voltage control circuit shown in Fig. 1, Fig. 3 is a sectional view showing the structure of a memory transistor, Fig. 4 is a circuit diagram showing the surroundings of a conventional high voltage 1iIIIO circuit, and Fig. 5 is a timing diagram showing the operation of the high voltage control circuit shown in Fig. 1. This figure is a timing diagram showing the operation of the high voltage control circuit shown in FIG. 4. In the figure, 20 is a tXIR pressure generation circuit, 21 is a comparator, 22 is a voltage divider, 23 is a switched capacitor,
24 is a control signal generation port, STM is a selection signal, and 5PRP
, PPP are control signals. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1 Figure 24 L---1+--J Figure 2 Figure 3 Figure 4 PP Figure 5 Procedural amendment (voluntary) June 6, 1988 Mr. Commissioner of the Patent Office Zo□Noodles 1, Incident Display of patent application No. 63-017787 2,
Name of the invention: Non-volatile semiconductor memory device 3, Person making the correction (Contact information: 03 (213) 3421 Permit Department) -, -5
, "Detailed explanation column of R light" of specification m to be corrected 6. Contents of correction (1) ``Control signal PRPJ in 8th to 9th line of page 5 of the specification is changed to υ control signal PRPJ. Correct. That's all.

Claims (1)

[Claims] (1) A nonvolatile semiconductor memory device in which the output time of a high voltage pulse whose waveform is shaped by a voltage control circuit is determined by the pulse width of a control signal, the device determining whether or not the waveform shaping function of the voltage control circuit is enabled or disabled. A nonvolatile semiconductor memory device comprising: time constant changing means for changing the rising time constant of the high voltage pulse; and control signal generating means for selectively generating a plurality of signals having different pulse widths as the control signal.