JPH01192085A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize a fast clear mode by writing clear data latched by a sense amplifier on a memory cell in a word line unit, and simultaneously outputting the clear data to the outside in serial. CONSTITUTION:When an address is supplied from the outside, a row address counter 7 is set at the state of the address, and a counter address is inputted to a row decoder 3, thereby, one word line is selected by the address. Meanwhile, to a column decoder 4, for example, all addresses are inputted at states with low levels from the counter 8 of column address. Thereby, one column selection line is activated and the clear data is outputted to the outside. Thus, the clear data latched by the sense amplifier 2 is written on all of the cells connected to one word line, and simultaneously, it is possible to output the data to the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, and particularly to a dynamic memory.

(Prior art) Among semiconductor memory devices that integrate Mos transistors, dynamic RAM (DRAM), which has a memory cell configuration of one transistor and one capacitor, has the smallest memory cell area per bit and is suitable for high integration. Because it is suitable, the minimum processing size is currently 4Mbit with 17a or less.
DRAMs have been announced one after another by domestic and foreign companies, and mass production is expected to begin in the near future.

Along with this increase in integration, each company is making improvements in areas such as higher speed and more bits to meet diversifying needs. In particular, with regard to specialization, the purpose is to incorporate memory peripheral functions for specific application fields to provide easier-to-use memory. The most typical field of specialization is the field of image memory.

Since the main purpose of an image memory is to temporarily store an image and output it to a display device at an arbitrary time, the frequency of clearing or writing of memory cell data is high.

In particular, clear the data displayed on the image data display device,
Moreover, the contents of memory cells are often cleared in preparation for the next write. Conventionally, in such a case, a method has been adopted in which clear data is first written into all cells, and then all data is read out to clear one display data.

(Problems to be Solved by the Invention) When this method is used, it takes a time equal to (number of memory bits) x (cycle time) x 2 to clear one display data, which is difficult for image processing that requires high speed.

This is extremely inefficient work.

Furthermore, there is a match window function as a method for processing one image, but when clearing only the data within one window, when using conventional DRAM,
Very difficult to use. In recent years, one of the demands from users is that they particularly desire a DRAM with the above function (window clearing function). In the present invention, a sense up which has the function of amplifying information from a cell is first activated, thereby latching certain information, and subsequently this sense up data is written into the memory cell, and at the same time this sense up data is externally written. A high-speed clear method is realized by outputting updater.

Furthermore, the above-mentioned high-speed clearing method has a two-way address counter and an address comparator in one row and one column, so that all cell data from an arbitrary row determined by an externally input address to an arbitrary row can be cleared. Do this serially.

The semiconductor memory device of the present invention includes the sense-up and rows,
It is equipped with a minimum of two address counters in the column direction, an address comparator, and a control circuit for controlling these.

(Function) According to the present invention, it is possible to serially clear memory cell data and at the same time output this cleared data to the outside. This is extremely effective especially when the RAM is used as an image memory. That is, when data drawn on a single image data display terminal is cleared at high speed, reading and writing can be performed at the same time, so the time required for this clearing can be halved to 172 times compared to the conventional one. Furthermore, since it has an address counter and an address comparator, it can be used as a memory with a window clear function that quickly clears only a part of the memory area.
We can supply RAM with high added value as image memory.

(Example) FIG. 1 is a block diagram of a DRAM of the present invention.

FIG. 2 is an example of a timing chart of the high-speed clear mode of the present invention. First, the high-speed clear mode setting cycle will be described. The circuit indicated by 9 in FIG. 1 is a high-speed clear mode detector circuit, and the DRAM control signal from the central processing
, CAS, WE and address signal (AO”AN
). For example, CAS b as shown in Figure 2.
A logical combination of addresses where efne RAS DEKATSUWE="Low" (in the figure, the lowest address Ao=
"High", highest address AN="High"), the detector circuit is activated and the 1-wire mode is set.When the 6-wire mode is set, the detector circuit is activated as shown in Figure 1. Activate the column address counter shown at 8 in the same way as the row address counter shown at 7,
At the same time that the counter output is input to the row decoder and column decoder shown at 3.degree. 4 in the figure, the detector circuit also functions to latch the state in the sense amplifier.

- In general, Dout and the cell logic level are different, but the logic level of the cell data line (hereinafter referred to as BL) is the same.

Therefore, in the high-speed clear mode setting cycle, the sense amplifier is configured to latch the information that the BL side is 'High' and the ■ side is 'Low' of the BL pair input to the sense amplifier according to the logic of Dout and the scrambler of Data. This is the setting cycle.

Next, the operation of the clear mode cycle will be described. In the first cycle following the clear mode setting cycle, when an address (start address) is given from the outside, the row address counter is set to the state of that address.
This counter address is input to the row decoder, thereby selecting one word line. On the other hand, a state in which all addresses are at a low level is inputted to the column decoder from the column address counter. This results in 1
After the column selection line of the book is turned on and the clear data is output to the outside, the column address counter is sequentially incremented in accordance with the toggle of the line. In this way, the clear data latched in the sense amplifier can be written to all cells connected to one word line, and this data can be outputted to the outside at the same time. By inputting the output of the highest address counter of a column to the lowest address counter of a row, the next vL is automatically selected when the clear data of all cells connected to one word line is output. .

Thereafter, this operation is repeated in a high-speed clear mode cycle.

Finally, the high-speed clear mode release cycle will be described. To exit the clear mode described above, use the same method as the setting cycle.

That is, DRAM control signals RAS, CAS
The release cycle is determined by controlling the detector circuit 9 in FIG. 1 by the logic combination of %lE and address (AO"AN).
freRAS big WE="Low", Ao="Low"
"e AN = "Low". After the release cycle, all control signals are reset (
(H1gh level) to enter a normal precharge cycle.

This is the high-speed clear mode release cycle.

As mentioned earlier, one of the points of the present invention is to cause the sense amplifier to latch certain information in the high-speed clear mode setting cycle, and a specific example of this will be described. FIG. 3 shows a connection diagram of a specific example of a sense amplifier set circuit and a core circuit for this purpose, and FIG. 4 shows a timing chart of the main clocks shown in FIG. 3. As shown in Fig. 3, the capacity of the dummy cell is equal to that of the memory cell, and 2 Vcc is written from the write-only transistor during precharge.
Many proposals have been made to prevent deterioration of sense sensitivity due to fluctuations in the harge potential. (Furuyava
T,,etal,“An Experimental
4Mb CMO8DRAM' IEEEII! Inte
rnationalSolid-5tate C1rc
uit Confareca, Digest ofT
electrical papers, paper number FAN 1
9.7. Feb. 1986) In this method, this write transistor is used in order not to increase the number of elements in the CoRE circuit. This will be explained in detail using FIGS. 3 and 4.

When entering the high-speed clear mode setting cycle mentioned above, the clock EQL first transitions to a low potential, and the BL and the equal
Cancel ize(-!-Vu). Next, while keeping the dummy cell write signal stone at a high potential, the dummy word @DVLO connected to the eaves is made to transition to a high potential. Further, for example, the input signal 5ASET of the sense amplifier set circuit shown in FIG. 3 is made to transition to a high potential. This results in
The write potential of the dummy cell connected to DVLO is set to on-chip TvC'g by transistor Q□,02.
It is disconnected from the enerator and grounded to a level lower than Vcc) 6. After resetting DuLQ 5ASET to a low potential, the activation signal of the r-cb sense terminal, the top 1 of the active restore circuit is set to a low potential. By transitioning the activation signal Ω1 to a high potential, it is possible to cause the sense amplifier to latch clear data according to the logic of Dout. Note that in order to write the inverted data (i.e., Dout = "H") to all cells, it is easy to do so by connecting the source side of the transistor Q of the sense amplifier set circuit from the ground to the power supply. can be done.

As described above, the high-speed clear mode according to the present invention can be exited from the clear mode at any time by a clear mode release cycle, but it also has an address comparator shown at 10 in FIG. It is also possible to automatically exit the high-speed clear mode simply by applying a stop address externally. That is, as shown in FIG. 1, the stop address input from Ao=AH is input to the address comparator shown at 10, and on the other hand, the counter address from the row address counter is also input to the address comparator. When these two addresses become equal, the address comparator sends a signal to the high-speed clear mode detector circuit 9 to automatically exit this mode. If this method is used, the externally input start address ( As a result, it is possible to serially clear the row determined by setting the address counter (setting the address counter) to the row determined by the stop address. It can be used as a so-called window clearing function that quickly clears only a part of the display screen of a data display terminal.There are various specific configurations of the address comparator, but the simplest method is shown in Figure 5. Indicated. That is,
By taking the exclusive OR of the stop address given from the outside and the counter address of the address counter output, and by taking the Nor logic of these N outputs, the MATCH signal is set when all addresses match. , This makes it possible to realize an address comparator.

Note that the high-speed clear mode setting cycle, release cycle, and clear mode cycle according to this embodiment may be realized by any combination of DRAM control signals, and the sense amplifier set circuit and address comparator may also be implemented using the specific example shown here. It can be changed freely as long as it is further developed and does not deviate from the original purpose of the circuit.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to write clear data latched by a sense amplifier into a memory cell in units of word lines, and at the same time output this clear data serially to the outside.

This is because image data clearing, which was conventionally done by writing clear data to all memory cells and then reading all memory cell data, can be done at the same time with this method. A so-called high-speed clear mode that can be completed in 172 hours can be realized. Furthermore, by having two address counters and an address comparator, it can be developed into a window clear function that quickly clears data from any row to any row according to an externally given address. As described above, the present invention provides a new function not found in conventional DRAMs, thereby making it possible to provide a RAM with high added value as an image memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a DRAM according to the present invention, FIG. 2 is a diagram showing an example of a timing chart of a high-speed clear mode according to the present invention, and FIG. 3 is an example of a sense amplifier set circuit for realizing the present invention. FIG. 4 is a diagram showing the main clock timing chart in the circuit diagram in FIG. 3. FIG. 5 is a diagram showing an example of an address comparator circuit for realizing the window clear function. . In the figure, 1...Memory cell array 2...Sense amplifier, I10 gate 3...Row decoder 4...Column decoder 5...Row address buffer 6...Column address buffer 7... Row address counter 8... Column address counter 9... High speed clear mode detector circuit lO... Address humparator 11... First clock generation circuit 12... Second clock Generation circuit 13...Data out buffer 14...Data in buffer Representative Patent attorney Nori Chika Mitsuyuki Matsuyama Figure 1 Figure 4 Figure Q Direct... (Tz CI Q Figure 5

Claims (4)

[Claims] (1) In a semiconductor memory device in which memory cells of one transistor and one capacitor are arranged in a matrix, the semiconductor has a high-speed clear mode that clears information in the memory cells and simultaneously outputs this cleared data to the outside at high speed. Storage device. (2) The high-speed clear mode includes a high-speed clear mode setting cycle determined by a logic combination of semiconductor memory device control signals from the central processing unit, a release cycle determined by the same method, and an interval between these two cycles. Claim 1 consisting of a clear cycle performed in
The semiconductor storage device described above. (3) The semiconductor memory according to claim 2, wherein the high-speed clear mode setting cycle is performed by latching the sense amplifier to a certain state by controlling the dummy word line, the dummy cell write transistor, and the dummy cell potential generation circuit with a clock. Device. (4) The high-speed clear mode has a row address counter, a column address counter, and an address comparator, so that from the row determined by the externally input start address to the row determined by the stop address 2. The semiconductor memory device according to claim 1, having a window clearing function for serially clearing the window.