JPH01191959A - Cache memory control system - Google Patents

Abstract

PURPOSE:To avoid the replacement of data due to a tentative reading action by storing previous access conditions when a cache mishit is decided at reference to tag information and replacing data on cache entries under a certain condition only. CONSTITUTION:The address relationships between the data stored in a cache memory and data stored in a main memory are defined as the tag information 11 and 13. Then the hit or the mishit is decided by reference to both information 11 and 13 and the replacement of data on the cache memory is performed. The replacement of cache entries is decided based on the next tag information 13 and a read flag 14. Then said replacement is carried out only when coincidence is obtained between the information 13 and a high-order address and the flag 14 is genuine. While the flag 14 is cleared when the replacement of cache entries is carried out. In case the replacement conditions are not satisfied, the high-order address is stored in the information 13 and the flag 14 is set.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a cache memory control method.

(Conventional technology) The methods for controlling cache memory can be roughly divided into the following two types.
It is divided into One is the direct mapping method, and the other is the set alicia tip method. The former is shown in FIG. 2, and the latter is shown in FIG.

In the figure, 21.31 is a main memory, 22.32 is a cache memory, and 23.33 is a directory memory. The directory memory 23.33 contains data stored in the cache memory 22.32 and the main memory 21.31.
Tag information (T
AG) and valid information (VALtD) indicating whether data corresponding to each tag information is valid or not are stored. 24
．． 34 indicates the vlJ buried address money.

In FIG. 2, there is one cache entry for a byte address area in the lower 32.

Which area exists in the cache 7 & entry area can be known by storing the upper address in the tag section. When accessing the cache, the tag part for the valley set of lower addresses (A5 to A14) is compared with the upper address, and only when they match and the valley parid pit is true is a cache hit, and data read/write is performed in the cache memory. It will be held between 22. When there is a miss, access is made to the main memory 2, and the data is also stored in the cache memory 22. In other words, an exchange of memory r and memory has occurred (69), and here the tag part is exchanged and the valid pit is made true.

FIG. 3 shows a 2-way example, and you can think of it as a second direct map. In other words, there are two caches and entries for the lower 16 byte address areas. At the time of cache and access, the two tag parts and the upper address are compared. If either matches, the subsequent operation will be the same as the direct map method. If they do not match, they are replaced, but which puncture to use is determined by a priority determination circuit (usually LRU system).

(Problems to be Solved by the Invention) By the way, the direct map method shown in Fig. 2 has a poor cash hit rate (and the set arithmetic method shown in Fig. 43 has the disadvantage that the circuit is complicated and the cost is high. have

The present invention provides a low-cost and efficient cache memory control method that focuses on cache and data replacement according to the direct mag method.

[Structure of the Invention] (Means for Solving the Problems) The present invention has an address correspondence relationship between data stored in a cache memory and data in a main memory as tag information, and by referring to all of this, In a cache memory control device that judges hit/miss hints and replaces data in a cache memory, the previous access conditions are stored when a cache miss is judged when referring to tag information.

The configuration is such that the cache and entry data are exchanged only under certain conditions, and the hit rate is improved by preventing frequent occurrence of cache and data exchange through temporary data access.

(Function) In the direct map method, when a cache or mishit occurs, a cache or data swap occurs unconditionally, but by adopting the above configuration, swapping is allowed on the condition that there are nine consecutive lead operations. It is something to do. This makes it possible to prevent frequent replacement of caches and entries due to temporary read operations, and to provide a low-cost and efficient cache control device.

(Example) Hereinafter, the following first embodiment of the present invention will be explained in detail.

FIG. 1 is a diagram illustrating an embodiment of the present invention, showing pit fields constituting each binary of a directory memory. In the figure, 11 is a tag part indicating the upper address of the cashier entry, 12 is a valid pit,
Indicates whether the cashier entry is valid or invalid. 13
is the next tag part, which indicates the upper address to enter into the next cache. 14 goes by the lead flag.

Indicates validity/invalidity information for the next cache entry. The above-mentioned IJ to 14 constitute a valley set.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. The operation at the time of caddy-miss determination will be explained as follows. When a cache miss occurs, it is natural to read/write data from/to the main memory, but the first step is to decide whether or not to replace the cache entry at this time.
This is done by looking at the next tag information 13 and read flag 14 shown in the figure.

Replacement is performed only when the netast tag information 13 and the upper address match and the read flag 14 is true. Also, when replacement occurs, the read flag is cleared. If the exchange conditions cannot be met, store the upper address money in the next tag and set the read flag (true for read operation). In other words, the conditions are now met for the next read operation in the same area. The other operations described in section 7 are the same as those of a general carriage and controller, so explanations will be omitted.

Incidentally, the present invention can also be applied to a 7" disk cash system using a similar method.

[Effects of the Invention] As explained above, according to the present invention, it is possible to prevent cache and entry data from being replaced due to temporary read operations, and it is possible to improve the efficiency of the cache system at a low cost.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing an example of the configuration of a cache system using a direct map, @3
The figure shows a cache with set associative, Umemory 7
It is a figure showing an example of composition of a stem. ii, 1s...tag information, JJ...valid bit. 14...Lead flag. Applicant's agent Suzue Takehiko 1r] Figure 2 Figure 3

Claims (1)

[Claims] A cache memory control device that has address correspondence between data stored in the cache memory and data in the main memory as tag information, and makes a hit/miss hit determination by referring to this tag information, thereby making a cache memory determination. A cache memory control method characterized in that when a cache miss is determined when referring to the tag information, the previous access condition is stored and the data in the cache entry is replaced only when a certain condition is met.