JPH01190126A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To make the loop gain constant and to stabilize the loop by using the output of an integration circuit integrating the output current of a phase current conversion circuit to control the output current of the phase current conversion circuit, thereby controlling the gain. CONSTITUTION:A phase current conversion circuit 50 compares a reference signal f0 with a phase of comparison signal fV1 being the result of feeding back an output of a voltage controlled oscillator VCO 4 and outputs a current iA. A gain control circuit 11 uses an integration output of the integration circuit 10 to control the current flowing from the current generating section of the circuit 50, then the output voltage of the circuit 10 controlling the VCO 4 can control the current iA of the circuit 50. Thus, the loop gain is made constant by combining the VCO 4 having the V-f characteristic approximated by the quadratic curve at a negative voltage and a linear line at a positive voltage, and the loop is stabilized.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a phase-locked loop circuit (hereinafter referred to as rPLL circuit), and in particular to an improvement of a PLI-circuit that can easily control the loop gain. Regarding.

<Prior Art> Conventionally, one type of frequency synthesizer uses a PLL circuit. Hereinafter, the conventional technology will be explained based on the drawings.

FIG. 5 is a block diagram showing the configuration of a digital signal generator used to explain a conventional PLL circuit.

In FIG. 5, 1 outputs a signal of frequency f (hereinafter referred to as "
This is a PLL circuit that outputs a signal (output signal). This PLL
The circuit 1 includes a reference oscillator 2 that outputs a reference signal of frequency f0 (hereinafter simply referred to as "reference signal"), a frequency dividing circuit 3 that divides the frequency of the output signal f into 1/N, and outputs the output signal f. Voltage controlled oscillator (hereinafter referred to as rV (, OJ) 4
, the comparison signal fV and the reference signal fed back through the frequency divider circuit 3. It has a loop configuration including a phase comparator 5 that compares the phase with There is.

7 is a fixed oscillator that outputs a signal with frequency f2, 8 is PL
A mixer 9 mixes the output signal f of L1 and the frequency f2 from the fixed oscillator 7, and 9 is a low-pass filter that outputs a low frequency component 2f+ of the output signal of the mixer 8.

In such a configuration, for example, 10
In order to obtain an output frequency of kHz to 100 MHz, the reference signal f0 is set to IOK Hz, and the oscillation frequency range of the VCO 4 is set so that the output signal f is 500 MHz to 599.99 MHz. Set the frequency division ratio of the frequency divider circuit 3. Also, the frequency f2 of the fixed oscillator 7 is set to 600 MHz.

Then, f2 f+ can be adjusted by changing the frequency dividing ratio of the frequency dividing port 3.

By the way, in the conventional PLL circuit 1, for example, VCO4
If the V-f characteristic of the By directly controlling the control voltage of C04 and bringing the output characteristic of 1 closer to a straight line using the output signal, P
The loop gain is controlled to stabilize the phytoback system of the L L circuit 1. Therefore, the gain control circuit 1a represented by the diode broken line approximation circuit shown by the dotted line is
The circuit configuration is provided before F6.

<Problems to be Solved by the Invention> However, in this conventional PLL circuit in which the gain control circuit 1a is provided before the LPF 6, the band of the gain control circuit 1a cannot be made lower than the band of the loop (in other words, Therefore, the noise generated in the gain control circuit 1a is directly transmitted to the VCO 4, and the S of the output signal f is /N (decreases the purity of the output signal f1). Also, ■C04
When the V-/characteristics of the gain control circuit 1a have characteristics that can be approximated by a quadratic curve, it is necessary to configure the gain control circuit 1a to obtain an output that corrects the characteristics that can be approximated by the quadratic curve. However, there is a problem in that it is quite difficult to create such a circuit configuration.

The present invention has been made in view of the problems of the conventional technology, and aims to stabilize the loop by controlling the loop gain without affecting the output signal f1, and An object of the present invention is to provide a PLL circuit that can stabilize the loop gain even when the PLL circuit has a V-f characteristic that can be approximated by .

Means for Solving Problems> A PLL circuit of the present invention for achieving the above object compares the phases of a reference signal and a comparison signal, and sends the compared value to a voltage controlled oscillator via a filter. a phase-locked loop circuit configured to feed back a signal output from the voltage-controlled oscillator as the comparison signal, a phase-current conversion circuit that compares the phases of the reference signal and the comparison signal and outputs a current; An integration circuit that integrates the output current of the phase current conversion circuit, and a gain control circuit that receives the integral output of the integration circuit and controls the output current of the phase current conversion circuit to control its gain. It is characterized by the fact that

<Example> Hereinafter, an example of the present invention will be described in detail based on the drawings. In the following drawings, parts that overlap with those in FIG. 5 are given the same numbers, and explanations thereof will be omitted.

FIG. 1 is a block diagram of a PLL circuit of the present invention, FIG. 2 is a circuit diagram showing a specific example of FIG. 1, and FIGS. 3 and 4 are diagrams for explaining the present invention.

In FIG. 1, 100 is a PLL circuit of the present invention.

In the PLL circuit 100, 50 is a reference signal f. 10 is an integration circuit that integrates the output current iA, and 11 is an input of the integral output of the integration circuit 10 to control the current 1A. This is a gain control circuit that controls the gain of the phase current conversion circuit 50.

In FIG. 2, the phase current conversion circuit 50 converts the reference signal f
0 and the comparison signal fv are input and compared with 9 using the reference signal, and if the phase of the comparison signal fat is early, the output terminal outputs a signal (advanced phase detection signal) Sd that drops the output signal. On the other hand, when the phase of the comparison signal fVI is slow, the output signal f is output from D.

A phase discrimination circuit 50a that outputs a signal (delayed phase detection signal) Su from output terminals U and tJ, and a resistor, a capacitor, etc. that outputs a current l + + i2, respectively.
Current generating section 50b consisting of a diode, a transistor, etc.
, , 50b2, and the current generating section 50bj.

50b2 are connected to each of the input terminals corresponding to the fixed terminals to supply the current t++i2, and the output terminals corresponding to the other fixed terminal are respectively connected at the connection point α to detect the leading phase from the phase discrimination circuit 50a. Either one is turned on/off based on the detection signal Sd or the delayed phase detection signal Su, and the current i1. It consists of a pair of switch sections 50c1 and 50c2, each having a differential amplifier circuit configuration, for example, which converts i2 into a pulse and outputs it from a connection point α as a current lA based on the phase comparison between reference signal 9 and comparison signal fat.

The gain control circuit 11 includes, for example, transistors Tr, ~T
r3. For example, the resistance value of R1 is 100Ω, R2 and R
5 is 100 Ω, R3 is 5.6 Ω, a resistor 9, for example, a reactance Ll of 270 μH, R2, a filter 11a consisting of a resistor R6 and a capacitor C2, a filter 11b consisting of a resistor R4 and a capacitor C1, Current generators 50b and 50b2 are connected to both ends, and one current flowing from the current generators 50b+ and 50b2 is controlled by the integral output of an integrating circuit 10 consisting of a resistor R7 and a capacitor C, resulting in a phase current conversion circuit. It consists of a configuration that controls a current output iA of 50.

At this time, an integral output (VCO4
becomes the control voltage. (hereinafter referred to as "control voltage") is V, and the voltage obtained at the connection point γ between the resistor R7 and the capacitor C1 of the integrating circuit 10 is V2. This voltage v2 is supplied to the transistor Tr of the gain control circuit 11.

In addition, in Figure 1, ■+ is +15V and V- is -15V.
shall be.

In addition, when the voltage (2) is 07 or more, the emitter potential of the Tr (assumed to be V3) is a high potential (for example, -1°4V or more).
Next to Tr2. Since Tr3 is in the off state, no current i3 flows from the current generators 50b+ and 50b2 to the gain control circuit 11, so that the current 1. The value of is (Rs/R1o) times the current 14 flowing from the connection point ζb1 between the cathode of the diode Db+ in the current generating section 50b and the resistor R[I to the ground via the resistor R8. Similarly,
The value of current 12 is determined from the ground in current generating section 50b2 via resistor R11 and diode Db2.
(R+
2/R+3) times.

In the circuit configured in this way, when the voltage v2 becomes 0■ or less, the transistor Tr of the gain control circuit 11,
Since the emitter potential v3 of becomes a low potential (for example, about -1.4V or less), Tr2 and Tr3 are turned on and the current iz
There is an inflow of As a result, the potential at the connection point ζb1 of the current generating section 50bl (assumed to be Va) decreases, and the potential at the connection point ζb2 of the current generating section 50b2 (assumed to be V5) increases, so that the current i1+12 increases. . If the current flowing to the ground via the resistor R8 when the voltage ■2 is 07 or more is i4°, and the current flowing from the ground via the resistor Ftz is i5°, the value of the current i1 is i1= (Rs
/R1o) ・[14. + (Ra/(Re 1Rs)) ・
is], and the value of current i2 is: i2= (Rt 2 /R+ 3 )・Ci5°+(R
++/(R+, +R+z)l ・13]. If the emitter voltage of transistor T r 2 is V6 and the emitter voltage of transistor T r 3 is 7, then "V2=
The relationship “V, −V,” is established.By the way, this “V8
V? = i 3 X R3”, so “is
= (V2) /R3” Tonal.

Therefore, 11= (Rs /RT o > [i4o + IRa
/ (Re +Rg))・・+ (−V2) /R3) ], and i2= (R+ 2 /R+ 3) ・[i50
+ (R+ 1/ (R+ 1+R+ 2))・(
(V2)/R31 from 0 or more, the relationship between ■2 and 1.1a is expressed as a characteristic diagram as shown in FIG. In other words, the third
The figure means that the current IA can be controlled by the control voltage . Therefore, the phase current conversion circuit 50. having the characteristics as shown in FIG. When a VCO 4 having a V-/characteristic that can be approximated by a straight line at positive voltage and a quadratic curve at negative voltage as shown in FIG. 4 is combined with the circuit consisting of the integrating circuit 10 and the gain control circuit 11, the loop gain can be approximately reduced. Since it can be made constant, the loop can be stabilized.

According to such a circuit configuration, the response of the gain control circuit 11 and the response of the loop can be considered independently.

Therefore, the response of the gain control circuit 11 may be sufficiently slow, so the time constants of the filters 11a and 11b are set to large values (
For example, set the resistance values of resistors R4 and R6 to 2Ω.

By setting the capacitance of the capacitors C1 and C2 to 0.1 μF), the influence on the current generating sections 50b+ and 50b2 can be suppressed.

Note that the present invention is not limited in application to the circuit configuration shown in FIG. The present invention can be applied even to a circuit configuration in which the CO output is directly used as a comparison signal without providing a frequency circuit or a frequency conversion circuit.

<Effects of the Invention> As described above, the present invention has been specifically explained along with the examples.
According to the PLL circuit of the present invention, the band of the gain control circuit can be sufficiently lowered with a relatively simple configuration, so that deterioration of the purity of the vCO output signal due to noise generated in the gain control circuit can be prevented. I can do it. This also allows noise countermeasures to be relatively relaxed in designing the gain control circuit. Furthermore, even in a PLL circuit using a VCO with a V-/characteristic that can be approximated by a quadratic curve, it has a great practical effect, such as 0, which allows you to easily stabilize the loop gain by making it constant. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the PLL circuit of the present invention, FIG. 2 is a circuit diagram showing a specific example of FIG. 1, FIGS. 3 and 4 are diagrams for explaining the present invention, and FIG. 1 is a block diagram showing the configuration of a digital signal generator used to explain a conventional PLL circuit. FIG. 1, 100...Phase-locked loop circuit (PLL circuit)
, 2... Reference oscillator, 4... Voltage controlled oscillator (VC
O>, 3... Frequency divider circuit, 5... Phase comparator, 6...
・Low pass filter (LPF), 10...integrator circuit,
11... Gain control circuit, 50... Phase current conversion circuit. Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] In the phase locked loop circuit configured to compare the phases of a reference signal and a comparison signal, guide the compared value to a voltage controlled oscillator via a filter, and feed back an output signal of the voltage controlled oscillator as the comparison signal, a phase current conversion circuit that compares the phases of the reference signal and the comparison signal and outputs a current; an integration circuit that integrates the output current of the phase current conversion circuit; A phase-locked loop circuit comprising: a gain control circuit that controls the output current of a current conversion circuit to control its gain.