JPH01189073A - Recording and reproducing of digital signal and reproducing device - Google Patents

Abstract

PURPOSE:To perform the recording and reproducing of a digital signal without trouble by constituting a PLL circuit so as to equalize an accumulated value of the number of recording samples from a regenerative signal with an accumulated value of a sampling clocks for reproducing at the time of reproducing. CONSTITUTION:An external clock from an input terminal 48 at the time of recording an external digital input, and an output signal of a VCO 57 at the time of reproducing are selected by a selector 47 respectively. At the time of reproducing, a counting circuit 50 is supplied with a word number detecting signal from a terminal 86. This word number detecting signal is formed of a discriminating signal in data under reproducing, corresponding to the recorded word number. And, a counting circuit 49 is supplied with the output signal of the VCO 57 as selected by the selector 47. The output signals of these circuits 49 and 50 are supplied via dividing circuits 53 and 54 respectively to a phase comparating circuit 55, where their phases are compared. Since an output signal of this circuit 55 is supplied to the VCO 57, the sampling clock generated from the VCO 57 becomes the same as at the time of recording.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital signal recording and reproducing device that is applied to, for example, recording an audio PCM signal on a magnetic tape using a rotating head and reproducing it from the magnetic tape. Regarding.

(Summary of the Invention) In the present invention, in a digital signal recording/reproducing device where the sampling frequency of a digital information signal to be recorded and the frequency of an internal recording reference signal are not an integer ratio, during recording, the number of samples of data to be recorded is The number of recording samples is selected so that the integrated value is equal to the integrated value of the number of samples of the human-powered digital signal, and an identification signal indicating the number of recorded samples is recorded, and during playback, the number of recorded samples obtained from the reproduced signal is By configuring the PLL circuit so that the integrated value of is equal to the integrated value of the sampling clock for reproduction, it is possible to record and reproduce digital signals without any trouble.

[Conventional technology]

For information symbols in a matrix-like two-dimensional array,
An error correction encoding device is known that performs error detection and encoding of an error correction code, such as a Lyde Solomon code, in both the vertical and horizontal directions. This code is transmitted column by column in the vertical direction, and on the receiving side, the first error detection and error correction code is used to correct the error and form a pointer indicating the presence or absence of an error. A second error detection and error correction code is adapted to correct the error.

When transmitting the above-mentioned error correction encoded data column by column, a synchronization signal and sub-data such as a block address are added to form one block of data. For example, in Japanese Patent Application Laid-Open No. 59-202750, for data for each column and parity data of the first error correction code,
It is shown that one block is formed by adding a synchronization signal and an address whose error can be detected independently using a CRC code. In the above-mentioned document, as shown in FIG. 14A, errors can be detected using CRC for addresses, and a first error correction code (CI) is used for data and [PCM audio signals]. (referred to as a C2 code) and a second error correction code (referred to as a C2 code).

In the case of the encoding shown in FIG. 14, since the C1 code is not applied to the at 17th, the protection against errors is only for net.

In order to solve the second problem, for example,
As described in Japanese Patent No. 77 and shown in FIG. 14B, error correction encoding in which C1 code is encoded also for addresses has been considered.

The error correction encoding shown in FIG. 14 is useful when the header consists only of addresses.

However, when a PCM audio signal (main data) is included in the header in addition to the address, the main data is encoded with only C1 code (71 code), resulting in a lack of protection against errors. There is. Encoding the entire ladder with C2 code, including the address, is
Due to 2 parity, the y-- area where addresses are recorded is lost (this is convenient).

, In order to solve such a problem, convert the entire He/Rada to 01 code i4 along with the data part, and also convert the main data that is not included in the Ladder except for the at 1/s. The encoding of the 02 code for each line can be made stronger by overlapping the header's data, 'U,,'
I made it possible to put the main data in 31bars and 1 by 3...-Pel', +, t:,,', 7'
T'-'j; The device σ has been designed in the first volume of this book. This error correction encoding device encodes a video signal for one field and an audio P for one field.
The so-called 8mm V, which records a CM signal and a time-axis compressed audio PCM signal on a magnetic tape in one scan.
Suitable for use in TR.

The 8mm VTR that is already in practical use is Audio P.
The sampling frequency of the CM signal was selected to be 2fh (fh: horizontal frequency). Therefore, the rotating head that rotates at the frame frequency and the sampling system are synchronized, and the problem of synchronization between images and audio does not occur. However, the sampling frequency of conventional 8mm VTRs is too low in terms of recording and reproducing high-quality audio signals, and the sampling frequency (44.1kHz) used in other digital audio equipment is too low.
z.

There was a problem that there was no consistency with 48kl (z, 32 kHz, etc.). Therefore, the sampling frequencies of the audio PCM signal at 8 mm V i″R are these frequencies (44, 1 kllz, 48 kllz, 32
kHz, etc.) is preferably used.

[Problem that the invention seeks to solve]

However, since the above-mentioned frequency is not in an integer ratio relationship with the field frequency (59, 94 Hz) of the NTSC system, which is a recording reference signal, the number of sample data included in one field period is not an integer number. In particular, when recording audio PCM signals from an external source, processing during recording and processing during playback pose problems. In other words, during playback, it is necessary to reproduce relationships that do not exist in the integer ratio during recording.

If the ratio between the frequency of the recording reference signal and the sampling frequency is different from that at the time of recording, a problem arises in which audio data is insufficient or surplus at the time of reproduction.

Therefore, an object of the present invention is to provide a digital signal recording and reproducing apparatus that can record and reproduce without any trouble even when the sampling frequency is not divisible by the frequency of the recording reference signal, for example, the field frequency. .

[Means for solving problems]

In this invention, in a digital signal recording/reproducing device where the sampling frequency of a digital information signal to be recorded and the frequency of an internal recording reference signal are not in an integer ratio, 2. A circuit that generates data of a plurality of integer values close to the quotient G obtained by dividing by an integer multiple of frequency, a first integration circuit to which data of a plurality of integer values is selectively supplied, and digital information. (2. The number of recording samples is selected so that the output of the first integration circuit and the output of the second integration circuit are equal to the second integration circuit that integrates the number of samples of the IN number, and A circuit that records an identification signal indicating (-5 during playback δ, ゛, again) 4. The recording lean pull number obtained from the 1st c) At the same time, a circuit that supplies the output signal of 1P I-1- to a second integration circuit compares the phases of the output of the first integration circuit and the output of the second integration circuit, and sends the comparison output to the VCO of the PLL. A circuit for supplying a control signal to the control signal is provided.

Further, in the present invention, the sampling frequency of the digital information signal to be recorded and the frequency of the internal recording reference signal are not an integer ratio, and the identification signal indicating the number of recording samples per one or more cycles of the recording reference signal is recorded. The number of recording samples obtained from the reproduced signal is supplied to the first integration circuit in the digital number recording device that reproduces the recorded recording medium, and the output signal of
The circuit that supplies the fi calculation circuit compares the phases of the output of the first integration circuit and the output of the second integration circuit, and outputs the comparison output as P.
A circuit 1''- for supplying control No. 43 and 1-4 to the VCO of f, f, , is shown.

1 [Function] A header consisting of a block address, an ID signal, and data, and a data block consisting only of main data.
A block is formed. An audio PCM signal is recorded in units of two-dimensional arrays of symbols in which a plurality of blocks are arranged. This two-dimensional array contains audio PC
Contains data for one field of the M signal. The error correction coded data for one field per field is time-base compressed and recorded on a magnetic tape.

In the case of the NTS C system, the field frequency is 59
．． 94 Hz, sampling frequency is 48kHz
In this case, the sampling frequency is not divisible by the field frequency. In other words, (48000+59.94″=
It will be $800.8). Samples (words) of the audio PCM signal to be recorded, such as 800 and 801, are set as integers of 2 or more close to this quotient.
The accumulated value is compared with the accumulated value of the selected one of the above-mentioned numerical values at the field period. When the cumulative value of the number of samples is greater than the cumulative value of the set value, 801
is selected, and conversely, when the integrated value of the number of samples is smaller than the integrated value of the set numerical value, 800 is selected. The selected number of samples is recorded as data for one field.

At the same time, an identification signal indicating the number of numbers is recorded. Therefore, even if the number of samples for one field is an integer, on average, the number of samples close to the above-mentioned quotient will be recorded each time, and it is possible to prevent synchronization between video and audio from occurring. Can be done.

Also, during playback, the identification signal extracted from the playback signal is integrated, and this integrated value is phase-compared with the integrated value of the sampling clock formed by i) L L, and the comparison output is P L l, ■00 is supplied to

Therefore, the same relationship between the recording reference signal and the sampling clock as during recording is maintained during reproduction, and the digital signal is reproduced without any problem.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This description is given in the following order.

a. Block configuration and frame configuration, example of data interleaving C, header configuration example d, recording and reproducing circuit e, clock generation circuit f, modification a. block configuration and frame configuration. The structure of one flock of data is shown below. l block consists of 49 symbols,
One symbol block same 1tJJ signal is located at the beginning,
Next, a 4-symbol header is located, followed by a 44-symbol data section.

As described later, the header includes an ID signal, data or C2 parity, block address ADR, simple parity for these, CI? It consists of an error detection code such as EDC. The data portion consists of data (audio PCM signal) or C2 parity, or data or C2 parity and CI parity.

As shown in FIG. 2, 1 frame is constructed by arranging 100 rows of the above-mentioned blocks. Intra-block addresses (0 to 47) are assigned to the 48 symbols in the vertical direction excluding the block synchronization signal in this matrix-like frame structure, and block addresses (0 to 99) are assigned to the 100 blocks in the horizontal direction. be done.

Block address (20-99) and intra-block address (4-47) (44 symbols x 80 blocks)
includes the ODI PCM signal and C1 parity. As will be described later, one scan of the rotating head allows
Since the video signal and the time-base compressed audio PCM signal are recorded on the magnetic tape, the amount of information of the audio PCM signal is included in the 1-field period. N
The PCM audio signal for one field in the TSC method is as follows when the sampling frequency is 48 kHz. As is clear from this equation, the sampling frequency is not divisible by the field frequency.

In order to solve this problem, in the frame configuration shown in FIG. 2, cases in which the number of recorded words is both 800 words and 801 words are mixed. However, in the following explanation of the code structure, the number of words is assumed to be 801 words.

When performing 16-bit linear quantization, each word is divided into upper 8 bits and lower 8 bits, and one symbol has 8 bits. Furthermore, when the ■ word is 12 bits, the ■ symbol is 6 bits. The sampling frequency may be 44.1kllz or 32kHz in addition to 48k)I2.

The upper symbols LOU and ROU of the first words LO and RO of the left channel and right channel two-channel audio PCM signals (LO-LaO2, RO to R800) are the intra-block address 1, and the block addresses 97 and 99. It is located in Also, the symbols LOε and ROP on the lower side are the intra-block address 3,
They are located at block addresses 97 and 99. Of the remaining 800 words, 800 symbols of odd-numbered words are placed at block addresses (20-59), and 800 symbols of even-numbered words are placed at block addresses (60-99).

The parity (C
2 parity).

The C2 code is a (25°20) Reed-Solomon code formed for 20 symbols in every four blocks of horizontally aligned symbols. Four C2 code sequences are generated for one row, so one row has (4X5
= 20 symbols) 02 parity is included. Therefore,
Block address (20-99) and intra-block address (4-47) (44 symbols x 80 blocks)
All symbols are encoded with CI code and C2 code.

Intra-block address O and block address (0~
99) includes an error detection code EDC for the header. For this error detection code EDC, C
2 code is not encoded.

1 of the address within the block and (20 of the block address)
to 99), the ID signal IDu or data Lou, RO
u is included, and the C2 parity formed from this data (
5X2=1O symbol) is 1 in the block address and (1, 3, 5, 7...17.1) in the block address
Included in 9). The ID signal IDf is included in the intra-block address 1 and the block address (0, 2, 4, 6...16.18).

2 of the address within the block and (0 to 0 of the block address)
99) includes the address ADH. Block address A I) R is not encoded with the C2 code.

3 of address within block and (20 of block address)
~99), the ID signal IDff1 or data LOj!
, Roe, and the C2 parity (5X2=10 symbols) formed from this data is the intra-block address 3 and the block address (1, 3, 5, 7...1).
7.19). Intra-block address 3 and block address (0, 2, 4, 6...16.18
) includes the TD signal l111.

Encoding with the C1 code is performed on all blocks (100 blocks). The C1 code is a (48,44) Reed-Solomon code. This C1 code sequence is made to span two adjacent blocks. That is, one C1 sequence is formed by the even-numbered symbols of the symbol sequences of two adjacent blocks, and another C1 sequence is formed by the odd-numbered symbols. Forming a CI sequence across two blocks in this way prevents two symbols in one 01 sequence from becoming errors due to an error occurring at the boundary between two consecutive symbols during recording. This is to prevent this. The 01 parity (8 symbols) of two adjacent blocks is
Intra-block address of odd-numbered block address (4
0 to 47).

During recording, 02 parity is formed from the data and the ID signal, and then C1 parity is formed from these data. During reproduction, error detection and/or error correction is performed using the C1 code, a pointer is set for a symbol that cannot be error corrected, and error detection and error correction of the C2 code is performed with reference to this pointer. Furthermore, during playback, an error detection code 1) C is used to detect errors in the header.

The generation of the C2 code will be explained again with reference to FIG. As shown in Figure 3, the address within the block (0,
1,...47) is represented as P, and the block address (
0, l, ...99) is expressed as k. (ffi-
0) and (ffi=2), the C2 code is not encoded. (f=1), only the C2 sequence including data Lou and ROU is formed. (f=3), data L Of and ROI! , only the C2 sequence containing , is formed. In (P-4 to P-41), a C2 sequence is formed for all data.

b. Example of data interleaving FIGS. 4 and 5 show interleaving of data of 801 words (=1602 symbols) for one field in the NTS C system. Figure 4A shows the data structure of block addresses (0 to 59), Figure 4B shows block addresses (60 to 99), and Figure 5 shows block addresses 20 and 21 in detail. Shown below.

As mentioned above, at block addresses 97 and 99, and intra-block addresses 1 and 3, there are four symbols of 2 words (LOu, LOffi, ROU.

The ROI is located at block address (20-59)
is the odd numbered word (Ll~L799°R1-R7
99), and the block addresses (60 to 99) contain even numbered words (L2 to I, 800, R2 to R
800) are arranged. By separating the recording positions of odd-numbered words and even-numbered words, consecutive words are prevented from becoming error words.

To explain interleaving of symbols in odd-numbered words as an example, data is sequentially arranged starting from addresses 4 and 6 within a block, as shown in FIGS. 4A and 5. In this case, the upper symbols (Llu, , Rlu, L3u
, R3u ・--R19U) as the address 4 in the block.
even block address (20, 22, 24, 2
6...58) I Arrange in this order, and the upper symbols (L,
lLl? 1, e, l, : 12, 1 n 3f -- R19f
) are sequentially allocated to even-numbered block addresses (20, 22, 24, 26, . . . 58) of address 6 in the block. The next odd numbered symbol is the address 5 in the block.
and 7 will be awarded two prizes as above. When the data arrangement is repeated in this way, tB99u and R7 are placed at addresses 37 and 39 in the block of block address 51).
99f! , will be located.

Further, in FIG. 5, POO~I)13 indicates Cl parity regarding two blocks of block addresses 20 and 21. That is, block addresses 20 and 21
In the two blocks, the parity of the Reed-Solomon code (C1 code) of (40,44) from the 48 symbols located at the even-numbered addresses in the block))00.
POl, PO2, PO3 are formed, and (48
, 44) parity IJO, pH of the Reed-Solomon code (C1' code).

R12 and R13 are formed.

Similarly to the odd-numbered words, as shown in FIG.
Even-numbered words are aligned. block address 9
9, the symbols R800u and l-R8 of the last word of the R channel are stored in blocks 37 and 39.
00ρ is placed. According to the interleaving shown in FIGS. 4 and 5, the recording positions of adjacent words in each of the even-numbered word series and the odd-numbered word series of each channel are separated by 4 blocks, and This prevents the higher-order symbols and lower-order symbols from being recorded consecutively, reducing the influence of burst errors.

C. Example of header configuration FIG. 6A shows the header portion of one block.

The header consists of two symbol ID signals IDu and l I)2
, a one-symbol block address ADR, and a parity, for example, simple parity, of these three-symbol error detection code (EDC). This error detection code is also used to detect block synchronization signals. Figure 6B is 1
3 symbols IDu and IDj when the symbol is 6 bits
2. Each information of AI)R is shown. In addition, FIG. 6C shows a 3-symbol IDu when one symbol is 8 bits.
, IDf, and ADR.

The least significant bit of block address ADH is “0”, that is,
In even-numbered blocks, 6 bits of ADR and IDI!
The lower two bits of , a total of 8 bits, indicate the block address. The upper 4 bits of IDff1 are used as a frame address. The frame address is used to identify frames during high-speed playback when a rotating head scans across multiple tracks. The lower three bits of IDu are used as a track address. The track address is used to identify channels when one track is divided into six channels. The upper three bits of IDu are used as an ID signal. This Il) signal can be used as a cue signal, time code, etc.

If the least significant bit of the block address ADH is "1", that is, the odd numbered block address is 6 of ADR.
Bits are used as block addresses.

With 6 bits, the number of bits is insufficient to express a block address, but the correct block address can be restored by interpolation using the block addresses of the previous and subsequent blocks. I l') u is used as the upper symbol of the ID signal or data (L Ou and R Ou in this embodiment).

+1]2 is used as the lower symbol of the [I) signal or data (in this example, L Offi and ROI!,). The LD signal is a cue signal, time code, etc.

An ID code for identifying the number of words included in the frame structure of the code is inserted as the above-mentioned ID signal. In this example, the frame structure contains 800 words or 801 words.
Since the words are included, a 10 code is used to distinguish between the two.

The structure of the header when the l symbol is 8 bits is shown in Figure 6C.
is shown. The least significant bit of the block address is “
0'' block, 8 bits A1, )R are used as the block address, IDf is used as the track address (3 bits) and frame address (5 bits), and IDu is assigned to the ID signal.The lowest block address In a block where the bit is “1”, 8-bit ADR is used as the block address, and IDu and IDff1
are assigned to [D signals or data.

Regardless of whether the l symbol is 6 bits or 8 bits,
A block whose least significant bit of the block address is “0” does not contain any data. Therefore, as mentioned above, the symbol of the block whose least significant bit of the block address in the header is “0” is C2 encoded. C2 parity prevents block addresses, frame addresses, and track addresses from being lost.

The present invention is applicable not only to the recording of NTSC video signals and accompanying audio signals, but also to the recording of CCIR video signals and accompanying audio signals. In the CCI R method, the field frequency is 50Hz, so when the sampling frequency is 48kllz, the data for one field is 9
60 words ([70~L, 959.RO~R959).

FIG. 7 shows a frame structure when the present invention is applied to the CCIR system, in which 48 symbols are arranged in the vertical direction, excluding the block synchronization signal, and 116 blocks are arranged in the horizontal direction. Part of the header includes symbols for the first words LO and RO.

This data is encoded with C2 code. Interleaving of even and odd words, C1
The encoding of the code and the encoding of the C2 code are the same as in the case of the NTSC system.

d. Recording/reproducing circuit FIG. 8 shows an example of a recording/reproducing circuit of a zero-speed head type VTR to which the present invention can be applied.

This VTR records video signals and commercial audio signals on a magnetic tape in one scan.

In No. 8, 25A and 25B indicate a pair of rotating heads, and the rotating heads 25A and 25B are 18 mm apart from each other.
The frame frequency fF (in the case of NTSC system, 29
．． At the same time, the magnetic tape 31 is rotated at a constant speed of 97 MHz, and the magnetic tape 31 is run diagonally at a constant speed over an angular range of 180' or more with respect to the rotating peripheral surface. In this case, the rotating head 2
The rotational phases of 5A and 25B are controlled during recording so as to be synchronized with the recorded video signal, and during playback,
Servo-controlled to scan the l-rack correctly.

Therefore, as shown in FIG. 9A, during every other field period Ta, the rotary head 25A scans the video section of the track, and approximately (115) field periods before the period Ta, the rotary head 25A scans the video section of the track. scan the PCM section.

In addition, in every other field period Tb, the rotary head 25B scans the video section of the trunk, and
The PCM section before the video section is scanned for about (115) field periods before the period Tb.

When recording a video signal, the color video signal SC and the monaural audio signal Sm are supplied to the video recording processing circuit 21, and frequency multiplexing of the FM luminance signal, the low frequency converted carrier color signal, the FM audio signal, and the pilot signal is performed. The signal Sf is continuously taken out as shown in FIG. 9B, and this signal Sf is supplied to the switch circuit 22.

A pulse generating means 34 is provided on the rotating shaft 32, and a frame indicating the rotational phase of the rotating heads 25A and 25f3 is provided.
The pulse pg is extracted and supplied to the signal forming circuit 36 via the shaping amplifier 35. From this signal forming circuit 36, as shown in FIG.
A pulse signal SW is formed which is inverted every time a and 'I'b. This pulse signal SW is supplied to the switch circuit 22 as a control signal, and the switch circuit 22 controls the period 1'a and Tb.
The state can be switched between the illustrated state and the opposite state.

Therefore, the signal Sf is alternately taken out from the switch circuit 22 during periods ]'a and 'rb, as shown in Figure 9.

The frequency multiplexed signal Sf passes through recording amplifiers 23A and 23B, and is further supplied to recording side terminals R of switch circuits 24A and 24B.
It is supplied to the rotating heads 25A, 25B through. Therefore, the magnetic tape 31 receives the signal Sf every period Ta, Tb.
are recorded sequentially as video sections.

Furthermore, the stereo audio signal R is supplied to the PCM recording processing circuit 29. Signal SW is pulse forming circuit 37
As shown in FIG. 9E, the rotary heads 25A and 25)3 each move to
Pulse Ps that becomes “1” during the scanning period of the CM section
is formed. This pulse Ps is the PCM recording processing circuit 2.
9, FIG. 9 I? As shown in (1), the field period bone signal R is compressed on the time axis during the period (Ps - “1#) and converted into a PCM signal.Furthermore, it is digitally modulated and extracted as a PCM signal Ss. .

During the field period Ta, this signal Ss is transmitted from [switch circuit 22 → amplifier 23B → terminal R of switch circuit 24B]
The signal is supplied to the rotary head 25B via the signal path. During the period TI), the signal is supplied to the rotary head 25A via the signal path [switch circuit 22→amplifier 23A→terminal R of switch circuit 24A]. Therefore, on the track, the signal Ss is recorded in the PCM section before the signal Sf is recorded in the video section.

On the other hand, during reproduction, the signals SS and Sf are alternately reproduced from the tracks of the magnetic tape 31 by the rotary heads 25A and 25B. The reproduced signals Ss and Sf pass through the reproduction side terminals P of the switch circuits 24A and 24B, and are then sent to the reproduction amplifier 26A.

The signal is supplied to the switch circuit 27 through 26B.

The signal SW is supplied as a control signal to the switch circuit 27, and the signal Sf is continuously taken out from the switch circuit 27, and the signal Ss is taken out every field period.

The signal Sf from the switch circuit 27 is supplied to the video reproduction processing circuit 28, and the original color video signal Sc and monaural audio signal Sm are taken out from the video reproduction processing circuit 28. The signal Ss from the switch circuit 27 is PCM
At the same time, the pulse Ps is supplied to the PCM reproduction processing circuit 30 as a window signal, and the original stereo audio signal R is extracted from the signal Ss.

e. Clock Generation Circuit The clock generation circuit of the above-mentioned rotary head type VTR will be explained with reference to FIG. In Figure 10,
1 indicates a rotating drum, and the rotating drum 1 rotates rotating magnetic healds 25A and 25B at a frequency of the plate. Further, although not shown, a magnetic tape 31 is obliquely wound around the circumferential surface of the rotating drum 10. 2 indicates a capstan for feeding the magnetic tape 31 at a constant speed.

The rotating drum 1 and capstan 2 are controlled by a servo circuit 3. For the servo, a detection signal indicating the rotational phase of the rotating drum 1 and a detection signal indicating the rotational frequency of the capstan 2 are supplied to the servo circuit 3. In addition, the ATF (automatic track following) signal separated from the playback signal is
TI'' circuit 4, and then to a servo circuit 3 for tracking control.

5 indicates a video processing circuit. This video processing circuit 5 is a circuit corresponding to the video recording processing circuit 21 and the video reproduction processing circuit 28 in FIG. 6 indicates a digital modulation/digital demodulation circuit 9 This digital modulation/digital demodulation circuit 6 is coupled to a system bus 7. Reference numeral 8 surrounded by a broken line is an A/D and [)/A interface coupled to the system bus 7. The A/D and D/A interface 8 includes an A/D converter 9, a digital input circuit 10, a D/A converter 11, and a digital output circuit 12.

An analog audio signal from the input terminal 13 is converted into a PCM signal by the A/D converter 9 and supplied to the system bus 7. An external audio PCM signal is supplied from the input terminal 14 to the system bus 7 via the digital input circuit 10 .

A PCM signal from the system bus 7 is taken out via the D/A converter 11 to the output terminal 15 as an analog output. A PCM signal from the system bus 7 is taken out as a digital output to an output terminal 16 via a digital output circuit 12.

17 indicates a RAM for storing digital data. Data is exchanged between the RAM 17 and the system bus 7. 18 indicates an encoder/decoder;
In one day of this encoder/decoder, the above-mentioned error correction code encoding and error correction processing are performed. 1
Reference numeral 9 denotes an address generation circuit that generates an address for the RAM 17. 20 is a control circuit for controlling signal processing.

The video processing circuit 5 is supplied with an external synchronization signal from a terminal 41 and an output signal from a frequency dividing circuit 42 as timing signals. The frequency dividing circuit 42 divides the frequency of the output signal of the crystal oscillator 43. These external synchronization signals and frequency dividing circuit 42
The output signal is supplied to the servo circuit 3 as a servo reference signal via the recording/reproduction changeover switch 44. The frequency of the servo reference signal is the frame frequency f F (29,971 (z) in the case of the NTSC system. During recording, an external synchronization signal is used as the servo reference signal, and during playback, the output signal of the frequency dividing circuit 42 is used as the servo reference signal. is used as the servo reference signal.

The frame frequency signal selected by the recording/playback switch 44 is output to the PLL 45 and the digital comparison circuit 46.
is supplied to The PLL 45 forms an internal sampling clock during recording, as will be described later. This PLL45
The output signal of
It is kHz. The output signal of the PLL 45 is sent to the A/D converter 9.
and is also supplied to the selector 47.

The selector 47 selects a sampling clock and is controlled by the control circuit 20. When recording an external analog input, the output signal (internal sampling clock) of the PLL 45 is selected by the selector 47, when recording an external digital input, the external clock from the input terminal 48 is selected, and during playback, the output signal of the VCO 57 is selected. is selected. A sampling clock generated by PLL 45 is supplied to A/D converter 9. The external clock is supplied to the digital input circuit 1o.

The reproduction sampling clock generated by the VC057 is supplied to the I/A converter 11 and the digital output circuit 12. The control signal for the selector 47 of the control circuit 20 is also supplied to the A/D and D/A interface 8.

The sampling clock selected by the selector 47 is supplied to the integration circuit 49. The integration circuit 49 is composed of a counter, and the output signal of the integration circuit 49 is supplied to the digital comparison circuit 46 via the recording side terminal r of the recording/reproduction changeover switch 51.

The output of the integration circuit 50 is supplied to the digital comparison circuit 46 via the recording side terminal r of the recording/reproduction changeover switch 52. The output of the digital comparison circuit 46 is supplied to the control circuit 20 as a word number selection signal, and is also supplied to the integration circuit 50. The number of words included in one frame of the code structure is controlled to 800 words and 801 words by the word number selection signal. When the number of words included in one frame of the code structure is 800 words, for example, words L800 and R800 are not recorded, and instead of these words, zero data as dummy data is recorded.

1/m frequency dividing circuits 53 and 54 are connected to the reproduction side terminals p of the recording/reproduction changeover switches 51 and 52, respectively. The output signals of these 1/m frequency dividing circuits 53 and 54 are supplied to a digital phase comparison circuit 55. The output signal of the digital phase comparator circuit 55 is passed through the low-pass filter 5.
6 to C057 as a control signal. The output signal of this VCO 57 is a sampling clock during reproduction.

The above-mentioned VCO 57, selector 47, integration circuit 49, recording/reproduction switch 51, l/m frequency dividing path 53, phase comparison circuit 55, and low-pass filter 56 form a PLL loop.

P to form the internal sampling clock mentioned above.
An example of L L 45 will be described with reference to FIG. 11. This PLL 45 is for generating a basic clock of frequency fo. l) 1. , L and a PLL for generating the sampling frequency [S.

Sampling frequency @fs (48ktlz, 4
4.1 kHz, 32 kHz) and NTS C
Water frequency fh (15,734265kt(
z) is expressed by the following formula.

fs = (h15 X32X143 X160 XI
/125 XI/384=48,000 f s = r h15 X32X143 X147
xi/125 XI/384~=44.100 f s = fh15 X32X143 X16
0 X2/3 XI/125Xl/384 =32
,000 sampling frequency [if S is 48 kHz,
−, the formula is transformed as follows.

525 (1' 15x3 Niji
12-251 ns f・, = f F X (525x
32X143)15x(480x512)/(125X
3 x 384) = fF x 480480xl/11
25x4x480 format, CCI R method (fh =
15.625kHz) (7) In the case, f s = f h15 X32X144 X160
Xi/125 Xi/384= 48.000 f s = f h15 X32X144 X147
xi/125 Xi/384=44,100 f s = f h15 X32X144 X160
X2/3 XI/125Xi/384-32.000.

In FIG. 11, a phase comparator circuit 62 receives a signal of frame frequency f17 from a terminal 61 and a frequency dividing circuit 6.
The output signal of the phase comparison circuit 62 is supplied to the VCO 63.

The frequency division ratio N1 of the frequency dividing circuit 64 is (
N 1 =480480), and (N 1 =557056) in the CCIR method. Therefore, V.C.
The frequency of the basic clock generated by the output C of O63 is: fO=14.4M7 (NTSC system) fO=13.926MHz (CCI R system).

This basic clock is taken out to an output terminal 65 and is also supplied to a frequency dividing circuit 66. Frequency division ratio N2 of frequency division circuit 66
has been selected as the following value.

N2 = 1125 (NTSC method) N2 = 108
8 (CCIR method) The output signal of the frequency dividing circuit 66 is supplied to the phase comparison circuit 67. The phase comparator circuit 67 is supplied with an output signal from the frequency divider circuit 70 . The output signal of the phase comparison circuit 67 is V
It is supplied to C06B as a control signal, and the output signal of VC06B is supplied to the frequency dividing circuit 69. The frequency dividing ratio of the frequency dividing circuit 69 is set to 1, and the output signal of the frequency dividing circuit 69 is
0.

The output signal of the frequency dividing circuit 69 is taken out to the output terminal 71 and is also supplied to the frequency dividing circuit 72 . The frequency dividing ratio of the frequency dividing circuit 72 is set to (1/128), and the output signal of the frequency dividing circuit 72 is taken out to the output terminal 73.

The output signal of the frequency dividing circuit 66 is 12.8 kHz. The frequency dividing ratio N3 of the frequency dividing circuit 70 is (480: 4BkHz
, 441: 44.1kHz, 320: 32k
Hz), and from the frequency divider circuit 70, 12.8kl
A signal of lz is generated. The output terminal 71 has 128 fs.
A signal with a frequency of fs is obtained, and a signal with a sampling frequency fs is obtained at the output terminal 73.

Further, the integration circuit 49, the digital comparison circuit 46, and the integration circuit 50 have a configuration shown in more detail in FIG. 12. In Fig. 12, the integration times l are shown surrounded by broken lines.
The PI 30 includes an integration circuit 8I, a recording/reproduction switch 82, a switch circuit 83, and a data generation circuit 84.8.
5 is included. The digital comparison circuit 46 shown surrounded by a broken line includes a comparison circuit 87 and a flip-flop 88.

The sampling clock selected by the selector 47 is supplied to the integration circuit 49 from a terminal 91 .

An output signal of the integrated value NA is generated from the integrating circuit 49, and this integrated value NA is supplied to the comparing circuit 87 via the recording side terminal r of the recording/residing changeover switch 51. Output signals of data generation circuits 84 and 85 that generate data 800 and 801, respectively, are supplied to a switch circuit 83, and an output signal of the switch circuit 83 is supplied to a recording/reproduction changeover switch 8.
The signal is supplied to the integration circuit 81 via the recording side terminal r of No. 2.

The playback side terminal p of the recording/playback switch 82 has
A word count detection signal during reproduction is supplied from a terminal 86.

The integrated value NB from the integrating circuit 81 is sent to the comparing circuit 87 via the recording side end 7-r of the recording/reproducing switch 52.
is supplied to Comparison circuit 87 compares the magnitudes of integrated values NA and NB and generates a determination signal. This decision signal is supplied to flip-flop 88 as a data input.

Multiplier circuit 9 as clock input of flip-flop 88
An output signal of o is provided. The multiplier circuit 90 has a terminal 8
A servo reference signal is supplied from 9. The output signal of the flip-flop 88 is sent to an output terminal 92 as a word number selection signal.
At the same time, it is supplied to the switch circuit 83 as a control signal. The word number selection signal taken out to the output terminal 92 is supplied to the control circuit 20. Control circuit 2
0, a word number identification signal is formed from the word number selection signal and this identification signal is recorded together with the data.

The word number control operation during recording will be explained with reference to FIG. FIG. 13A shows the timing of the field period generated by the multiplier circuit 90. For example, if the numerical value 800 from the data generation circuit 84 is initially selected, as shown in FIG. 13B, the product X of the integration circuit 81 is
"value NB is also 800. On the other hand, the integration circuit 49 counts the sampling clock from the selector 47 and
As shown in Figure C, an integrated value NA of increasing values is generated sequentially.

The integrated values NA and NB are compared by the comparison circuit 87 at the timing of the field period. For example (N A = 79
9. N B =800), (NA≦NB)
Therefore, a determination signal of "0" is generated as shown in the 13th ID. Therefore, the word number selection signal from the flip-flop 88 also becomes "0". The number of words selection signal is “
0'', the switch circuit 83 is connected to the data generation circuit 8.
800 data from 4 is selected, the output of the integrating circuit 81 becomes 1600, and the number of words in one frame of the code becomes 800 words.

At the timing of the next field period, the integrated values NA and NB are compared again. At the time of this comparison, (NA=160
1), since (N B = 1600), (
NA>NB), and the word number selection signal becomes "1" as shown in FIG. 13I. Therefore, the switch circuit 8
3 selects data 801 from the data generation circuit 85, the output of the integration circuit 81 becomes 2401, and the number of words in one frame of the code becomes 801.

The same operation as described above is repeated, and it is assumed that the number of recorded words matches the number of words of the human data on average. Since the values of the integrating circuit 81 and the integrating circuit 49 are finite, when the field period is repeated a predetermined number of times, the respective integrated values return to their initial values.

During playback, record/playback switch 51, 52.
82 is in a state where it selects the reproduction side terminal p.

A word count detection signal from a terminal 86 is supplied to the integration circuit 50 (integration circuit 81). This word number detection signal is formed from an identification signal in the reproduced data, and corresponds to the number of recorded words. In addition, the integration circuit 4
9 is supplied with the output signal of the VCO 57 selected by the selector 47. The output signals of these integration circuits 49 and 50 are supplied to a digital phase comparison circuit 55 via l/m frequency division circuits 53 and 54, respectively, and phase comparison is performed.

The frequency division ratio m of the 1/rn frequency dividing circuits 53 and 54 is, for example, 1
00. In the digital phase comparator circuit 55,
Digitally compare the phases of the most significant bit of the output of the integrating circuit 50 which changes stepwise, divided by l/m, and the most significant bit of the output of the integrating circuit 49, divided by 1/m. . Specifically, the digital phase comparison circuit 55 is constituted by an exclusive OR gate.

Since the output signal of the digital phase comparison circuit 55 is supplied to the VCO 57 via the low-pass filter 56, the VCO
The sampling clock generated from 5'7 is the same as that during recording. Therefore, during playback, the audio PCM
There is no problem of insufficient or surplus signals.

r, Modified Example In this example, two types of numerical data are 800
and 80], but in addition to these, values close to the quotient of the sampling frequency Is divided by the field frequency, such as 800 and 802, may be used. Further, the number is not limited to two, but three or more types of numerical values may be selectively used.

In this invention, error correction codes other than Reed-Solomon codes can be used.

〔Effect of the invention〕

In this invention, even if the number of words included in one frame of the code structure of a digital information signal is an integer, it is possible to record the number of words equal to the quotient of the sampling frequency divided by the field frequency on average. It is possible to prevent synchronization between video and audio from occurring. Also·
According to this invention, when an external digital input is recorded in synchronization with an external clock, the frequency relationship between the sampling clock and the recording reference signal can be made the same as during recording during playback, and the audio PCM signal during playback can be It is possible to prevent excess or deficiency of data from occurring.

[Brief explanation of the drawing]

FIG. 1 is a route map showing a block configuration of an embodiment of this invention, FIG. 2 is a route map showing a frame configuration of an embodiment of this invention, and FIG. 3 is a route map used to explain the generation of C2 codes. , FIG. 4 and FIG. 5 are route maps used to explain an example of data interleaving, FIG. 6 is a route map used to explain the header configuration, and FIG. 7 is a route map of another example of the frame configuration.
8 and 9 are a block diagram and a timing chart of an example of a recording/reproducing circuit of a rotary head type VTR to which this invention can be applied, FIG. 10 is a block diagram of a clock generation circuit, and FIG. 11 is a clock generation circuit. Figures 12 and 13 are a detailed block diagram of a portion of Figure 11 and a timing chart used to explain its operation. Figure 14 is used to explain the conventional error correction code. This is a route map. Explanation of main symbols in the drawings ■ = rotating drum, 2: cab stan, 3: servo circuit, 5: video processing circuit, 7: system bus, 8: A/D and D/A interface, 20: control circuit, 45 : PLL for clock generation, 46: Digital comparison circuit, 47: Selector, 48: External clock input terminal, 49.50: Integration circuit, 55: Digital phase comparison circuit, 57: VCO. Figure 5: One house for the frame scheme

Claims (3)

[Claims] (1) In a digital signal recording/reproducing device in which the sampling frequency of the digital information signal to be recorded and the frequency of the internal recording reference signal are not in an integer ratio, the sampling frequency is set to the frequency of the recording reference signal or the recording reference signal at the time of recording. a circuit that generates data of a plurality of integer values close to the quotient obtained by dividing by a frequency that is an integral multiple of , and a first circuit that selectively supplies data of the plurality of integer values.
a second integrating circuit that integrates the number of samples of the digital information signal, and a number of recording samples is selected so that the output of the first integrating circuit and the output of the second integrating circuit are equal. and a means for recording an identification signal indicating the number of recording samples, and at the time of reproduction, supplying the number of recording samples obtained from the reproduced signal to the first integrating circuit, and supplying the output signal of the PLL to the second integration circuit. and means for comparing the phases of the output of the first integrating circuit and the output of the second integrating circuit and supplying the comparison output to the VCO of the PLL as a control signal. A digital signal recording and reproducing device characterized by: (2) The sampling frequency of the digital information signal to be recorded and the frequency of the internal recording reference signal are not in an integral ratio, and an identification signal indicating the number of recording samples per one or more cycles of the recording reference signal is recorded. Means for supplying the number of recording samples obtained from the reproduction signal to a first integration circuit in a digital signal reproduction device that reproduces a recording medium, and supplying the output signal of the PLL to a second integration circuit; A digital signal reproducing device comprising means for comparing the phases of the output of the integrating circuit and the output of the second integrating circuit and supplying the comparison output to the VCO of the PLL as a control signal. (3) Claim (1) or claim (2) characterized in that the output of the first integration circuit and the output of the second integration circuit are supplied to the phase comparator circuit via a frequency dividing circuit, respectively. ) Digital signal recording/playback device.