JPH01188179A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain a satisfactory picture by simultaneously reading the signal charges of plural horizontal lines with plural reading registers, directly supplying the charges to a signal processing circuit, delaying the reading signal of one line, at least, for a prescribed period and supplying the signal to the signal processing circuit. CONSTITUTION:The signal charges of the plural horizontal lines are simultaneously read by reading registers 5 and 6 and supplied to signal processing circuits 24 and 25 directly. Then, the reading signal of one line, at least, is delayed for the prescribed period and supplied to the signal processing circuits 24 and 25. Thus, by delaying the reading signal of one horizontal line, at least, out of the plural lines to be simultaneously read for the prescribed period, a signal in the same condition as to change the arrangement of a color filter, which is arranged in correspondence to a photo-detecting element, is obtained. Then, by the signal not to be delayed and this delayed signal, the reading signal of the arrangement of the color corresponding to >= a real horizontal line number is obtained. Thus, with small horizontal line number as one unit, the satisfactory video signal of a high S/N ratio and high vertical resolution can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device suitable for use in, for example, a single-chip color camera.

[Summary of the invention]

The present invention provides a solid-state imaging device suitable for use in, for example, a single-chip color camera, including a light-receiving element, a transfer register for transferring signal charges accumulated in the light-receiving element, and a signal charge transferred by the transfer register. The plurality of readout registers simultaneously read out the signals 11i of the plurality of horizontal lines, and the readout signals of the plurality of horizontal lines are directly supplied to the signal processing circuit. At least one line of the readout signals is delayed for a predetermined period and then supplied to the signal processing circuit, thereby making it possible to obtain a good image with a high SN ratio and high vertical resolution.

(Prior Art) Conventionally, a solid-state imaging device for use in a ll& type color camera has been proposed, the planar structure of which is schematically shown in FIG.

In this FIG. 8, +1) indicates a P-type silicon substrate,
In this solid-state imaging device, this P-type silicon substrate (
A light receiving element consisting of a photodiode +21 is placed on the surface side of 11.
A light-receiving section (3) consisting of 492 (vertical) x 510 (horizontal) pieces of +21...(2) arranged in a matrix is provided, and a subject image is formed on the surface of this light-receiving section (3). A signal charge corresponding to the brightness of the subject image is transmitted to each light receiving element (21(
21...(2) is multiplied by N. In this case, for example, white W, green G,
@Ye.

Color filter such as cyan Cy 492 (DuM)
A color filter array (not shown) consisting of 510 (horizontal) color filters is arranged, and each color filter of this color filter array is made to correspond to each light receiving element (2) (2)...(2). , signal charges based on colored light passing through each color filter are accumulated in each light receiving element (2+ (21...(2)).

In addition, light-receiving elements (2) (2) arranged in a matrix
...(2) Vertical registers (41(4)...(4) consisting of charge-coupled devices (hereinafter referred to as CCDs) for each column
is provided, and each light receiving element +21 +2)...(2)
The signal charges accumulated in the
+21... (2) The signal charges accumulated in (2) are read out every field and every alternate horizontal line to perform interlacing, and the signal charges are transferred in the vertical direction, that is, toward the bottom of the page. ing.

Also, this vertical register (4) (4)...(4)
First and second horizontal registers (5) and (6) consisting of CCDs forming readout registers are provided in two columns on the output side of The incoming signal charges are transferred in the horizontal direction two horizontal lines at a time. In this case, both horizontal registers (5) and (6) are connected through the gate part (11), and the first horizontal register (5) and the second horizontal register (6) form one horizontal line. The shifted signals are transferred line by line.

The output sides of the horizontal registers (5) and (6) are equipped with, for example, floating diffusion amblifiers.
output parts (7) and (8) consisting of
is provided, and this output section (
Output terminals (9) and (lO
).

This image signal is output as a color signal that changes in accordance with the color arrangement state of the color filter array arranged on the light receiving section (3). For this reason, for example, the color filters arranged corresponding to the four adjacent light-receiving elements (2) on the upper, lower, left, and right sides are different colors, and the respective light-receiving elements (2) constituting the four pixels of these two lines are colored as shown in FIG. ) with different color signals 31. S2. S3.
By obtaining S4, a good color imaging signal with less moiré can be obtained. That is, as mentioned above, 2
Since the image signals of two adjacent horizontal lines are simultaneously output from the horizontal registers (5) and (6), the output terminal (
9).

The signal processing circuit to which the signals from (10) are supplied can simultaneously process the signals 31 to s4 having information on these four colors,
For example, the luminance signal Y can be obtained by mixing the color signals of these four colors. Then, in order to convert into red R2 green G and blue B color video signals, the first chroma signal C1
and a second chroma signal C2 is required, then the first chroma signal C2 is required.
The chroma signal C1 of the first line is the signal S1+32
and the second line signal S3. S4 and the second chroma signal C2 as shown in FIG.
Signal 31'+S2' on the third line adjacent to s4
and the fourth line signal S 3' l S 4'. In this case, the signal Sll S2. S31 S4
The pixel color filter array and signal S L' + corresponding to
The arrangement of the color filters of the pixels corresponding to S 2' * S 3' * S 4' is changed, for example, as described above, the luminance signal Y is expressed as Y = S t + S 2 + S
3 + S4, the first chroma signal C1 is C1= (SL +33) - (S2 +S4), and the chroma signal C2 of 9A2 is C2= (S1'+33') (S2'-84")
can be obtained as

Then, the signals s1~S4°S, 1~S from these 8 pixels
Based on the luminance signal Y and chroma signal c1°C2 obtained from 4', color video signals of three primary colors, for example, red R1, green G, and blue B, can be obtained. The video signal obtained by simultaneous reading of two lines in this manner has the advantage of less color moire.

Problems to be Solved by the Invention C] However, if a color video signal is obtained by simultaneously reading two lines in this way, readout signals of four horizontal lines are required to obtain a video signal of the 141st primary color. Therefore, there was an inconvenience that the vertical resolution of the video (No. 8) was low.

In order to solve this problem, for example, the signal S from the four light receiving elements (2) of two adjacent lines shown in FIG.
L, S2.33. Only S4 outputs the luminance signal Y and the first and second
The vertical resolution can also be increased by obtaining the chroma signals c1 and C2.

That is, the luminance signal Y may be obtained as Y=St+S2+S3+S4, the first chroma signal C1 may be obtained as C1-5t-52, and the second chroma signal C2 may be obtained as C2-53-S4. can.

However, in this case, only the signals from the four light receiving elements (2) are directly subtracted, so the chroma signals CL, C2
The signal level of the video signal was low, and the signal-to-noise ratio of the video signal was poor.

In view of the above, it is an object of the present invention to provide a solid-state imaging device that performs two-line simultaneous readout and can obtain good video signals with high vertical resolution.

[Means to solve the problem]

For example, as shown in FIG. a transfer register (4) (41...(4)) that transfers the signal charge to be transferred;
This transfer register (41 (41... ) simultaneously reads out the signal charges of a plurality of horizontal lines, supplies the readout signals of the plurality of horizontal lines directly to the signal processing circuits (24) and (25), and at least one of the readout signals of the plurality of horizontal lines.
The line read signal is delayed for a predetermined period and then supplied to the signal processing circuits (24) and (25).

(Function) According to the solid-state imaging device of the present invention, by delaying the readout signal of at least one horizontal line among the plurality of lines read out simultaneously for a predetermined period, the color filter disposed corresponding to the light receiving element (2) A signal in the same state as when changing the arrangement of The signal-to-noise ratio is high (the number is 1) (good video signals with high vertical resolution can be obtained).

〔Example〕

Hereinafter, one embodiment of the solid-state imaging device of the present invention will be explained with reference to FIGS. 1 to 4. In FIGS. 1 to 4, parts corresponding to FIGS. are given the same reference numerals, and detailed explanation thereof will be omitted.

In this example, as in the conventional example, an interline transfer type solid-state imaging device is used that can read signal charges of two horizontal lines at the same time.As shown in FIG. A light-receiving section (2) consisting of photodiodes (2) +2)... (2) arranged in a matrix, for example 492 (vertical) x 76B (horizontal), on the side.
3), a subject image is coupled to the surface of this light receiving section (3), and a signal charge corresponding to the brightness of this subject image is transmitted to each light receiving element (3).
21(2)...<21.

In this case, a color filter array (12) shown in FIG. 2 is arranged on the surface of the light receiving section (3).
) for each color filter on each light receiving element (2) +2)...
Corresponding to (2), the signal charge based on the colored light passing through each filter is transferred to each light receiving element +2) +2)...(2
). This color filter array (1
2) C. First horizontal line L1. Third horizontal line L31
... Yellow Ye and cyan cy color filters are arranged alternately on the 491st horizontal line L491, respectively, and the second horizontal line L2. 4th horizontal line L 41...49th
It is constructed by alternately arranging white W and green G color filters on two horizontal lines L (s2).

In addition, light receiving elements arranged in a matrix + 2) (2)
...(2) A vertical register consisting of CCU for each column (
4) (41...(4) is provided, and the light receiving element (2) (
2)・・・The signal charge accumulated in (2) is vertically
In other words, the image can be transferred downward on the page.

In addition, a first horizontal register (5) made of COD is provided on the output side of the vertical register (41 (4) (4)), and a second horizontal register (5) made of the same < COD is provided via the gate part (11). A horizontal register (6) is provided.A first output section (7) and a second output section (8) for signal amplification are provided on the output side of each of the horizontal registers (5) and (6), respectively. , such as the first and second output parts (7) and (8
) to the first and second output terminals (9) and (10), respectively.
Derive.

The first and second output terminals (9) and (10
) is supplied to a signal processing circuit as shown in FIG. That is, the first and second output terminals (9
) and (10) are connected to one and the other addition signal input terminals of the first adder (21), respectively. Further, the first output terminal (9) is connected to one addition signal input terminal of the second adder (22), and the second output terminal (10) is connected to the second output terminal (10) via the delay circuit (23). Connect to the other addition signal input terminal of addition 1 (22). In this case, the delay circuit (23) is a circuit that delays the transfer time of one pixel of the horizontal register (6) (1 (transfer time of the signal charge of the light receiving element (2) of II).

The addition output signals of the first and second adders (21) and (22) are then supplied to the sampling separation circuit (24), respectively. The sampling separation circuit (24) separates the added and supplied readout signals into signals for each readout period of one pixel as described later, and supplies the separated color signals to the matrix circuit (25). Further, the addition output signal outputted by the first addition circuit (21) is transferred to the matrix circuit (
Based on these signals, the matrix circuit (25) converts them into R, G, and H primary color signals, and the converted R2O and H primary color signals are supplied to the red signal output terminal (25), respectively.
6R).

Green signal output terminal (26G) and blue signal output terminal (
26B).

Next, each light receiving element (2) is
(2+...(2)) To explain the operation when reading out the signal charge accumulated by receiving light, for example, the first horizontal register (5) is connected to the light receiving element (2) of the second horizontal line L2 (
2)...The signal charge of (2) is read out, and the second horizontal register (6) reads the light receiving element (21() of the first horizontal line L1).
21...(2) is in a state where the signal charges are being read out. At this time, the signal obtained at the output terminal (9) is connected to the second horizontal line L2, as shown as the signal S^ in FIG.
The color signal is based on the arrangement of the color filters W, G, W, .
1 color filter Ye, Cy, Ye = Ye.

The color signal is based on the cy array. Therefore, the addition signal output from the first addition circuit (21) is
．． A signal Sχ is obtained by adding the signal S^ISB of LL. In this signal S, white W and yellow Ye signals are simultaneously obtained as color signals at a predetermined timing, and green G and cyan cy signals are simultaneously obtained at different timings.

The signal supplied to the second adder circuit (22) is
As shown in FIG. 4, the signal S1 of the first horizontal line L1 is delayed by one pixel by the delay circuit (23), so the addition signal sy output by the second addition circuit (22) is
is white W and cyan Cy at predetermined timing as color signals.
signals are obtained at the same time, and green G and yellow Ye signals are obtained at different timings.
signals can be obtained simultaneously.

Since the sampling separation circuit (24) separates signals for each pixel that are obtained simultaneously, this addition circuit (21)
, (22).

sy, a mixed signal of white W and kYe, a mixed signal of green G and cyan Cy, a mixed signal of white W and cyan cy, a mixed signal of green G and yellow Ye, and each mixed signal is sent to the matrix circuit. (25)
supply to.

Then, this matrix circuit (25) combines the mixed signals such as these and the addition No. 16 S× outputted by the first addition circuit (21).
As a result, color signals of the three primary colors R, G, and H are obtained, and the primary color signals obtained by conversion are supplied to output terminals (261?) (26G) and <26B).

In this way, according to the solid-state imaging device of this example, one unit is based on the signals (one element each of W, G, Ye, and Cy) obtained from a total of four light receiving elements (2) in two adjacent horizontal lines. (1
A color video signal of the primary colors of pixels (pixels) is obtained. For this reason,
111 using four horizontal lines as shown in the conventional example.
The vertical resolution is twice as high as that of a system that obtains color video signals of the same primary colors. In addition, by using a delay circuit (23) to substantially change the color arrangement of the signals from the four light receiving elements (2) of the two horizontal lines, a signal in the same state as the signal from the four horizontal lines can be obtained. Since the signal from the four light-receiving elements is subtracted to obtain the ζ chroma signal, the signal level does not become small, and the signal level is large and has a high signal-to-noise ratio with little influence of noise. It is possible to obtain a color video signal with a high quality and a good image with little noise.

An example of the signal processing performed by the matrix circuit (25) is expressed by an equation. First, a luminance signal Y and first and second chroma signals C1 and C2 are created.

Luminance signal Y - W + Y e + G + Cy = 4
G+2R+2B First chroma signal 'CL = (W+Ye)-(G+C
y)=2R Second chroma signal C2= (W+Cy)-CG+Ye)
The primary color signals of R, G, and B are obtained based on the signals Y, C1, and C2 of the field 2B and others.

In the above embodiment, the readout signals from each light receiving element are added outside the substrate (1), but the signal charge is taken out using a floating gate and added to the signal charge on the substrate (1) on which the CCD is configured. It is also possible to add the values in a circuit and then output them. That is, as shown in FIG. 5, the signal charges of the vertically adjacent pixels transferred to the first and second horizontal registers (5) and (6) are not read out, but are transferred to the floating gate (31) in the horizontal direction. A floating gate (32) is provided without reading out the signal charge of the upper pixel which is shifted by one pixel, and both floating gates (31) and (32) are provided.
) may be supplied to the sampling separation circuit (24) and the matrix circuit (25).
In this case, for example, as shown in FIG.
1a ) and a floating gate (
One end of each floating gate (31b) is connected to the clock signal source (33a) and (33b), respectively.
The other ends of 31a) and (31b) are connected to FE'l' (34
) to a common source. And this NET (3
Connect the drain of 4) to the power supply terminal Van (35), and
E 'l' (34) (7) Connect the gate to the control terminal (3
6). Also, the source of FE"r (34) is connected to the detection signal output terminal (37). With this configuration, the signal charge of a predetermined pixel of the first horizontal register (5) and the second horizontal The signal charge of a predetermined pixel of the register (6) is simultaneously read out to the output terminal (37).

By reading out signals using floating gates in this way, the readout signals are added in the circuit on the board (11) on which the COD is configured, reducing the influence of noise caused by signal amplification at the output section. This improves the signal-to-noise ratio of the read signal.

In addition, as shown in Fig. 7, a floating gate (38
) and (39), signal charges caused by light of the same color on the same horizontal line may be simultaneously read out and added for two adjacent pixels. In the case of the example in FIG. 7, the horizontal resolution is lower than in the example in FIG. 5, but the signal level is higher and the SN ratio of the read signal is further improved.

Furthermore, the arrangement of color filters shown in the above-described embodiments is merely an example, and various other arrangements may be selected. Furthermore, the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations may be adopted without departing from the gist of the present invention.

(Effects of the Invention) According to the present invention, there is an advantage that a solid-state imaging device that performs two-line simultaneous readout can obtain a good image with a high SN ratio and high vertical resolution.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the solid-state imaging device of the present invention, FIGS. 2, 3, and 4 are route maps for explaining the example in FIG. 1, and FIGS. 5 and 7. 6 is a circuit diagram showing an output section of the example shown in FIG. 5, and FIG. 8 is a configuration diagram showing an example of a conventional solid-state imaging device.
FIG. 9 is a route map for explaining the example in FIG. 8. Ill is a P-type silicon substrate, (2) is a light receiving element, (3)
is the light receiving section, (4) is the vertical register, (5) is the first horizontal register, (6) is the second horizontal register, (21) is the first addition circuit, and (22) is the second addition circuit. , (23) is a delay circuit, (24) is a sampling separation circuit, (25)
is a matrix circuit.

Claims (1)

[Scope of Claims] A light receiving element, a transfer register that transfers signal charges accumulated in the light receiving element, and a plurality of readout registers that read out signal charges transferred by the transfer registers, The signal charges of a plurality of horizontal lines are simultaneously read out by a readout register, the readout signals of the plurality of horizontal lines are directly supplied to a signal processing circuit, and the readout signal of at least one line among the readout signals of the plurality of horizontal lines is read out for a predetermined period. A solid-state imaging device characterized in that the signal is supplied to the signal processing circuit with a delay.