JPH01186013A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a pulse width expansion circuit with high accuracy by inputting a pulse via a superconductive delay line to an OR circuit. CONSTITUTION:A pulse via a conventional communication line 5 and a pulse retarded with high accuracy in response to the length of a superconductive delay line 4 made of a OR temperature superconductor therethrough are given to a OR gate 1. A pulse whose width is expanded from the gate 1 in response to the delay time based on both inputs is outputted and a pulse width expansion circuit with high accuracy is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a pulse width stretching circuit including delay means.

[Conventional technology]

Pulse technology has made remarkable progress along with semiconductor technology such as ICs, and high-speed pulse circuits in particular are indispensable for hardware for realizing high-speed digital information processing technology, and are widely used in electronic devices. Pulse width control is a basic circuit technology in high-speed pulse circuits. Although this technology has an extremely wide range of applications, it is especially essential for the following two applications.

The first is used for precise timing control within clock time, and the second is used to correct changes in pulse width of the output waveform of an element in a nonlinear circuit. Typical nonlinear elements include, for example, semiconductor lasers and light emitting diodes, and with the recent development of optical communication technology, the above-mentioned applications have become increasingly important.

FIG. 3 shows a conventional pulse width stretching circuit.

The OR gate circuit 1 has two input terminals and one output terminal, and a buffer circuit 2 is connected to one input terminal (FIG. 2(a)).

As this buffer circuit 1, an inverter circuit 3 can be simply used.
．． 3 connected in two cascades may be used (FIG. 3(b)).

FIG. 4 shows operating waveforms of the pulse width expansion circuit shown in FIG. 3. For example, if the delay time of the buffer circuit 2 connected to the circuit is t, the pulse width of the output waveform is 2
It spreads by t. Note that when shortening the pulse width, a waveform obtained by further inverting the output waveform is used. in this way,
The output waveform is expanded.

[Problem to be solved by the invention]

However, conventional pulse width stretching circuits have had the following problems, especially in integrated circuits using compound semiconductors, as electronic circuits have become faster in recent years.

First, there is a narrow degree of freedom in setting the amount of change in pulse width. The amount of change in pulse width in the circuit shown in Figure 4 is an even multiple of the delay time of buffer circuit 2 (or inverter 3.3) (or the sum of the delay times of each inverter), and can be set to any value. It was difficult to select the

Second, the accuracy is not sufficient. According to the conventional pulse width stretching circuit, the temporal accuracy depends on the accuracy of the delay time. However, in recent years, high-speed integrated circuits, especially integrated circuits using compound semiconductors, are difficult to manufacture, so it is difficult to reduce the variation in delay time of OR gate circuits and ensure lot-to-lot reproducibility. It is extremely difficult.

On the other hand, as clock speeds in high-speed pulse circuits become faster, demands on the temporal accuracy of pulse widths have become more severe.

Therefore, an object of the present invention is to improve the accuracy of a pulse width expansion circuit.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a method in which a pulse input having a constant width is directly applied to at least one input terminal of an OR gate circuit having a plurality of input terminals.
A semiconductor device having a pulse width expansion circuit that outputs a pulse with an expanded pulse width by applying a pulse input to at least one other input terminal via a delay means, the delay means being based on a superconducting line. It is characterized by being a delay line.

Further, the pulse input is applied to at least one input terminal of the logic gate circuit having a plurality of input terminals via the first delay means, and the pulse input is applied to at least one other input terminal at a delay different from the first delay means. A semiconductor device having a pulse width expansion circuit that outputs a pulse with an expanded pulse width by applying time through a second delay means, the first and second delay means being a delay line formed by a superconducting line. It is characterized by

[Effect]

Since this invention is configured as explained above,
Due to the action of the delay line formed by the superconducting line, input pulses are input to the two input terminals with a time lag, and a pulse having a pulse width corresponding to the time lag is output.

Furthermore, by using two superconducting lines with different delay times for the respective input terminals, the delay time of the pulse input given to the OR gate circuit changes, and the output pulse width and pulse timing change.

〔Example〕

An embodiment of a semiconductor device according to the present invention will be described below with reference to the accompanying drawings. In the description, the same elements are denoted by the same reference numerals, and redundant description will be omitted.

FIG. 1(a) shows an embodiment of a semiconductor device according to the present invention, and FIG. 1(b) shows its circuit configuration. In FIG. 1, a portion surrounded by a broken line is an OR gate circuit 1. A superconducting line 4 is connected in series as a delay line to one of the two input terminals of the OR gate circuit 1, and a normal signal line 5 is connected to the other.

One end of the superconducting line 4 is connected to one of the input terminals of the OR gate circuit 1, and the other end is connected to the signal line 5. The superconducting line 4 is, for example, at a liquid nitrogen temperature (77°K).
) It consists of a 5 mm to 10 mm microstrip line or coplanar line in which a ceramic-based high-temperature superconductor that becomes superconducting is sandwiched between silicon nitride films.

In this embodiment, in order to save area, the superconducting line 4 is formed in a so-called meander structure and is housed in a very small area.

The superconducting line 4 is described, for example, in the ``Journal of Research of National and Neelow of Standards (R, L, Kautz; Journal of'Re
5earch of National Bureau
orStandards) Vol, 84. No.3. M
ay-June, 1979. pl), 247-2594
As shown in the analysis, the extremely wide band allows pulses to be transmitted without deterioration.

The effect will be explained below. Input pulse is input pad 6
One branch is sent to the signal line 5 and directly input to the OR gate circuit 1. The other one is input to the OR gate circuit 1 via the superconducting line 4. However, since the delay time of a superconducting line depends on its length, the length of this example
Superconducting line 4 of about 5 mm to 10 mm has a speed of about 100 ps
It becomes a high-quality delay line with a delay time of about 200 ps. Therefore, the pulse input from the input pad 6 to the gate F via the superconducting line 4 is delayed by about 100 ps to 200 ps from the pulse applied to the signal line 5 and input to the gate H. Therefore, the pulse width of the output pulse can be made wider than the input pulse by about 100 ps to 200 ps.

FIG. 2 shows operational waveforms of the embodiment shown in FIG. If the delay time of the superconducting line 4 connected to the OR gate circuit 1 is t, 1, the pulse width of the output waveform is td
It spreads by l. If this is inverted, a waveform narrower by t,1 can be obtained.

FIG. 3 shows another embodiment of the semiconductor device according to the present invention. The difference from the embodiment shown in FIG. 1 is that a first superconducting line 7 and a second superconducting line 8 are connected to the input terminals as delay means, respectively. Here, since the delay time of the first superconducting line 7 is configured to be longer than that of the second superconducting line, the output pulse is expanded more than the input pulse and output.

FIG. 4 shows operational waveforms of the embodiment shown in FIG. 3. Superconducting line 7 connected to OR gate circuit 1.
The delay time of 8 is 1. 1, the pulse width of the output waveform is widened by (L d2t dI). If you connect an inverter circuit to this output, (td
A waveform narrower by 2-td□) is obtained.

FIG. 5 shows a modified example in which there are three input terminals. Delay time of superconducting line 7.8 is 1 Sl
Then, the pulse width of the output waveform is td2di
It can be expanded by d2. In this case, when the width of the input pulse is T, t d2 > T, and the circuit is useful as an expansion circuit for a pulse width exceeding the pulse width.

As described above, the number of input terminals in the application of the present invention is not limited to two, and a wide variety of input terminals are possible. What is important is that the superconducting line is connected to at least one input terminal.

Although this embodiment has been described using a pulse width expansion circuit as an example, if an inverter circuit is added to the output terminal of this circuit to invert the pulse signal, it can be used as a pulse width shortening circuit.

〔Effect of the invention〕

Since this invention is configured as explained above,
Highly accurate pulse width can be freely selected. In particular, since the amount of change in pulse width can be determined only by the physical length of the superconducting line, it is possible to achieve higher precision in the pulse width expansion circuit, reduce the variation in delay time of the OR gate circuit, and It becomes easy to ensure reproducibility between lots.

In addition, the amount of change in pulse width is determined by the amount of change in the OR gate circuit, unlike the conventional technology in which the required number of delay elements such as CR integration circuits, Schmitt circuits, MOS FETs, and Miller integration circuits are inserted. Any time can be easily set over a wide range from about the rise time to several hundred ps or more.

Furthermore, the mechanism that determines the amount of change in pulse width is IC.
Since it is determined only by the shape of the superconducting line on the package, it is unrelated to factors that cause variations in element characteristics in semiconductor integrated circuits, and variations can be suppressed not only within the wafer surface but also between lots.

In the present invention, since pulse width variation is realized only by passive components, there is an economical advantage of lower power consumption compared to the prior art.

In particular, in the invention in which superconducting lines are provided on both input terminals of the OR gate circuit, the length of both superconducting lines is: J3
By adjusting the pulse width, not only the pulse width but also the pulse timing can be controlled.

[Brief explanation of the drawing]

1 is a diagram showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a diagram showing operating waveforms of the embodiment shown in FIG. 1, and FIG. 3 is a diagram showing an embodiment of a semiconductor device according to the present invention. 4 is a diagram showing operation waveforms of the embodiment shown in FIG. 3, FIG. 5 is a diagram showing a modification of the semiconductor device according to the present invention, and FIG. 6 is a diagram showing another embodiment. A diagram showing a conventional pulse width stretching circuit,
FIG. 7 is a diagram showing operating waveforms of the pulse width expansion circuit shown in FIG. 6. 1... OR gate circuit 2... Buffer circuit 3.
...Inverter circuit 4...Superconducting line 5...Ordinary signal line 6...Input pad 7...First superconducting line 8...Second superconducting line Patent applicant Sumitomo Electric Industries, Ltd. Representative Patent Attorney Yoshiki Hasejo
Mountain 1) Row −−1−+−
1d1-? -I-td. Operating waveforms of the embodiment Fig. 2 Operating waveforms of other embodiments Fig. 4 Input modification example Conventional pulse width expansion circuit Fig. 6 Operating waveforms of the prior art Fig. 7

Claims (1)

[Claims] 1. A pulse input having a constant width is directly applied to at least one input terminal of an OR gate circuit having a plurality of input terminals, and the pulse input is applied to at least one other input terminal. A semiconductor device having a pulse width stretching circuit that outputs a pulse with an expanded pulse width by applying the pulse width through a delay means, the delay means being a delay line made of a superconducting line. Semiconductor equipment. 2. The semiconductor device according to claim 1, wherein the semiconductor device uses a compound semiconductor. 3. The semiconductor device according to claim 1, wherein the superconducting line is a high temperature superconductor. 4. Applying a pulse input to at least one input terminal of an OR gate circuit having a plurality of input terminals via a first delay means, and applying the pulse input to at least one other input terminal by the first delay means. A semiconductor device having a pulse width expansion circuit that outputs a pulse with an expanded pulse width by providing a delay time different from that of the second delay means through a second delay means, wherein the first and second delay means are superconducting. A semiconductor device characterized in that the delay line is a line. 5. The semiconductor device according to claim 4, wherein the semiconductor device uses a compound semiconductor. 6. The semiconductor device according to claim 4, wherein the superconducting line is a high temperature superconductor.