JPH01185452A - Apparatus for testing electric circuit board - Google Patents

Apparatus for testing electric circuit board

Info

Publication number
JPH01185452A
JPH01185452A JP63008544A JP854488A JPH01185452A JP H01185452 A JPH01185452 A JP H01185452A JP 63008544 A JP63008544 A JP 63008544A JP 854488 A JP854488 A JP 854488A JP H01185452 A JPH01185452 A JP H01185452A
Authority
JP
Japan
Prior art keywords
circuit
layers
circuit pattern
resistance
capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63008544A
Other languages
Japanese (ja)
Inventor
Hideyuki Sumiyoshi
住吉 英之
Izumi Namita
泉 波多
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Via Mechanics Ltd
Original Assignee
Hitachi Seiko Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Seiko Ltd filed Critical Hitachi Seiko Ltd
Priority to JP63008544A priority Critical patent/JPH01185452A/en
Publication of JPH01185452A publication Critical patent/JPH01185452A/en
Pending legal-status Critical Current

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

PURPOSE:To obtain a test apparatus not overlooking the shortcircuit error between circuit pattern layers and enhanced in reliability, by continuously measuring the resistance value between two conductive circuit layers when both electrostatic capacity values measured between a reference conductive plate and two conductive circuit patterns are equal or almost equal to each other. CONSTITUTION:When both electrostatic capacity measured values C1, C2 between circuit pattern layers 1a, 1b and a reference conductive plate 3 by a capacity measuring apparatus 10 are equal or almost equal, the following operation is taken even a case judged to be a good product by the measurement of electrostatic capacity. That is, a control computer 11 holds a contact element 6 as it is when said contact element 6 is brought into contact with the terminal part 1c of the upper circuit pattern layer 1a theretofore and moves a contact element 5 to the terminal part 1d of the lower circuit pattern layer 1b by an X-Y positioning apparatus 7 to bring the same into contact therewith. Subsequently, a resistance measuring apparatus 9 is operated to measure the resistance between the layers 1a, 1b. When the resistance measured value is 0 or almost 0, it is made clear that the layers 1a, 1b are shortcircuited and the overlooking of a shortcircuit error is prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、プリント基板などの電気回路板の導電回路の
誤配線など(エラー)をチエツクするテスト装置に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test device for checking for incorrect wiring (errors) in conductive circuits on an electric circuit board such as a printed circuit board.

〔従来の技術〕[Conventional technology]

一般に、この種のテスト装置は、2つの接触子と、この
2つの接触子を、テスト位置にセットされた被テスト電
気回路板上の所望箇所(通常は端子)に各々独立して移
動し、接触させる位置決め装置と、前記2つの接触子相
互間の抵抗を測定する抵抗測定装置と、前記2つの接触
子のうちの任意の一方と前記電気回路板セット面に所定
の誘電体層を挟んで対向する位置に配設された基準導電
板との間の静電容量を測定する容量測定装置とを備えて
なり、これらを所定の手順に従って作動させて電気回路
板をテストするものである。
Generally, this type of test equipment includes two contacts, each of which is moved independently to a desired location (usually a terminal) on an electrical circuit board under test that is set at a test position. a positioning device for contacting, a resistance measuring device for measuring the resistance between the two contacts, and a predetermined dielectric layer sandwiched between any one of the two contacts and the electric circuit board set surface. The device is equipped with a capacitance measuring device that measures the capacitance between a reference conductive plate placed at an opposing position, and is operated according to a predetermined procedure to test an electric circuit board.

ところで、最近、電気回路、例えばプリント基板におい
ては、それに形成する回路パターン(導電回路)の多層
化が進んできているが、このようなプリント基板(以下
、多層基板という)において、次のような場合には、単
に静電容量測定するだけでは適正なエラー検出ができな
い。すなわち、2層の回路パターンが同−又は近似の形
状で、かつ相互に全体又はほぼ全体が重なり合っている
場合、静電容量測定ではそれら両回路パターンが短絡し
ていても、短絡していない場合と同様の測定結果となり
、短絡エラー検出できない。
By the way, recently, the number of layers of circuit patterns (conductive circuits) formed on electric circuits, such as printed circuit boards, has been increasing. In some cases, it is not possible to properly detect errors simply by measuring capacitance. In other words, if the circuit patterns in the two layers have the same or similar shapes and completely or almost entirely overlap each other, then even if both circuit patterns are short-circuited in capacitance measurement, if they are not short-circuited. The measurement result is the same as that of , and the short circuit error cannot be detected.

これについて、第2図及び第3図を参照して詳述する。This will be explained in detail with reference to FIGS. 2 and 3.

両図において、1は形状が同一の2つの回路パターン層
1a、 lbを有する被テスト多層基板、2はテスト装
置の被テスト基板セット面、3はこのセット面2に誘電
体層4を挟んで対向する位置に配設された基準導電板で
ある。この導電板3は、一方の入力端が一方の接触子(
図示せず)に接続された容量測定装置(図示せず)の他
方の入力端に接続されている。また、Slは上部回路パ
ターン層1aの、S2は下部回路パターン層1bの面積
を表わし、S3は上、下部回路パターン層1a、 lb
が短絡しているときの回路パターン層1a、lbの総合
面積を表わす、さらに、d、は基板1の厚さを、d8は
誘電体層4の厚さを、各々示し、ここではd、に比べて
d2が充分太きく (a、<<aX)、静電容量測定上
、基準導電板3と回路パターン層la、 lb間の各寸
法がほぼ同一とみなせるものとする。
In both figures, 1 is a multilayer board to be tested having two circuit pattern layers 1a and lb with the same shape, 2 is a test board setting surface of the test equipment, and 3 is a dielectric layer 4 sandwiched between this setting surface 2. These are reference conductive plates arranged at opposing positions. This conductive plate 3 has one input end connected to one contact (
The capacitance measuring device (not shown) is connected to the other input end of a capacitance measuring device (not shown). Further, Sl represents the area of the upper circuit pattern layer 1a, S2 represents the area of the lower circuit pattern layer 1b, and S3 represents the area of the upper and lower circuit pattern layers 1a, lb.
represents the total area of the circuit pattern layers 1a and lb when they are short-circuited. Furthermore, d represents the thickness of the substrate 1, and d8 represents the thickness of the dielectric layer 4. Here, d represents the total area of the circuit pattern layers 1a and lb when In comparison, d2 is sufficiently thick (a, << aX), and in terms of capacitance measurement, each dimension between the reference conductive plate 3 and the circuit pattern layers la and lb can be considered to be almost the same.

第2図は、基板1の回路パターン層1at lbが同一
形状で、かつ相互に全体が重なり合っている場合を例示
している。したがってこの場合は5l−32=33とな
り、静電容量測定(回路パターン層1a (又はlb)
及び基準導電板3間の静電容量C+(又はCZ>測定)
だけでは両回路パターン層1a。
FIG. 2 illustrates a case where the circuit pattern layers 1at lb of the substrate 1 have the same shape and completely overlap each other. Therefore, in this case, 5l-32=33, and capacitance measurement (circuit pattern layer 1a (or lb)
and the capacitance C+ between the reference conductive plate 3 (or CZ>measurement)
Only both circuit pattern layers 1a.

lb間の短絡をチエツクできない。第3図は、基板1の
回路パターン層1a+ lbが同一形状であるが、それ
らが僅かずれて重なり合っている場合を例示する。この
場合は、51=32ではあるが、回路パターン層1a、
lbがずれて重なり合っているので、短絡時には、接触
子1と接触する回路パターン層1aの実質総合面積が回
路パターン層1a、lbの基板セット面2への投影面積
S3と等しくなる。この面積の増分(33−31)によ
って増加した容量値が、エラー判定容量値(基準値)よ
りも大きい場合はエラーとして検出されるが、電源ライ
ンやアースラインなどのように、広い面積の回路パター
ンでは、エラー判定容量値も太き(、エラー見落しの可
能性が大きくなってくる。
Unable to check for short circuit between lb. FIG. 3 exemplifies a case where the circuit pattern layers 1a+lb of the substrate 1 have the same shape, but are slightly shifted and overlapped. In this case, although 51=32, the circuit pattern layer 1a,
Since the circuit pattern layers 1a and 1b are shifted and overlapped, in the event of a short circuit, the substantial total area of the circuit pattern layer 1a in contact with the contactor 1 becomes equal to the projected area S3 of the circuit pattern layers 1a and 1b onto the board setting surface 2. If the capacitance value increased by this area increment (33-31) is larger than the error judgment capacitance value (reference value), it will be detected as an error. In the pattern, the error judgment capacitance value is also large (the possibility of overlooking an error increases).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし従来は、静電容量測定値が基準値に鉤して大きく
異なる場合に抵抗測定して短絡確認するにすぎず、基準
値と同−又は近似の場合には抵抗測定などによる確認は
していなかった。このため、第2図及び第3図のような
回路パターン層1a、 lb構造の場合の、それらの短
絡については検出されず、欠陥品を生じさせ得、信頼性
が劣るという問題点があった。
However, conventionally, when the capacitance measurement value differs significantly from the reference value, the short circuit is only confirmed by measuring the resistance, but when the capacitance measurement value is the same as or close to the reference value, confirmation by resistance measurement etc. is not performed. There wasn't. For this reason, short circuits in the circuit pattern layers 1a and lb structures as shown in FIGS. 2 and 3 are not detected, leading to defective products and poor reliability. .

本発明の目的は、多層基板のテストにおいて、回路パタ
ーン層相互間の短絡エラーの見落としがなく、信頼性を
向上した電気回路板テスト装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an electric circuit board testing device that does not overlook short-circuit errors between circuit pattern layers and has improved reliability in testing multilayer boards.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的は、測定された基準導電板と2つの導電回路層
各層との間の両静電容量値C+、Ctが相互に等しいか
、ほぼ等しいときには、静電容量測定に引き続いて両導
電回路層間の抵抗値測定する導電回路層間短絡検出手段
を備えることにより達成される。
The above purpose is that when both the capacitance values C+ and Ct between the measured reference conductive plate and each of the two conductive circuit layers are equal or almost equal, the capacitance measurement is followed by the measurement of the capacitance between the two conductive circuit layers. This is achieved by providing a means for detecting a short circuit between conductive circuit layers to measure the resistance value of the conductive circuit.

〔作用〕[Effect]

導電回路層間短絡検出手段は、多層基板のテスト時、測
定された基準導電板と2つの導電回路層各層との間の両
静電容量値C,,C,が相互に等しいか、ほぼ等しいと
き、その静電容量測定に引き続いて、両導電回路層間の
抵抗値を測定して、両導電回路層間の短絡箇所の有無を
検出し、短絡エラーの見落としを防止する。
The short-circuit detection means between conductive circuit layers detects when the capacitance values C, , C, between the measured reference conductive plate and each of the two conductive circuit layers are equal or almost equal when testing a multilayer board. Following the capacitance measurement, the resistance value between both conductive circuit layers is measured to detect the presence or absence of a short circuit between both conductive circuit layers, thereby preventing a short circuit error from being overlooked.

〔実施例〕〔Example〕

以下、図面を参照して本発明の詳細な説明する。第1図
は本発明による電気回路板テスト装置の一実施例を示す
構成図で、図中1 、 la、lb、 2〜4は各々第
2図、第3図と同様である。1cは上部回路パターン層
1aの端子部、1dは下部回路パターン層1bの端子部
である。5及び6は各々接触子、7は、テスト位置にセ
ットされた被テスト多N基板1上の所望位置(x、y座
標)に接触子5を移動し、接触させるX−Y位置決め装
置、8は同様に接触子5を移動し、接触させるX−Y位
置決め装置である。9は2つの接触子5.6間の抵抗を
測定する抵抗測定装置、10はいずれか一方の接触子、
ここでは接触子6と基準導電板3の間の静電容量を測定
する容量測定装置である。11は制御コンピュータで、
上記各装置7〜lOを従来装置と同様のシーケンスに従
って作動させ、多層基板1の基準導電板3と2つの回路
パターン層1a+ lb各層との間の両静電容量値C+
、Cz  (第2.3図参照)測定を行わせると共に、
次のような回路パターン層1a、 lb間短絡検出制御
を行わせる。すなわち、測定された上記両静電容量値C
,,C,が相互に等しいか、ほぼ等しいとき、静電容量
測定に引き続いて、前記回路パターン層1a、lb間の
抵抗値を抵抗測定装置9で測定して、両回路パターン層
la、  lb間の短絡箇所、換言すれば短絡エラーの
有無を検出させる。
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an electric circuit board testing apparatus according to the present invention, and in the figure, 1, 1a, 1b, and 2 to 4 are the same as in FIGS. 2 and 3, respectively. 1c is a terminal portion of the upper circuit pattern layer 1a, and 1d is a terminal portion of the lower circuit pattern layer 1b. 5 and 6 are contactors respectively; 7 is an X-Y positioning device that moves the contactor 5 to a desired position (x, y coordinates) on the multi-N board to be tested 1 set at the test position and brings it into contact; 8 is an XY positioning device that similarly moves the contactor 5 and brings it into contact. 9 is a resistance measuring device for measuring the resistance between two contacts 5.6, 10 is one of the contacts,
Here, it is a capacitance measuring device that measures the capacitance between the contactor 6 and the reference conductive plate 3. 11 is a control computer;
Each of the above devices 7 to 1O is operated according to the same sequence as the conventional device, and both capacitance values C+ between the reference conductive plate 3 of the multilayer substrate 1 and the two circuit pattern layers 1a+ lb each layer are
, Cz (see Figure 2.3), and
The following short-circuit detection control between the circuit pattern layers 1a and 1b is performed. That is, both the measured capacitance values C
,,C, are equal or almost equal to each other, following the capacitance measurement, the resistance value between the circuit pattern layers 1a and lb is measured by the resistance measuring device 9, and both circuit pattern layers la and lb are measured. In other words, the presence or absence of a short circuit error is detected.

次に、上述本発明装置の動作について説明するが、通常
のテスト動作(基準導電板3と回路パターンJila又
は1bとの間の静電容量値C,,CZの測定動作)につ
いては、従来装置の場合と特に変わるところはないので
、ここでは短絡エラー検出に関する動作についてのみ説
明する0図示基板1は、その上、下部回路パターン層1
a、 lbの平面形状が酷似し、かつそれらのほぼ全体
が相互に重なり合う構造となっている。また、基板1の
厚さdlが誘電体層4の厚さd2に比べて充分小さく(
d。
Next, the operation of the above-mentioned device of the present invention will be explained, but regarding the normal test operation (measurement operation of the capacitance values C, CZ between the reference conductive plate 3 and the circuit pattern Jila or 1b), the conventional device Since there is no particular difference from the case, only the operation related to short circuit error detection will be explained here.
The planar shapes of a and lb are very similar, and almost all of them overlap each other. Further, the thickness dl of the substrate 1 is sufficiently smaller than the thickness d2 of the dielectric layer 4 (
d.

<<aZ)、静電容量測定上、基準導電板3と回路パタ
ーン層1a、 lbまでの寸法がほぼ同一であるとみな
せるものとする。この場合、基準導電板3及び上部回路
パターン層18間の静電容量CIと、同導電板3及び下
部回路パターン層lb間の静電容量Cよとは、はとんど
差がない、ここで、回路パターン層1a、lb間が短絡
しているとすると、基準導電板3に対する回路パターン
層1a、 lbの実質的な総合面積はそれらの基板セッ
ト面2への投影面積に等しい。すなわち、短絡エラーが
あっても、増加する面積は、回路パターン層1a+ l
bの重なり合っていない部分の面積だけである。いま仮
に、増加した面積によって静電容量が5pF増大すると
し、静電容量測定によるエラー判定基準が基準容量値の
±15%とすると、基準導電板3から回路パターン層1
a (又はlb)までの間の静電容量CI(又はC2)
が33pFを越えるものである場合、静電容量測定のみ
では短絡エラーは発見不能となる。
<<aZ) In terms of capacitance measurement, it is assumed that the dimensions of the reference conductive plate 3 and the circuit pattern layers 1a and 1b are almost the same. In this case, there is almost no difference between the capacitance CI between the reference conductive plate 3 and the upper circuit pattern layer 18 and the capacitance C between the same conductive plate 3 and the lower circuit pattern layer lb. Assuming that there is a short circuit between the circuit pattern layers 1a and lb, the substantial total area of the circuit pattern layers 1a and lb relative to the reference conductive plate 3 is equal to their projected area onto the board setting surface 2. That is, even if there is a short circuit error, the increased area is the circuit pattern layer 1a+l
It is only the area of the non-overlapping portion of b. Now, suppose that the capacitance increases by 5 pF due to the increased area, and the error criterion for capacitance measurement is ±15% of the reference capacitance value.
capacitance CI (or C2) between a (or lb)
If it exceeds 33 pF, the short circuit error cannot be detected by capacitance measurement alone.

これは、特に広面積の回路パターンをもつ場合に起きや
すいが、いずれにしても本発明においては、容量測定装
置10による回路パターン111a、lb及び基準導電
板3間の両静電容量測定値C,,C。
This is particularly likely to occur when the circuit pattern has a wide area, but in any case, in the present invention, both capacitances measured between the circuit patterns 111a, lb and the reference conductive plate 3 by the capacitance measuring device 10 C ,,C.

が相互に等しいか、ほぼ等しい時には、静電容量測定に
よって良品と判定された場合であっても無条件で次のよ
うに動作する。すなわちこの場合には、制御コンピュー
タ11は、それまで上部回路パターン層1aの端子部1
cに接触子6が接触していたならば、この接触子6はそ
のままの位置に保持し、かつ位置決め装置7により、も
う一方の接触子5を下部回路パターン層1bの端子部1
d上方に移動させた後に下降させて、これと接触させる
。そして、抵抗測定装置9を作動させ、上、下部回路パ
ターン層1a、 lb間の抵抗を測定する。抵抗測定値
が0又はほぼOであるならば両回路パターン層1a、l
b間が短絡していることが分かり、短絡エラーの見落と
しが防止されることになる。
When they are equal or almost equal, the following operation occurs unconditionally even if the product is determined to be good by capacitance measurement. That is, in this case, the control computer 11 has previously controlled the terminal section 1 of the upper circuit pattern layer 1a.
If the contact 6 is in contact with the contact 6, the contact 6 is held in that position, and the positioning device 7 moves the other contact 5 to the terminal portion 1 of the lower circuit pattern layer 1b.
d After moving it upward, lower it and bring it into contact with this. Then, the resistance measuring device 9 is activated to measure the resistance between the upper and lower circuit pattern layers 1a and lb. If the measured resistance value is 0 or approximately O, both circuit pattern layers 1a, l
It can be seen that there is a short circuit between B and B, and it is possible to prevent a short circuit error from being overlooked.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、多層基板における導
電回路層相互間の短絡エラーの見落としが防止でき、テ
スト結果の信鯨性を向上することができるという効果が
ある。
As described above, according to the present invention, short-circuit errors between conductive circuit layers in a multilayer board can be prevented from being overlooked, and reliability of test results can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明装置の一実施例を示す構成図、第2図及
び第3図は従来装置の問題点を説明するための静電容量
測定時における多層基板セット部分の断面図である。 1・・・被テスト多層基板、la、lb・・・回路パタ
ーン層、2・・・被テスト基板セット面、3・・・基準
導電板、4・・・誘電体層、5.6・・・接触子、7,
8・・・接触子のX−Y位置決め装置、9・・・抵抗測
定装置、10・・・容量測定袋!、11・・・制御コン
ピュータ。
FIG. 1 is a block diagram showing one embodiment of the device of the present invention, and FIGS. 2 and 3 are cross-sectional views of a multilayer board set portion during capacitance measurement to explain the problems of the conventional device. DESCRIPTION OF SYMBOLS 1...Multilayer board to be tested, la, lb...Circuit pattern layer, 2...Test board setting surface, 3...Reference conductive plate, 4...Dielectric layer, 5.6...・Contactor, 7,
8... Contact X-Y positioning device, 9... Resistance measuring device, 10... Capacity measuring bag! , 11... control computer.

Claims (1)

【特許請求の範囲】[Claims] 1.2つの接触子と、この2つの接触子を、テスト位置
にセットされた被テスト電気回路板上の所望箇所に各々
独立して移動し、接触させる2つの接触子位置決め装置
と、前記2つの接触子相互間の抵抗を測定する抵抗測定
装置と、前記2つの接触子のうちの任意の一方と前記電
気回路板セット面に所定の誘電体層を挟んで対向する位
置に配設された基準導電板との間の静電容量を測定する
容量測定装置とを備えてなる電気回路板テスト装置にお
いて、導電回路を複数層有する被テスト電気回路板のテ
スト時、その電気回路板の一方の導電回路層と前記基準
導電板との間の静電容量値と、他方の導電回路層と前記
基準導電板との間の静電容量値が相互に等しいか、ほぼ
等しいときには静電容量測定に引き続いて、被テスト電
気回路板の前記一方の導電回路層と他方の導電回路層と
の間の抵抗値を前記抵抗測定装置で測定して、両導電回
路層間の短絡箇所の有無を検出する導電回路層間短絡検
出手段を具備することを特徴とする電気回路板テスト装
置。
1. Two contactors, two contactor positioning devices that independently move and contact the two contactors at desired locations on the electrical circuit board to be tested set at the test position; a resistance measuring device for measuring the resistance between the two contacts; and a resistance measuring device disposed at a position facing any one of the two contacts and the electric circuit board set surface with a predetermined dielectric layer in between. In an electric circuit board testing device that is equipped with a capacitance measuring device that measures the capacitance between a reference conductive plate and a reference conductive plate, when testing an electric circuit board under test that has multiple layers of conductive circuits, one of the electric circuit boards is When the capacitance value between the conductive circuit layer and the reference conductive plate and the capacitance value between the other conductive circuit layer and the reference conductive plate are equal or almost equal, capacitance measurement is performed. Subsequently, the resistance value between the one conductive circuit layer and the other conductive circuit layer of the electrical circuit board to be tested is measured by the resistance measuring device to detect the presence or absence of a short circuit between the two conductive circuit layers. An electric circuit board testing device characterized by comprising circuit layer short circuit detection means.
JP63008544A 1988-01-20 1988-01-20 Apparatus for testing electric circuit board Pending JPH01185452A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63008544A JPH01185452A (en) 1988-01-20 1988-01-20 Apparatus for testing electric circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63008544A JPH01185452A (en) 1988-01-20 1988-01-20 Apparatus for testing electric circuit board

Publications (1)

Publication Number Publication Date
JPH01185452A true JPH01185452A (en) 1989-07-25

Family

ID=11696084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63008544A Pending JPH01185452A (en) 1988-01-20 1988-01-20 Apparatus for testing electric circuit board

Country Status (1)

Country Link
JP (1) JPH01185452A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0682509A (en) * 1992-02-28 1994-03-22 Internatl Business Mach Corp <Ibm> Device and method for testing circuit
JP2009080121A (en) * 2008-10-27 2009-04-16 Hioki Ee Corp Method and device for testing circuit board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0682509A (en) * 1992-02-28 1994-03-22 Internatl Business Mach Corp <Ibm> Device and method for testing circuit
JP2009080121A (en) * 2008-10-27 2009-04-16 Hioki Ee Corp Method and device for testing circuit board

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