JPH01184967A - Josephson element and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent an element from characteristics deterioration attributable to diffusion or the like and to facilitate its application to an enhanced integration package by a method wherein a material (Nb) same as the one constituting a junction electrode is employed as an etching stopper. CONSTITUTION:On an Si semiconductor substrate 10, Nb is deposited for the building of a base electrode 11, a 5nm-thick Al film is deposited, and then thermal oxidation is accomplished for a 1nm-thick layer out of the 5nm-thick Al film to be converted into AlOX for the formation of a tunnel barrier layer 12. A process follows wherein Nb is deposited 25nm thick for the construction or a counter electrode 13. The SNAP technique is then applied for the definition of a junction area. That is, a resist 21 to serve as a mask is formed on a region J1 for a junction, which is followed by anodization. In this process, the section not covered by the resist 21 or the region near the junction is converted into Nb2O5 (anode oxide film 14) which is insulatory in nature, self-alignedly to the resist 21. Finally, the resist 21 is removed and Nb is deposited on the entire wafer surface for the formation of a conductive layer 15 to serve as an etching stopper.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a Josephson element and a method for manufacturing the same, particularly a technique for forming a junction in an element using an Nb-based Josephson junction, which prevents characteristic deterioration due to diffusion etc. In order to facilitate application to high integration, a first conductive layer made of niobium, a first insulating layer exhibiting weak superconductivity, and a second conductive layer made of niobium are sequentially deposited on a semiconductor substrate. a first step of depositing, a second step of anodizing the deposited stack so that a region where a bond is to be formed remains, and depositing a third conductive layer of niobium. a third step, a fourth step of leaving a second region including the region where the bond is to be formed and larger than the third conductive layer as a conductive layer; and a fifth step of removing a portion corresponding to a part of the second region by reactive ion etching after depositing the second insulating layer, and selecting a reactive gas used for the etching to remove the portion corresponding to a part of the second region. The configuration is such that only the second insulating layer can be removed.

[Industrial application field]

The present invention relates to a Josephson device and a method for manufacturing the same, and particularly to a technique for forming a niobium (Nb)-based Josephson junction in a device using the same.

In recent years, there has been a demand for ultra-high-speed calculations, such as image processing in nuclear power, nuclear fusion, weather, satellite communications, etc., logical simulation in the fields of computational physics such as aircraft design and molecular science, and the development of new generation computers. As a result, there is a strong social demand for the development of ultra-high-speed digital devices as a technology to meet this demand from a hardware perspective. The device using the Josephson element described above is one of the ultrahigh-speed digital devices that meet such social demands.

A Josephson device has a structure in which two superconductors are coupled through a weak coupling region (a region with weak superconductivity), and the macroscopic quantum effect unique to superconductivity is generated by an externally applied magnetic field or It is a device that can be controlled by voltage, and has extremely strong nonlinearity due to macroscopic quantum effects, high-speed response, and low noise. Therefore, Josephson elements with these features can be used in a wide range of applications, including digital applications, and have already been put to practical use in analog applications such as voltage standards, high-sensitivity magnetometers, and millimeter-wave detection mixers. has reached the stage of

[Conventional technology]

As an example of technology for forming Nb-based Josephson junctions, S
N'A P (Selective Niobium
AnordizaLionProcess) method is known (Reference: 11. Kroger.

L, N, Sm1th and D, W, Jillie,
Appl, Phys, Lett, 39°280 (1
981)).

This 5NAP method creates a sandwich structure of a superconductor (Nb) as a lower electrode, a tunnel barrier as a weak coupling region, and a superconductor (Nb) as an upper electrode all at once on the entire wafer surface. A region to be formed in a vacuum atmosphere and then to form a bond (hereinafter simply referred to as "bond")
This is a method to determine.

In this case, the junction is determined by insulating the upper electrode other than the portion corresponding to the junction by anodizing. Also, when performing anodic oxidation, resist or patterned silicon dioxide (Si) can be used as a mask to cover the bond.
O2) thin film is used.

However, in the element isolation by anodic oxidation used in the 5NAP method, the anodic oxide film grows laterally and also extends inside the bonding mask. Therefore, when the bond becomes small, it becomes difficult to accurately determine the bond area. This means that when many elements are formed on the same wafer, it becomes difficult to make the bonding area of each element uniform, which puts constraints on the circuit when integrated circuits are created. .

As a means to deal with this problem, a method has been proposed in which elements are separated by etching.

An example of this is S N I P (Self-aligned
ed Niobium (nitride) l5ola
tion process) method (References HA, 5hoji et al+ IEEE T
rans, onMagnetics, MAG-19,
827 (1983)).

In this 5NIP method, reactive ion etching (RrE) is used to separate the junction from the sandwich structure formed over the entire wafer, namely the bottom electrode (Nb), tunnel barrier and top electrode (Nb). It will be done. In this case, the mask used during etching is not removed, but is used as a mask for lift-off, and
An iO insulating thin film is deposited, and the periphery of the junction is insulated and isolated using a self-alignment line.

In this way, the 5NIP method uses RIE for element isolation, that is, junction isolation, so it has the advantage that the junction area can be determined with high precision compared to the 5NAP method. However, on the other hand, the insulation around the junction is Since this is done using a vapor-deposited film, it cannot be said to be preferable from the viewpoint of reliable insulation compared to a 5in2 film which has better insulation resistance. Therefore, if possible, it is preferable to use an ordinary SiO□ film as a film for insulating the periphery of the junction.

In addition, as another method for forming Nb-based junctions, SNE
P (Selective Niobium Etc.
Hing Process) method is known (References: M, Gurvitch, M, Hachi, Was-hing
Lon and Il, 8, Huggins,
Appl, Phys, Lett, 42+472(
1983) ).

The 5NEP method uses RIE similar to the 5NIP method when separating the junctions, and uses anodic oxidation similar to the 5NAP method when insulating the periphery of the junctions. Therefore, this 5
The NEP method, like the 5NAP method, has problems due to the lateral growth of the anodic oxide film.

The present inventor proposed one method for addressing the problems associated with the formation of Nb-based junctions described above (Reference B
S, Morohashi et at, Appl, P
hys, Lett.

■, 254 (1986)). Below, this method will be described as SA
It is called the C (Self-Igned Contact) method.

This SAC method first determines the bonding area using the 5NEP method for a sandwich structure formed over the entire wafer, that is, a base electrode (Nb), a tunnel barrier, and a counter electrode (Nb), and then removes the resist. After that,
Deposit the AI film over the entire surface, leave a portion larger than the bonding area and anodize the surrounding area, and further,
The steps include processing a base electrode portion, depositing an insulating layer over the entire surface of the wafer, and forming contact holes by RIE. In this case, the above-mentioned A
The I film is then etched by RIE method.
It has the function of suppressing the etching from reaching the inside of the film, that is, it functions as an etching stopper.

[Problem that the invention attempts to solve]

FIG. 7 illustrates some of the steps in the SAC method described above. In the figure, 70 is a Si semiconductor substrate, 71 is an Nb base electrode, 72 is an AIO tunnel barrier layer, 73 is a Nb counter electrode, 74 is an anodized NbzOs film, and 75 is an etching stopper film. ,
Reference numeral 76 indicates a resist.

According to this SAC method, A1 is used as an etching stopper.
Since the film 75 is used, as shown in FIG.
73, resulting in the disadvantage that the characteristics of the Josephson element deteriorate. Furthermore, as shown in FIG. 2B, the A1 film mainly relies on lift-off, so there is also the problem that it is difficult to apply to large-scale integrated circuits.

The present invention was created in view of the above-mentioned problems in the prior art, and provides a Josephson device and method for manufacturing the same that can prevent characteristic deterioration caused by diffusion etc. and facilitate application to high integration. is intended to provide.

[Means and effects for solving the problem] The problem with the above-mentioned conventional technology is that the bonding electrode is made of the same material (Nb).
This problem can be solved by using as an etching stopper.

According to one aspect of the invention, a first conductive layer made of niobium is formed on a semiconductor substrate, and a weak superconductor is formed on the first conductive layer in a region where a junction is to be formed. a first insulating layer exhibiting conductivity; a second conductive layer made of niobium formed on the first insulating layer; and a first insulating layer and a second conductive layer formed on the first conductive layer. a second insulating layer formed so as to sandwich the conductive layer; and a second region that includes the region where the bond is to be formed and is larger than the region, on the second conductive layer and the second insulating layer. and a third insulating layer formed to have a contact hole through which a fourth conductive layer can come into contact with the third conductive layer. A Josephson device is provided.

According to another aspect of the present invention, a first conductive layer made of niobium, a first insulating layer exhibiting weak superconductivity, and a second conductive layer made of niobium are sequentially deposited on a semiconductor substrate. a second step of anodizing the deposited laminate to leave a region where a bond is to be formed; and a third step of depositing a third conductive layer of niobium. a second conductive layer that includes a region where the junction is to be formed with respect to the third conductive layer and is larger than the region;
a fourth step of leaving a region as a conductive layer; and after depositing a second insulating layer over the entire surface, a portion corresponding to a part of the second region is removed by reactive ion etching. A method for manufacturing a Josephson device is provided, comprising a fifth step, and selecting a reactive gas used in the etching so that only the second insulating layer can be removed.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings. .

〔Example〕

FIG. 1 shows a cross-sectional view of the structure of a Josephson element as an embodiment of the present invention.

In FIG. 1, 10 is a semiconductor substrate made of silicon (Si), 11 is a base electrode made of Nb and has superconductivity, and 12 is a tunnel as a weak coupling region (region with weak superconductivity) made of AIO. 13 is a superconducting counter electrode made of Nb, 14 is an anodic oxide film as an insulating layer made of Nb2O5, 15 is a conductive layer made of Nb and functions as an etching stopper, 16 is Nb.
Anodic oxide film as an insulating layer consisting of 2O5, 17 is 5i
An insulating layer made of Oz, 18 a wiring layer made of Nb, Jl
is iJt which defines the size of the junction (Josephson junction)
and J2 represent the area (Jz>J+) that defines the size of the etching stopper.

Next, a method for manufacturing the Josephson element shown in FIG. 1 will be explained with reference to process diagrams in FIGS. 2(a) to 2(g).

First, in step (a), in a vacuum atmosphere, by DC magnetron sputtering,
After depositing 200 nm of Nb to form the base electrode 11, and then depositing 5 nm of AI, thermal oxidation converts about 1 nm of the 5 nm into Al0X to form the tunnel barrier layer 12, and further deposits 25 r+a of Nb.
The counter electrode 13 is formed by depositing the amount of the opposite electrode 13.

Next, in step (b), the bonding area is determined using the 5NAP method. That is, after a resist 21 is formed as a temporary resist on the region Jl where a junction is to be formed, anodic oxidation is performed. As a result, the region around the junction with the resist 1-21 in a self-aligned manner (self-alignment), that is, the portion not covered with the resist 21, is converted to NbzOs having insulating properties (anodic oxide film 14).

Next, in step (c), after removing the resist 21, Nb is deposited to a thickness of about 25 nm over the entire surface of the wafer to form a conductive layer 15 as an etching stopper.

Next, in step (d), the same method as in step (b) (SNAP
After forming a resist 22 as a mask on a second region J2 that includes the region J in which a junction is to be formed and is larger than the region J2 by a method (method), anodic oxidation is performed.

As a result, the surrounding area is converted into Nb2O5 having an insulating property (anodic oxide film 16) in a self-aligned manner with the resist 22 (self-alignment).

Next, in step (e), after removing the resist 22, cp
A base electrode part is formed by the RIE method using a mixed gas of a+sχ0□, and then a 5in2 electrode is formed over the entire wafer surface.
A thickness of approximately 0.00 nm is deposited to form an insulating layer 17.

Next, in step (f), after patterning the resist 23 so that a portion of the Sin layer 17 corresponding to a part of the second region J2 is exposed, CHF3 + 30χ
The 5iOzAW was obtained by the RIE method using a mixed gas of 0□.
17 is removed by etching. The etching rate in this case is selected so that the SiO□ layer 17 is easily etched, but the underlying conductive layer 15 made of Nb is hardly etched. Specifically, since the etching rate can be controlled by the etching process, the gas is switched to only CHh just before the etching process reaches the conductive layer 15. It is known that Nb is hardly etched by CHh gas alone. Therefore, by switching the gas in this way, as shown in Figure Cf>, the shape is created such that the Sin2 layer 17 is etched cleanly, but the underlying conductive layer 15 made of Nb is hardly etched. Obtainable.

Finally, in the process axis), Nb is deposited over the entire surface of the wafer and patterned into a predetermined shape to form the wiring layer 18.

In the process of this embodiment described above, since the etching stopper 15 is made of the same material (Nb) as the bonding electrode (in this case, the counter electrode 13), diffusion etc. as seen in the conventional type are avoided. It is possible to prevent characteristic deterioration caused by this. Further, since lift-off is not used when forming the counter electrode 13, it is possible to miniaturize the bonding area, thereby easily adapting to high integration.

Furthermore, the reaction gas for etching used in step (f) is selected so that the 5102 layer 17 is easily etched, but the underlying conductive layer 15 made of Nb is hardly etched. The Nb2O5 film formed by oxidation does not need to be formed thickly. 5NAP
In this case, it is sufficient for the Nb film as the counter electrode 13 to have a thickness of about 25 nm, and when the anode applied voltage is set to about 25 V, the Nb film is
The film (25 nm) is converted to NbzOs (50 nm). If the applied voltage were to be about 40 V, there is a risk that the junction would be destroyed, but in this example, due to the presence of the etching stopper 15 made of Nb, there is no need to increase the applied voltage, and as mentioned above, the applied voltage is about 25 V. Voltage is sufficient.

In the above embodiment, the bonding area is determined based on the 5NAP method (see FIG. 2(b)), but it may be determined based on the 5NEP method. An example of a manufacturing process using the 5NEP method is shown in FIGS. 3(a) to 3(d).

Step (a) in FIG. 3 corresponds to step (a) in FIG. In step (b) of FIG. 3, a resist 21 as a mask is formed on the region J1 where a junction is to be formed. In step (c), R using a mixed gas of CF4+5χ02
By the IE method, the Nb layer 1 not covered with the resist 21 is
3 is removed by etching, and in step (d),
Anodic oxidation is performed with resist 21 remaining. As a result, the portion not covered with the resist 21 is converted to Nb2O5 having insulating properties (anodic oxide film 14a).

The subsequent manufacturing steps are the same as steps (c) to (g) in FIG. 2, so their explanation will be omitted.

In addition, an example using the above-mentioned 5NAP method (Fig. 2 (b)
), we have explained an example in which the bonding area J is determined by one-time anodic oxidation;
As shown in a) and (b), the junction area may be determined by two anodic oxidations.

In Fig. 4, (a) corresponds to the top view of the cross-sectional view in Fig. 2 (b) when viewed from above, and (b) shows the state when the second anodic oxidation is performed from above. This is a schematic diagram of Tamo.

In the figure, 21a is a resist as a mask (Fig. 2(b)
), 21b represents a resist formed in a direction crossing the resist 21a, and the hatched portion represents the anodic oxide film 14.

In this way, by performing anodic oxidation twice using two masks that intersect with each other, the bonding area can be determined with high precision.

Similarly, in the embodiment using the 5NEP method shown in FIGS. 3(a) to 3(d), an example was explained in which the bonding area J1 was determined by one anodic oxidation. 5 As shown in Figures (a) and (b), 2
The bonding area may also be determined by anodic oxidation.

In FIG. 5, (a) corresponds to a top view of the cross-sectional view in FIG. 3(d) when viewed from above, and (b) shows the state after the second RIE and anodization. This is a schematic view from above. In the figure, 21c is a resist as a mask.
(corresponding to the resist 21 in FIG. 3(d)), 21d indicates a resist formed in a direction intersecting the resist 2IC, and the portion indicated by hunting represents the anodic oxide film 14a.

Further, in each of the embodiments described above (for example, see FIG. 2(d)), an example was explained in which the area J2 of the etching stopper 15 is determined by anodic oxidation.
The area J2 may be determined by RIE as shown in FIGS. (a) to (c).

In FIG. 6, step (a) corresponds to step (c) in FIG. In the step (b) of FIG. 6, a resist 22 is formed as a mask on the region J2, and in the step (C), the portions of the NbN13 not covered with the resist 22 are etched away using the RIE method. Since the subsequent steps are similar to steps (e) to (g) in FIG. 2, their explanation will be omitted. However, in this case, an element having a structure without the anodic oxide film 16 is completed.

Further, in each of the above-described embodiments, the case where AIO is used as the material constituting the tunnel barrier layer 12 has been described, but the material is not limited to this, and for example, ZrL + YbOx + Ta0
X etc. may also be used.

〔Effect of the invention〕

As explained above, according to the Josephson element and its manufacturing method of the present invention, by forming the etching stopper from the same material as the bonding electrode, that is, Nb,
It is possible to prevent characteristic deterioration due to diffusion, etc., to miniaturize the junction area, and to easily adapt to high integration.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of a Josephson device as an embodiment of the present invention, FIGS. 2(a) to (g) are manufacturing process diagrams of the device in FIG. 1, and FIGS. 3(a) to (d) is a diagram for explaining the manufacturing process of a modification of the element shown in FIG. 1, and FIGS. 4(a) and (b) are diagrams for explaining a modification of the process of FIG. 2(b). 5(a) and (b) are top views for explaining a modification of the process of FIG. 3(d), and FIGS. 6(a) to (c) are top views of the element of FIG. 1. 7(a) and 7(b) are diagrams for explaining the manufacturing process of another modification. (Explanation of symbols) 10...Semiconductor substrate (Si), 11...Base electrode (Nb), 12...Tunnel layer (810)
X), 13... Counter electrode (Nb), 14A4a...-Anodized film (NbzOs), 15...
・Etching stopper (Nb), 16... Anodic oxide film (NbzOs), 17... Insulating layer (SiO□), 1
8... Wiring layer (Nb), 21.2'la to 21d, 22.23-mask (resist), J,... region where a junction is to be formed, J2... region J, larger second area. A cross-sectional view showing the structure of a Noyosefson device as an embodiment of the present invention.・
Counter electrode (Nb) 14... Anodic oxide film (Nb205) 15... Etching hole f (Nb) 16...
Anodic oxide film (Nb205) 17... Insulating layer (Si02) 18°°° Wiring layer (Nb) 43'12 Manufacturing process diagram for the device in Figure 1 Figure 2 i2B Manufacturing process diagram for the device in Figure 1 FIG. 3: A top view for explaining a modification of the process in FIG. illustration

Claims (1)

[Claims] 1. A first conductive layer (11) made of niobium formed on a semiconductor substrate (10), and a region (J_1) on which a junction is to be formed on the first conductive layer. The formed first insulating layer (12) exhibiting weak superconductivity
), a second conductive layer (13) made of niobium formed on the first insulating layer, and sandwiching the first insulating layer and the second conductive layer on the first conductive layer. The formed second insulating layer (14,
14a), and a second region (J_2) made of niobium formed on the second conductive layer and the second insulating layer over a second region (J_2) that includes the region where the junction is to be formed and is larger than the region. a third conductive layer (15); and a third insulating layer (17) formed to have a contact hole through which a fourth conductive layer (18) can come into contact with the third conductive layer. Josephson element to prepare. 2. A first conductive layer (11) made of niobium and a first insulating layer (12) exhibiting weak superconductivity on a semiconductor substrate (10).
) and niobium (13), and anodizing (14) so that a region (J_1) in which a bond is to be formed remains in the deposited stack. , 14a); a third step of depositing a third electrically conductive layer (15) of niobium; a fourth step of leaving a second region (J_2) larger than the second region in the state of a conductive layer; and after depositing a second insulating layer (17) over the entire surface, a part of the second region a fifth step of removing a portion corresponding to the second insulating layer by reactive ion etching, and selecting a reactive gas used in the etching so that only the second insulating layer can be removed. Method. 3. In the second step, the area where the bond is to be formed (J_1
) After forming the mask (21; 21a, 21b), the step of anodizing (14) is performed at least once.
3. The method of manufacturing a Josephson device according to claim 2, comprising: 4. In the second step, the area where the bond is to be formed (J_1
) and removing the second conductive layer (13) by reactive ion etching after forming a mask (21; 21c, 21d) to define the mask (21; 21c, 21d); and anodizing (14a) with the mask remaining. 3. The method of manufacturing a Josephson device according to claim 2, further comprising the step of performing the following steps at least once each.