JPH01181444A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH01181444A JPH01181444A JP63002867A JP286788A JPH01181444A JP H01181444 A JPH01181444 A JP H01181444A JP 63002867 A JP63002867 A JP 63002867A JP 286788 A JP286788 A JP 286788A JP H01181444 A JPH01181444 A JP H01181444A
- Authority
- JP
- Japan
- Prior art keywords
- region
- wiring
- superconducting
- thin film
- compound
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 150000001875 compounds Chemical class 0.000 claims abstract description 15
- 239000010409 thin film Substances 0.000 claims abstract description 10
- 230000007704 transition Effects 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 8
- 230000020169 heat generation Effects 0.000 abstract description 2
- 239000002887 superconductor Substances 0.000 abstract description 2
- 230000001747 exhibiting effect Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229940125782 compound 2 Drugs 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置、特にその配線構造と製造方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and particularly to its wiring structure and manufacturing method.
従来の技術
第2図a −dは従来の配線構造を形成する方法を説明
する工程断面図である。第2図&に示すように、半導体
基板1o1上に配線材料例えばアルミニウム等の金属1
02を形成した後、レジスト103をコートし、マスク
104を用い光露光105を行い(第2図b)、現像を
することによりレジスト103を第2図Cのようにパタ
ーン形成する。次に、レジスト1o3をマスクに配線材
料102をエツチングし、配線パターンを形成する(第
2図d)。BACKGROUND ART FIGS. 2a to 2d are process cross-sectional views illustrating a method of forming a conventional wiring structure. As shown in FIG.
After forming 02, a resist 103 is coated, light exposure 105 is performed using a mask 104 (FIG. 2B), and development is performed to form a pattern on the resist 103 as shown in FIG. 2C. Next, the wiring material 102 is etched using the resist 1o3 as a mask to form a wiring pattern (FIG. 2d).
・発明が解決しようとする課題
半導体装置が微細化され、高集積化されるに従い、従来
の技術における配線構造においては、配線の抵抗が問題
となり、それを解決するために配線材料の低抵抗化が図
られているが、材料の安定化、加工技術の難しさ等で実
現は困難になっている。・Problems to be solved by the invention As semiconductor devices become smaller and more highly integrated, interconnect resistance becomes a problem in interconnect structures in conventional technology. However, it is difficult to achieve this goal due to difficulties in stabilizing the materials and processing technology.
一方、素子の高密度化に伴い、配線の多層化が図られて
いるが、配線構造の段差により、形成の難しさや、断線
、短絡等の発生による信頼性の低下等に問題があった。On the other hand, as the density of devices increases, wiring is multilayered, but there are problems such as difficulty in formation due to steps in the wiring structure and reduction in reliability due to occurrence of disconnections, short circuits, etc.
本発明は従来の問題点を解決すべく、抵抗が低く、信頼
性の高い配線構造を提供するものである。The present invention provides a wiring structure with low resistance and high reliability in order to solve the conventional problems.
課題を解決するための手段
本発明は、半導体基板表面上に形成された超電導性化合
物薄膜の一部を、その化合物の成分比が異なるものにし
て、超電導転移臨界温度を異ならせ、所定の温度範囲に
おいてその領域を超電導状態として配線領域とし、他の
領域を常電導状態として非配線領域として用いるように
する。Means for Solving the Problems The present invention makes a part of a superconducting compound thin film formed on the surface of a semiconductor substrate have a different component ratio of the compound, so that the critical temperature for superconducting transition is different, and the superconducting transition critical temperature is adjusted to a predetermined temperature. Within the range, that region is set to a superconducting state and used as a wiring region, and the other region is set to a normal conducting state and used as a non-wiring region.
作用
超電導性を示す化合物の中に、その成分比が異なる時に
超電導転移温度が変わるものが知られている。半導体基
板上に形成されたこのような性質を示す化合物薄膜の一
部にその一成分である原子をイオン化して注入すること
により、転移温度の異なる領域を形成できる。この領域
のみが超電導状態となる所定の温度範囲において、配線
領域として用いることができる。It is known that among compounds exhibiting functional superconductivity, there are compounds whose superconducting transition temperature changes when their component ratios differ. Regions with different transition temperatures can be formed by ionizing and implanting atoms, which are one of the components, into a portion of a thin compound film exhibiting such properties formed on a semiconductor substrate. In a predetermined temperature range in which only this region becomes superconducting, it can be used as a wiring region.
実施例
第1図は本発明の一実施例を示す工程断面図及び構造断
面図である。Embodiment FIG. 1 is a process sectional view and a structural sectional view showing an embodiment of the present invention.
第1図aに示すように、半導体基板1上に超電導性を示
す化合物2を形成する。例えばYBaCuO系薄膜を電
子ビーム蒸着等により形成する。As shown in FIG. 1a, a compound 2 exhibiting superconductivity is formed on a semiconductor substrate 1. For example, a YBaCuO thin film is formed by electron beam evaporation or the like.
次に第1図すに示すように、マスク3を用いて化合物の
一成分を成す原子のイオン種4を化合物薄膜2中に注入
を行い、異なる成分比の領域5を形成する。例えばYB
aCuO系の場合には、酸素を注入する。この後、必要
により熱処理を行ってもよい。Next, as shown in FIG. 1, ion species 4 of atoms constituting one component of the compound are implanted into the compound thin film 2 using a mask 3 to form regions 5 having different component ratios. For example, YB
In the case of aCuO system, oxygen is implanted. After this, heat treatment may be performed if necessary.
イオン注入された領域の超電導転移温度T1は他の領域
の転移温度T2よりも高く、下記に示す温度範囲で、
T、> T > T2
イオン注入領域5は超電導状態、他の領域は常電導状態
を示す。この温度範囲ではイオン注入領域は抵抗がゼロ
となシ、電流はほとんどこの領域を流れる。The superconducting transition temperature T1 of the ion-implanted region is higher than the transition temperature T2 of other regions, and in the temperature range shown below, T, > T > T2 The ion-implanted region 5 is in a superconducting state, and the other regions are in a normal conducting state. shows. In this temperature range, the ion implantation region has zero resistance and most of the current flows through this region.
以上のような方法で形成した配線構造を第1図Cに示し
である。配線と成す領域5に選択的にイオン注入されて
いる。The wiring structure formed by the above method is shown in FIG. 1C. Ions are selectively implanted into the region 5 forming the wiring.
上記配線構造において、配線を超電導体で形成すること
により、配線抵抗をゼロにでき、半導体集積回路の動作
速度を速め、発熱を小さくでき、素子の性能を大幅に向
上させることができる他、配線構造が平坦であるため、
素子の信頼性も高められる。In the above wiring structure, by forming the wiring with a superconductor, the wiring resistance can be reduced to zero, the operating speed of the semiconductor integrated circuit can be increased, heat generation can be reduced, and the performance of the element can be greatly improved. Because the structure is flat,
The reliability of the device can also be improved.
発明の効果
本発明による半導体基板表面上に形成された超電導性化
合物薄膜の一部を、その化合物の成分比が異なるものに
して、超電導転移臨界温度を異ならせ、所定の温度範囲
においてその領域を超電導状態として配線領域とし、他
の領域を常電導状態として非配線領域として用いること
により、平易なプロセスと平坦な構造により配線抵抗が
小さく信頼性の高い配線構造を実現でき、その実用的効
果は大きい。Effects of the Invention Parts of the superconducting compound thin film formed on the surface of a semiconductor substrate according to the present invention are made to have different component ratios of the compound, so that the critical temperature for superconducting transition is varied, and the region is controlled within a predetermined temperature range. By using the wiring area as a superconducting state and the other area as a non-wiring area in a normal conducting state, it is possible to realize a highly reliable wiring structure with low wiring resistance through a simple process and a flat structure, and its practical effects are as follows. big.
第1図a、bは本発明における一実施例を説明する工程
断面図、第1図Cは同実施例の配線構造を示す斜視図、
第2図a −dは従来の配線パターンを形成する工程断
面図である。
1・・・・・・半導体基板、2・・・・・・超電導性化
合物薄膜、4・・・・・・イオン種、5・・・・・・配
線パターン。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
第2図1A and 1B are process sectional views explaining one embodiment of the present invention, FIG. 1C is a perspective view showing the wiring structure of the same embodiment,
FIGS. 2a to 2d are cross-sectional views of the process of forming a conventional wiring pattern. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Superconducting compound thin film, 4... Ion species, 5... Wiring pattern. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2
Claims (2)
膜より成り、前記薄膜中に成分比の異なる領域を有し、
前記各領域の超電導転移温度が異なるものとし、所定の
温度範囲において、一方の前記領域を超電導状態として
配線領域とし、他方の領域を常電導状態として非配線領
域とする半導体装置。(1) Consisting of a superconducting compound thin film formed on the surface of a semiconductor substrate, having regions with different component ratios in the thin film,
A semiconductor device in which each of the regions has a different superconducting transition temperature, and within a predetermined temperature range, one of the regions is in a superconducting state and serves as a wiring region, and the other region is in a normal conducting state and serves as a non-wiring region.
膜中の一部に、前記化合物の一成分を成す原子のイオン
種を注入することにより、前記薄膜中に成分比の異なる
領域を形成して配線領域と非配線領域とを形成する半導
体装置の製造方法。(2) By implanting ion species of atoms constituting one component of the compound into a part of the superconducting compound thin film formed on the surface of the semiconductor substrate, regions with different component ratios are formed in the thin film. A method of manufacturing a semiconductor device in which a wiring region and a non-wiring region are formed by using the same method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63002867A JPH01181444A (en) | 1988-01-08 | 1988-01-08 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63002867A JPH01181444A (en) | 1988-01-08 | 1988-01-08 | Semiconductor device and its manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01181444A true JPH01181444A (en) | 1989-07-19 |
Family
ID=11541311
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63002867A Pending JPH01181444A (en) | 1988-01-08 | 1988-01-08 | Semiconductor device and its manufacture |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01181444A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01199453A (en) * | 1988-02-04 | 1989-08-10 | Fujitsu Ltd | Manufacture of superconductor element |
JPH0284732A (en) * | 1988-02-04 | 1990-03-26 | Fujitsu Ltd | Manufacture of superconductor element |
JPH0355889A (en) * | 1989-07-25 | 1991-03-11 | Furukawa Electric Co Ltd:The | Manufacture of superconducting multilayered circuit |
US5646096A (en) * | 1990-11-01 | 1997-07-08 | Sumitomo Electric Industries, Ltd. | Process for fabrication superconducting wiring lines |
US5912503A (en) * | 1997-01-02 | 1999-06-15 | Trw Inc. | Planar in-line resistors for superconductor circuits |
-
1988
- 1988-01-08 JP JP63002867A patent/JPH01181444A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01199453A (en) * | 1988-02-04 | 1989-08-10 | Fujitsu Ltd | Manufacture of superconductor element |
JPH0284732A (en) * | 1988-02-04 | 1990-03-26 | Fujitsu Ltd | Manufacture of superconductor element |
JPH0355889A (en) * | 1989-07-25 | 1991-03-11 | Furukawa Electric Co Ltd:The | Manufacture of superconducting multilayered circuit |
US5646096A (en) * | 1990-11-01 | 1997-07-08 | Sumitomo Electric Industries, Ltd. | Process for fabrication superconducting wiring lines |
US5912503A (en) * | 1997-01-02 | 1999-06-15 | Trw Inc. | Planar in-line resistors for superconductor circuits |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4093503A (en) | Method for fabricating ultra-narrow metallic lines | |
US5411937A (en) | Josephson junction | |
CA2052380C (en) | Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material and method for manufacturing the same | |
JPH01181444A (en) | Semiconductor device and its manufacture | |
JP3382588B2 (en) | Use of ion implantation to create normal layers during superconducting-normal-superconducting Josephson junctions | |
US5637555A (en) | Method for manufacturing a three-terminal superconducting device having an extremely short superconducting channel | |
JPS63291436A (en) | Manufacture of semiconductor device | |
US6352741B1 (en) | Planar high temperature superconductive integrated circuits for using ion implantation | |
JPH0613731A (en) | Superconducting super-small electronic circuit based on microlithographic patterning of superconductive compound and related material | |
Nakagawa et al. | Fabrication process for Josephson computer ETL-JC1 using Nb tunnel junctions | |
Kingston et al. | Photolithographically patterned thin-film multilayer devices of YBa/sub 2/Cu/sub 3/O/sub 7-x | |
JP2835244B2 (en) | Superconducting device and manufacturing method thereof | |
JPS63265474A (en) | Manufacture of superconductng electronic circuit | |
EP0281156B1 (en) | Semiconductor-coupled three-terminal superconducting device having a junction gate structure | |
JP2641970B2 (en) | Superconducting element and fabrication method | |
US3450534A (en) | Tin-lead-tin layer arrangement to improve adherence of photoresist and substrate | |
JP3049125U (en) | Superconducting conductor with non-superconducting phase geometrically distributed | |
JPH01101679A (en) | Formation of superconducting circuit | |
JPS63304646A (en) | Formation of superconductor thin film pattern | |
JP2994190B2 (en) | High-temperature superconducting thin film structure and method for producing the same | |
JP2641974B2 (en) | Superconducting element and fabrication method | |
JP2641973B2 (en) | Superconducting element and manufacturing method thereof | |
Harris et al. | Formation of extremely narrow metallic lines | |
JPH05206532A (en) | Method of manufacturing josephson element | |
JPH0444250A (en) | Manufacture of semiconductor device |