JPH01181329A - Flexible address decoder for cpu peripheral circuit - Google Patents

Abstract

PURPOSE:To increase freely the expansion system by preserving a circuit data of a logic cell array (LCA) at the initial setting, rewriting only a part revised newly by a CPU freely and writing the revised circuit data into an E<2>ROM so as to preserve the data even if power supply is interrupted. CONSTITUTION:The CPU 11 sets the circuit data to revise the hardware constitution freely by the logic cell array (LCA) 12. Then the circuit data of the LCA 12 at the initial setting is preserved and only the part revised newly is rewritten freely by the CPU 11 and written into the E<2>ROM so as to preserve the data even if power supply is interrupted. Thus, the user can select a peripheral equipment required really among lots of peripheral equipments. Thus, the user can increase the expanded system freely.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is an improvement of a flexible address decoder,
In particular, the present invention relates to an address decoder circuit that changes data in a logic cell array (hereinafter referred to as LCA) on an E2ROM.

(Prior Art) Conventionally, in this type of address decoder, the address is fixed, or even if it is variable, it is changed by a dip switch, and the number of peripheral circuits that can change the address is small.

(Problem to be Solved by the Invention) The conventional address decoder described above has a fixed address or has an exclusive address map in terms of hardware, so it has many peripheral circuits attached to it. The disadvantage is that the computer system currently in use does not have enough port addresses, and the user cannot freely increase the number of expansion systems.

An object of the present invention is to set circuit data using a CPU and to freely change the hardware configuration using LCA.
Save the initial setting LCA circuit data, and freely rewrite only newly changed parts using the CPU, so that the changed circuit data will not be erased even if the power is turned off.
7 for CPU peripheral circuits configured to eliminate the above drawbacks and freely increase the expansion system
Provides a lexical address decoder.

(Means for Solving the Problems) A flexible address decoder for a CPU peripheral circuit according to the present invention includes a CPU, a logic cell array, and a BROM.

The CPU is for setting circuit data required for the circuit.

The logic cell array is used to incorporate circuit data, and the hardware configuration can be changed arbitrarily by setting data by the CPU.

The B ROM is used to store logic cell play circuit data at the time of initial setting, and to rewrite only newly changed portions by the CPU and retain them regardless of the power supply state.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a 7-lexiple address decoder for a CPU peripheral circuit according to the present invention.

In Figure 1, 1 is a basic system using a CPU;
2 is a peripheral device whose address map can be freely changed by LCA. In the basic system 1 [, 11 is C
PU, 12 is LCA.

13 is a B2ROM, 14 is a RAM, 15 is an interface LSI, and 21 is an expansion R in the peripheral device 2.
OM, 22 is expansion RAM, 23 is interface L8
I, 24 is a timer LSI.

Basic system 1 consists of CPUII, LCAl2, and E”R.
OM13, RAM14, and interface L811
5. CPU1 first sends the circuit data of E'ROM13 to LCAl2,
Next, the LCA 120 circuit configuration is set. LCAl2 determines the address map of the peripheral device 2 according to the circuit data. In the E2ROM 13, the circuit data can be changed at any time by the CPU 1, and the changed data is saved. The CPU 1l can send the above data to the LCAl 2 again and reconfigure the circuit of the LCAl 2.

The peripheral device 2 includes an expansion ROM 21, expansion R and AM 22,
It is configured to include an interface L8I23 and a timer L8I24. LCAl2 determines the address to be allocated and whether or not the peripheral device 20 can be used.

FIG. 2 is a block diagram showing an example of a modification of the address map of the address decoder shown in FIG. 1. In FIG. 2, 201 is an LCA, 202 and 203 are first and second RAMs 1204, 205 are first and second ROMs, respectively, and 206 is a CPU. Further, DIN is a data input, D/P is an enable terminal, AQ and An are address output terminals, and DO and B7 are data bus terminals.

In the initial state, the LCA 201 allocates the first RAM 202 from address 80000HK, and also from address 90HK.
The second RAM 203 is allocated from 000HK. When using a dedicated ROMized O8 or compiler,
A first ROM 204 and a second ROM 205 can be used instead of the first and second RAMs 202 and 203.

(Effects of the Invention) As explained above, the present invention saves the circuit data of KL and LCA at the initial setting so that the circuit data can be set by the CPU and the hardware configuration can be freely changed by LCA, and the circuit data of LCA at the time of initial setting is saved. By freely rewriting only the changed parts using the CPU and writing the changed circuit data to the B2ROM so that it does not disappear even when the power is turned off, the user can select only those that are actually needed among the many peripheral devices. You can add an expansion system to an unused port address, change the expansion RAM/ROM address map, use expansion ROM instead of expansion RAM, or change the printer's assigned serial number. Changes such as assigning a plotter to a port can be made on the keyboard, and updated LCA circuit data can be saved on the E2ROM.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a 7-lexiple address decoder for a CPU peripheral circuit according to the present invention. FIG. 2 is a schematic diagram showing an example of changing the address map of the address decoder shown in FIG. 1. 1...Basic system 2...Peripheral device 11.206-CPU 12.201-LCA 13.21.204.205-ROM 14.22.202.203-RAM 15.23-...Interface LSI24--・Timer LSI Patent applicant Hisashi Inoro, agent for NEC Corporation, patent attorney

Claims (1)

[Claims] C for setting the circuit data required for the circuit in question
The hardware configuration can be arbitrarily changed by setting the data by the PU and the CPU, and the logic cell array for incorporating the circuit data and the circuit data of the logic cell array at the time of initial setting are saved and newly changed. 1. A flexible address decoder for a CPU peripheral circuit, comprising an E^-ROM for rewriting only a portion by the CPU and retaining it regardless of the state of the power supply.