JPH01180830U - - Google Patents
Info
- Publication number
- JPH01180830U JPH01180830U JP7240688U JP7240688U JPH01180830U JP H01180830 U JPH01180830 U JP H01180830U JP 7240688 U JP7240688 U JP 7240688U JP 7240688 U JP7240688 U JP 7240688U JP H01180830 U JPH01180830 U JP H01180830U
- Authority
- JP
- Japan
- Prior art keywords
- full
- wave rectifier
- rectifier circuit
- resistor
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Emergency Protection Circuit Devices (AREA)
Description
第１図はこの考案の一実施例を示す構成図、第
２図はこの考案の他の実施例を示す構成図、第３
図は従来のサージ抑制装置を示す構成図、第４図
は振動時の波形図である。
１はＰＷＭインバータ、２は負荷、４はサージ
抑制装置、２０は全波整流回路、２１〜２６はダ
イオード、２７はコンデンサ、２８は第一の抵抗
器、２９は第二の抵抗器、３１，３２は全波整流
回路の直流出力側端子。
Fig. 1 is a block diagram showing one embodiment of this invention, Fig. 2 is a block diagram showing another embodiment of this invention, and Fig. 3 is a block diagram showing another embodiment of this invention.
The figure is a configuration diagram showing a conventional surge suppressor, and FIG. 4 is a waveform diagram during vibration. 1 is a PWM inverter, 2 is a load, 4 is a surge suppressor, 20 is a full-wave rectifier circuit, 21 to 26 are diodes, 27 is a capacitor, 28 is a first resistor, 29 is a second resistor, 31, 32 is the DC output side terminal of the full-wave rectifier circuit.
Claims (1)
により交流電力を供給される負荷回路に設けられ
たサージ抑制装置において、一方向性導通素子に
よる全波整流回路、この全波整流回路の直流出力
側端子の一端に接続された第一の抵抗器、この第
一の抵抗器を介して前記全波整流回路の直流出力
側端子に接続されたコンデンサ、一端をこのコン
デンサの接続された前記全波整流回路の直流側出
力端子に他端を前記第一の抵抗器のいずれか一方
の端子に接続された第二の抵抗器を備えたことを
特徴とするサージ抑制装置。 In a surge suppressor installed in a load circuit that is supplied with AC power by an inverter configured with switching elements, a full-wave rectifier circuit with a unidirectional conduction element is connected to one end of the DC output side terminal of this full-wave rectifier circuit. a capacitor connected to the DC output terminal of the full-wave rectifier circuit through this first resistor; one end connected to the DC output terminal of the full-wave rectifier circuit connected to this capacitor; A surge suppressor comprising a second resistor whose other end is connected to one of the terminals of the first resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7240688U JPH01180830U (en) | 1988-05-31 | 1988-05-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7240688U JPH01180830U (en) | 1988-05-31 | 1988-05-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01180830U true JPH01180830U (en) | 1989-12-26 |
Family
ID=31297573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7240688U Pending JPH01180830U (en) | 1988-05-31 | 1988-05-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01180830U (en) |
-
1988
- 1988-05-31 JP JP7240688U patent/JPH01180830U/ja active Pending
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