JPH01180119A - D/a converter - Google Patents

Abstract

PURPOSE:To attain conversion output with high accuracy and high speed by using an output signal of a 2nd D/A converter so as to measure the weight of each bit of a 1st D/A converter, storing the result into a memory and correcting the conversion output of the 1st D/A converter based on the data. CONSTITUTION:A switch 11 is turned off at zero calibration and a switch 14 is switched between Z, M in 50% duty. An output signal of D/A converters 6, 7 is adjusted to minimize an output signal VN of an LPF 20 of a detection section 15 and to store setting values IP2, ES2 into a memory 23. Thus, an output signal VOUT of an adder 8 is zero. In case of reference voltage calibration, the signal of the D/A converters 6, 7 is adjusted to minimize the output signal VN of the LPF 20 and the setting values TPR, ESR in this case into the memory 23. Thus, the relation of VOUT=VR is obtained. Then the switch 14 is set to the position M to evaluate the weight of all hits of the converter 6 relatively by the output ES of the converter 7.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a D/A converter, and more specifically, to a D/A converter that can obtain high-precision, high-speed conversion output.
This invention relates to a conversion device.

(Prior Art) There is a current addition type D/A converter that performs high-speed conversion operations.

FIG. 8 is a conceptual explanatory diagram of such an A/A conversion device. In FIG. 0, 1 is a reference voltage source that outputs a reference voltage Vr. 21 to 21 are resistors each having a predetermined weighted resistance value, one end of which is connected in parallel to the reference voltage source 1, and the other end connected to each of the switches 31 to 3TL.
The adder 4 is connected to the adder 4 via the adder 4. 5 is an output terminal.

In such a configuration, the switches 31 to 31 are selectively driven by pit signals corresponding to each of the n-pit digital signals. When the switch is turned on, the reference voltage Vr is applied to the resistors connected in series with the switch, and a current corresponding to the resistance value of each resistor is applied to the adder 4. This causes the output terminal 5 from the adder 4 to be connected to the switch 3. A voltage proportional to the code value of the n-pit digital signal that drives .about.31 is output.

(Problem to be solved by the invention) However, according to such a conventional ellipse,
Although a fast stabilization time of ~ several tens of microseconds can be obtained, the resistance value of the LSB resistor must be set to 2n of the resistance value of the 88B resistor, and as the number of pits increases, the accuracy of the weight of each pit decreases. It becomes difficult to adjust temperature characteristics, stability, etc. within predetermined ranges. Specifically, when focusing on linearity, only about 16 bits (four and a half, 15 ppi) are achieved.

The present invention has focused on these points, and its purpose is to provide a D/A converter that has a relatively simple configuration and can provide highly accurate and high-speed conversion output.

(Means for Solving the Problems) A D/A converter of the present invention includes: a first D/A converter; a second D/A converter; and a reference voltage generating means for outputting a reference voltage. , each of the above D/A
an adder that adds the output signals of the converter with different weights; a first switch that selectively outputs the output signal of the adder to the outside; the output signal of the adder, a common potential point, and a reference voltage. a second switch that selectively outputs one of the signals; a signal detection unit that detects the output signal output from the second switch; and A that converts the output signal of the signal detection unit into a digital signal.
/D converter, and the output signal of this A/D converter is taken in, and each of the D/A
and an arithmetic control unit that controls the set value of the converter and drives and controls each switch, and the weight of each pit of the first D/A converter is determined by the output signal of the second D/A converter. The present invention is characterized in that the measurement result is stored in a memory, and any conversion output of the first D/A converter is corrected based on the weight measurement data stored in the memory.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. 1st
In the figure, 6 is the first D/A converter, and 7 is the second D/A converter.
The A converter, 8, is an adder, which is composed of an operational amplifier. The non-inverting input terminal of this operational amplifier is connected to a common potential point, and the output terminal of the D/A converter 6 is directly connected to the inverting input terminal, and the D/A converter 6 is connected via a resistor 9 having a resistance value RN. The output terminal of the converter 7 is connected, and a resistor 10 having a resistance value R is connected between the non-inverting input terminal and the output terminal. 11 is a first switch that selectively outputs the output signal vg of this adder 8 to an external output terminal 12, 13 is a reference voltage generator that outputs a reference voltage vR, and 14 is an output signal (M ), a second switch that selectively outputs either the common potential point (Z) or the reference voltage (R); 15 is a signal detection unit that detects the output signal output from the second switch 14; The signal detection unit 15 detects high frequency components (difference signals 8M and 2 of M and R) of the output signal V output from the second switch 14, for example.
or the difference signal of M itself) is passed through the bypass filter 16. Amplifier 17° that amplifies output signal ■2 of bypass filter 16 Output signal of amplifier 17 from vco to M
and R, or M and Z, to remove low frequency noise and high frequency noise, and also remove noise contained in the output signal of the adder 8 (<M). Diode 1 for detecting the amplitude of the difference signal from the output signal v4 of the bandpass filter 18
9. It consists of a low-pass filter 20 that converts the output signal 5 of the diode 19 into direct current.

21 is an A/D converter that converts the DC signal VN output from the signal detection section 15 into a digital signal vo, and the converted signal Vo is applied to the calculation control section 22. The arithmetic control unit 22 takes in the conversion signal Vo, and inputs the conversion signal Vo to each D/A converter 6, 7.
In addition to controlling the set value of , each switch 11.14 is driven and controlled. A non-volatile memory 23 stores the calculation results of the calculation control section 22. That is, the calculation control section 2
2 is the output signal of the second D/A converter 7, and the weight of each pit of the first D/A converter 6 is measured, and the result is stored in the memory 2.
3, and any conversion output of the first D/A converter 6 is corrected based on the weight measurement data stored in the memory 23.

The operation of the device configured in this way will be explained.

In the following description, it is assumed that the first D/A converter 6 has a unipolar output, and the second D/A converter 6 has a bipolar output.

These combinations may be selected depending on the drift performance of the D/A converter 6.7, and the one with excellent drift performance is used as the first D/A converter 6.

First, for zero calibration, switch 11 is turned off, and switch 14 is switched between Z and M with a duty of 50%. Then, each D/A converter 6.7
Adjust the output signal of each D/A converter 6.7
Setting value IPZ.

ESz is stored in the memory 23. As a result, adder 8
The output signal vllllll becomes O in V, ll.

Next, when calibrating the reference voltage, the switch 11 is turned off, and the switch 14 is switched between M and R with a duty of 50%. Then, the output signal of each D/A converter 6.7 is adjusted so that the output signal vN of the low-pass filter 20 of the signal detection section 15 is minimized, and the settings of each D/A converter 6.7 at that time are set. The values IPR and ESR are stored in the memory 23. As a result, the output signal v of the adder 8 becomes vR in VQ.

FIG. 2 is a waveform diagram of each part when determining these IPR and ESR, (a) shows the output signal 1 of the switch 14, (b) shows the output signal v2 of the bypass filter 16, and (c ) indicates the output signal ■3 of the amplifier 17, and (d
) indicates the output signal ■4 of the bandpass filter 18, and (
(e) shows the output signal v5 of the diode 19, (f) shows the output signal VN of the low-pass filter 20, and (g) shows the output signal Vo of the A/D converter 21. Here, the duty of the switch 14 that switches between M and R is M>
It determines the detection sensitivity difference of the signal detection unit 15 between R and MAR, and is not necessarily limited to 50%.
FIG. 3 is an explanatory diagram of the relationship between the magnitudes of M and R and duty, where (a) shows MAR, (b) shows M=R, and (c
) indicates M<R. Fig. 4 is a half-wave rectification characteristic diagram related to Fig. 3, and Fig. 5 is an enlarged view of the vicinity of the origin in Fig. 4, where the solid line shows the case where the duty is 50%, and the broken line shows the case where the duty of M is small. , and the dashed-dotted line indicates the case where the duty of M is large. As is clear from these countries, the actual signal detection unit 15 has a detection limit near M to R, and when the duty is 50%, it is clear that M,
The average value (M, +M2)/2 of M2, which can be said to be R, and the average value (M, +M2)/2 of M2, which can clearly be said to be M2>R, is extremely close to R, but if the duty goes out to 40 = 60, the average value (M
, 10M 2 )/2 will change up to R±(detection limit value)X2/3.

After performing two-point calibration in this way, switch 14 is set to M.
, the weights of all the pits of the first D/A converter 6 are relatively valued using the output ES of the second D/A converter 7.

That is, (ES/RN) < IPノ)-ki, E
The S linearity error, the maximum output error, and the offset error are sufficiently large within the error tolerance range of the output signal - of the adder 8.

When pricing LSB (IPI), the first combination is to set IP to "000...Ol" (IPI) and set ES to O, and the first combination is to set IP to "000...Ol" (IPI) and to set ES to O.
00''<IPo) and a second combination of setting ES to ES, and outputting the second combination with a duty of 50%, the ES that minimizes vN is determined and stored in the memory 23. Next, change the IP address to “000...10” (
The first combination of setting IP2) and setting ES to O, and the second combination of setting IP to 000...0IJ (IPI) and setting ES to ES, are output with a duty of 50%. The ES that minimizes VN is determined and stored in the memory 23.

This results in IP+ = ES+ + IP.

=ES, +ES.

and the LSB (IPl) of the first D/A converter 6
The weight of can be relatively valued by the output [S of the second D/A converter 7.

Below, in the same procedure, from LSB +1 (IP2) to 1
The relationship between these values, in which each pit of 43B (IPi) is valued, is expressed as follows.

IP2 = ES2 + IP+ + IPO=E
S2 +ES1 +ESO+ESO=ES2 +E
S, +2ES0 IP, =ES, +IP2+IP, +IP.

=ES3 +ES2 +ES1 +2ESO+ES1
+ESO+ESO =ES3+E12 12ES1 + 4ESOIPi
= ESI 1ESi-1+2ESt-1+4EJ-3
+...+ 2''ESO A specific example of such a device will be explained.

The resolution of the D/A converters 6 and 7 is 4 bits and the accuracy is ±0. Let ILSB be Ih = 7.9. IP2
=4.1. IP1=1.9. IPo = 1.1
．． ES3 = -8,1, ES2 = 4.0. E
St = 2.1. ESo = 0.9, I
The overall offset voltage v when P and ES are all 0
.

ff is −0,211aX, and vR is 10. Also, the scale factor is lVot +l+1IPolnax by ES (approximately -8
Since about 7) must be covered, (0,2+1.1)/2 in 0.186 in 0.1
9.

Let's assume that.

When ES is calculated based on these, it becomes as shown in the following table.

ES7...0111=7.0...x 0.19
=1.330ES6...0110=6.1...
x 0.19=1.159ESS...0101=4.
9...x 0.19=0.931ES4...
0100=4.0...x 0.19=0.76
0ES3...0O11=3.0...x O,1
920, 570ES2...0O10=2.1...
・x 0.19= 0.399ESI ・・・0OO1
=0.9...x 0.19=0,171ES
O...oooo=o, o...x 0.19=O
ES-1...1111 =-1,1...x 0.1
9=-0,209ES-2...1110=-2,0
...x 0.19=-0,380ES-3...11
01 =-3,2...x 0.19=-0,608E
S-4...1100 =-4,1...x O,19
Tomi-0,779ES-5...1011 =-5,1.
・・x 0.19=-0,969ES-6...101
0 = -6,0...x O,19・-1,140[
S-7...1001 =-7,2...x 0.1
9=-1,368ES-8...1000=-8,1
...x 0.19 knee 1.539 From these, the zero voltage is ES where 1yoi t +ESl is closest to O
ES1=0.171 can be obtained.

Next, as the reference voltage VR, it is sufficient to select IP and ES where Vo t t +IP+ES is closest to vR, and -0
,2+IP, ÷IP, +ES2 value
? , 9 1.9 0.399 remaining
? , 7 9.6 9.999 to IPx ,
It will be IP+ and ES2.

For IPO (1, 1), Vo t t + IPo is the most V
You just need to select an ES that is close to off + ES, and IPo
The ES closest to is ES6 (1,159).

For IP, (1,9), it is sufficient to select the ES in which Vo t t +IP1 is closest to VO14+xp O+ES, and IP, medium IP0 +ES4=ES6+ES4
From the value 1.9 1.1 0.76 remaining 0.8 0.04, ES becomes ES4 (0,760).

Similarly, IP2 medium IP, ÷IP0 ÷ES6= 3E
S6-ES4 value 4.1 1.9 1.1 1.159 remaining 2.2 1.1 0.059, IP, medium IP2 ÷ IP+ -IPo +E
S4=5ES6÷ES4 value 7.9 4.1 1.9 1
．． 1 0.760 remaining 3.8 1.9 0
．． 8 It becomes 0.04.

Recalculating vR using the IP obtained in this way, VR=IP, +IP, 10ES2=5ES
6+3ES4+ES6+ESJ×ES2=6ES6+
It becomes 4ES4-ES2.

Here, since the school factor of ES is as small as 0.19, it can be treated as substantially linear. As a result, during vR, (6X6+4X4 +2)ES1= 54ES
1 Zero voltage = IESI IP, medium 6ESI IP, medium (6-4) ES1 = IQES11P2 medium (3
x 6+4) ES1 wealth 22 ESIIP, Ki (5x
6+3x4)ESl=42ES1.

When outputting an arbitrary voltage X from these values of vR and zero voltage, from ESx=ax+b, 54=a・10+b 1=a・o×b b=1, a=(54-1)/10= 5
．． 3, and ESx can be found by ESx = 5.3x +1. Here, 1/a
=115.3 = 0.11G4: If you want to output 0, for example 13,2, which matches the scale factor mentioned above, 13.2. x 5.3 1 = 70.96 medium 7
171-42(IP:+)-22(IP2
)−6(IPo)=1(ES), IP3, I
Output P 2 , IP O and ESl.

The actual output voltage vT:m is 7.9÷4.1÷1,1÷0.171-0.2=13.
07, and the error is -0.13. This error is D
This is due to the small number of pits in the /A converters 6 and 7.

For example, if the resolution of the D/A converters 6 and 7 is both 16 bits, the output voltage of the D/A converter 6 is set to 0 to 10 V, and the D/A converter 6 has a resolution of 16 bits.
Assuming that the output voltage of converter 7 is -10~10cm and the overall offset voltage is 1nV, the scale factor SF is: 5F=(1nV-f10V/65536))/10V
0.12
0x 32768 Ki 2' 3 x 215=2
20, and a resolution equivalent to 28 bits can be obtained.

With this configuration, a filter unlike the pulse width modulation method is not required, and a high-speed response can be obtained. Further, by determining the absolute value of the reference voltage vR using a standard battery or the like, a more accurate output can be obtained.

Note that the diode 19 constituting the signal detection section 15 may be replaced with a double-wave rectifier circuit.

Furthermore, according to a rectifier circuit as shown in FIG. 1, in which a synchronous detection circuit may be used as the signal detection section 15, M>R is also M
<R#J has the disadvantage that the rectified outputs have the same polarity,
According to the synchronous detection circuit, the detection output polarity for M>H and the detection output polarity for M<H are opposite to each other, and M=R can be quickly found using a known binary search method.

In addition, although FIG. 1 shows an example in which a current output type is used as the first D/A converter 6 and a voltage output type is used as the second D/A converter 7, any output type may be used. It may be a combination.

FIG. 6 shows an example in which a voltage output type is used as the D/A converter 6.7, and R,<R2 is set.

FIG. 7 shows an example in which a current output type is used as the D/A converter 6.7, and the maximum output current is set so that Is<IP.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize a D/A conversion device that can obtain high-precision, high-speed conversion output with a relatively simple configuration, and has great practical effects.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a waveform diagram for explaining the invention in detail, Fig. 3 is an explanatory diagram of the relationship between the magnitudes of M and R and duty, and Fig. 4 is a half-wave rectification characteristic diagram related to FIG. 3, FIG. 5 is an enlarged view of the vicinity of the origin of FIG. 4, FIGS. 6 and 7 are circuit diagrams showing other embodiments of the present invention, and FIG. The figure is a conceptual configuration diagram showing an example of a current addition type D/A converter. 6.7... D/A converter, 8... operational amplifier, 11
14...Switch, 13...Zener diode,
15... Signal detection unit, 21... A/D converter, 22
...Arithmetic control unit, 23...Nonvolatile memory. Figure 1 Figure 2 (bn VZ □
6 Figure 6 Figure 7 p IF fau > Is full Figure S

Claims (1)

[Scope of Claims] A first D/A converter, a second D/A converter, a reference voltage generating means for outputting a reference voltage, and a weight of an output signal of each of the D/A converters. an adder that adds the signals at different levels; a first switch that selectively outputs the output signal of the adder to the outside; and an adder that selectively outputs either the output signal of the adder, the common potential point, or the reference voltage. a second switch that detects the output signal outputted from the second switch; a signal detection unit that detects the output signal output from the second switch; and A that converts the output signal of the signal detection unit into a digital signal.
/D converter, and the output signal of this A/D converter is taken in, and each of the D/A
and an arithmetic control unit that controls the set value of the converter and drives and controls each switch, and the weight of each pit of the first D/A converter is determined by the output signal of the second D/A converter. and storing the results in a memory, and correcting any conversion output of the first D/A converter based on the weight measurement data stored in the memory.
/A conversion device.