JPH0117619B2 - - Google Patents

Info

Publication number
JPH0117619B2
JPH0117619B2 JP7031083A JP7031083A JPH0117619B2 JP H0117619 B2 JPH0117619 B2 JP H0117619B2 JP 7031083 A JP7031083 A JP 7031083A JP 7031083 A JP7031083 A JP 7031083A JP H0117619 B2 JPH0117619 B2 JP H0117619B2
Authority
JP
Japan
Prior art keywords
transformer
channel
data transmission
winding
transmission path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP7031083A
Other languages
Japanese (ja)
Other versions
JPS59194544A (en
Inventor
Kyoharu Inao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP7031083A priority Critical patent/JPS59194544A/en
Publication of JPS59194544A publication Critical patent/JPS59194544A/en
Publication of JPH0117619B2 publication Critical patent/JPH0117619B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J1/00Frequency-division multiplex systems
    • H04J1/02Details
    • H04J1/10Intermediate station arrangements, e.g. for branching, for tapping-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、情報処理装置を接続するデータ伝送
路に使用する簡易な分岐挿入回路に関する。特
に、簡易な周波数多重形のデータ伝送路に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a simple add/drop circuit used in a data transmission path connecting information processing devices. In particular, it relates to a simple frequency multiplexed data transmission path.

〔従来技術の説明〕[Description of prior art]

情報処理装置と端末あるいは情報処理装置を相
互に接続する一対のデータ伝送路あるいはデータ
バスに、高速度のデイジタルデータ信号を伝送
し、このデータ伝送路の信号を各端末で分岐挿入
する方式が用いられている。このような方式で、
各端末あるいは情報処理装置の間に、高速度のデ
イジタルデータ信号の他に速度の遅い制御信号を
伝送する必要があると、従来方式では別に低速用
のデータ伝送路を別に設けることが必要であつ
た。データ伝送路を別に設けることができないと
きには、高速度のデイジタルデータ信号を伝送す
るデータ伝送路に、低速度の信号を周波数多重し
て伝送することになる。このときには、第1図に
示すように、各端末あるいは中央装置でデータ伝
送路から信号を分岐しもしくはデータ伝送路に信
号を挿入するために、高速度のデータ信号に対す
る高域濾波器と、低速度のデータ信号に対する低
域濾波器とを備えなければならない。
A method is used in which high-speed digital data signals are transmitted to a pair of data transmission paths or data buses that interconnect information processing equipment and terminals or information processing equipment, and the signals on this data transmission path are added and dropped at each terminal. It is being In this way,
When it is necessary to transmit slow control signals in addition to high-speed digital data signals between terminals or information processing devices, conventional methods require a separate low-speed data transmission path. Ta. When a separate data transmission path cannot be provided, low-speed signals are frequency-multiplexed and transmitted on the data transmission path that transmits high-speed digital data signals. In this case, as shown in Figure 1, in order to branch the signal from the data transmission path or insert the signal into the data transmission path at each terminal or central device, a high-pass filter for high-speed data signals and a low A low pass filter for the speed data signal must be provided.

このような構成では、低域濾波器および高域濾
波器が大形になり、装置が大形化する欠点があ
る。また、データ伝送路の中継には広帯域増幅器
を必要とするので、システムが高価になる。
Such a configuration has the disadvantage that the low-pass filter and the high-pass filter are large in size, making the device large. Furthermore, since a broadband amplifier is required for relaying the data transmission path, the system becomes expensive.

〔発明の目的〕[Purpose of the invention]

本発明は、きわめて簡単な構成で、小形かつ安
価にデータ伝送路を周波数多重化して利用するこ
とができる分岐挿入回路を提供することを目的と
する。
SUMMARY OF THE INVENTION An object of the present invention is to provide a drop/add circuit that has an extremely simple configuration, is small in size, and can be used at low cost by frequency multiplexing data transmission paths.

〔発明の特徴〕[Features of the invention]

本発明は、データ伝送路に結合するためのトラ
ンスを濾波器として兼用するものである。
In the present invention, a transformer for coupling to a data transmission line also serves as a filter.

すなわち本発明は、一次側の巻線数が少なく、
二次側の巻線が第一のチヤネルの入出力端子に接
続された第一のトランスと、一次側の巻線数が多
く、二次側の巻線が第二のチヤネルの入出力端子
に接続された第二のトランスと備え、 上記第一のトランスの一次側の巻線と上記第二
のトランスの一次側の巻線が直列に接続された回
路が周波数多重データ伝送路に並列に接続され、
上記第二のトランスの一次側の巻線と並列に上記
第一のチヤネルの周波数帯で低いインピーダンス
を有するコンデンサが接続されたことを特徴とす
る。
In other words, the present invention has a small number of windings on the primary side,
A first transformer with a secondary winding connected to the input/output terminal of the first channel, and a first transformer with a large number of primary windings and a secondary winding connected to the input/output terminal of the second channel. and a second transformer connected thereto, a circuit in which the primary winding of the first transformer and the primary winding of the second transformer are connected in series is connected in parallel to the frequency multiplexed data transmission line. is,
The present invention is characterized in that a capacitor having low impedance in the frequency band of the first channel is connected in parallel with the primary winding of the second transformer.

〔実施例による説明〕[Explanation based on examples]

第2図は本発明は実施例回路の構成図である。
Dはデータ伝送路であり、このデータ伝送路Dに
は第3図に示すように、高い周波数帯の第一のチ
ヤネルCH1と、低い周波数帯の第二のチヤネル
CH2とが周波数多重伝送される。この実施例回路
では、第一のチヤネルCH1は1Mb/Sのデータ伝
送を行うものであり、これに第二のチヤネルとし
てRS232Cに相当する約10kHzの制御信号を周波
数多重するものである。
FIG. 2 is a block diagram of a circuit according to an embodiment of the present invention.
D is a data transmission path, and this data transmission path D has a first channel CH 1 in a high frequency band and a second channel in a low frequency band, as shown in Fig. 3.
CH 2 is frequency multiplexed and transmitted. In this embodiment circuit, the first channel CH 1 is for data transmission of 1 Mb/S, and the second channel is for frequency multiplexing a control signal of approximately 10 kHz corresponding to RS232C.

本発明の分岐挿入回路には、2個のトランス
T1およびT2を備える。第一のチヤネルT1の二次
側巻線は、第一のチヤネルの入出力端子CH1に接
続される。第二のトランスT2の二次巻線は、第
二のチヤネルの入出力端子CH2に接続される。こ
の2個のトランスT1およびT2の各一次巻線は直
列に接続され、この直列に接続された回路がデー
タ伝送路Dに並列に接続される。さらに、第二の
トランスT2の一次側巻線と並列にコンデンサC
が接続される。ここで、この第一のトランスT1
の一次巻線の巻線数は少なく、この第一のトラン
スT1は周波数の高い第一のチヤネルで有効にト
ランスとして作用する。また、第二のトランス
T2の一次巻線の巻線数は多く、このう第二のト
ランスT2は周波数の低い第二のチヤネルで有効
にトランスとして作用する。コンデンサCは第一
のチヤネルの周波数帯で低いインピーダンスを有
する値に設定される。
The branch/add circuit of the present invention includes two transformers.
Comprising T 1 and T 2 . The secondary winding of the first channel T 1 is connected to the input/output terminal CH 1 of the first channel. The secondary winding of the second transformer T 2 is connected to the input/output terminal CH 2 of the second channel. The respective primary windings of the two transformers T 1 and T 2 are connected in series, and the circuits connected in series are connected to the data transmission line D in parallel. Furthermore, a capacitor C is connected in parallel with the primary winding of the second transformer T2 .
is connected. Here this first transformer T 1
The number of turns of the primary winding is small, and this first transformer T1 effectively acts as a transformer in the first channel having a high frequency. Also, the second transformer
The number of turns of the primary winding T 2 is large, and thus the second transformer T 2 effectively acts as a transformer in the second channel having a lower frequency. Capacitor C is set to a value that has a low impedance in the first channel frequency band.

本実施例の各回路定数を示すと、 トランスT1の主インダクタンスL1=1mH トランスT2の主インダクタンスL2=22mH コンデンサC=470pF である。 The circuit constants of this embodiment are as follows: Main inductance L 1 of transformer T 1 = 1 mH Main inductance L 2 of transformer T 2 = 22 mH Capacitor C = 470 pF.

このように構成された装置の動作を説明する
と、第一のチヤネルの高い周波数帯(約1MHz)
では、コンデンサCのインピーダンスが低いの
で、トランスT1の一次巻線は等価的にデータ伝
送路Dに並列に接続された状態となる。一方、第
二のチヤネルの低い周波数帯(約10kHz)では、
トランスT1の一次巻線の巻線数が少なくそのイ
ンピーダンスは低いので、等価的にトランスT2
の一次巻線はデータ伝送路Dに並列に接続された
状態となる。
To explain the operation of a device configured in this way, the first channel's high frequency band (approximately 1MHz)
In this case, since the impedance of the capacitor C is low, the primary winding of the transformer T1 is equivalently connected in parallel to the data transmission line D. On the other hand, in the lower frequency band of the second channel (approximately 10kHz),
Since the number of turns in the primary winding of transformer T 1 is small and its impedance is low, equivalently transformer T 2
The primary winding of is connected to the data transmission path D in parallel.

この構成では、各周波数帯の入出力端子CH1
よびCH2には、各周波数帯の増幅器を接続するこ
とができるので、データ伝送路Dに広帯域の増幅
器を挿入する必要がなくなる利点がある。
With this configuration, an amplifier for each frequency band can be connected to the input/output terminals CH 1 and CH 2 for each frequency band, so there is an advantage that there is no need to insert a wideband amplifier into the data transmission path D.

第4図は本発明の別の実施例回路構成図であ
る。この例はハイブリツド結合方式に本発明を実
施するもので、前実施例と同一の符号が付してあ
るので同様に理解することができる。
FIG. 4 is a circuit diagram of another embodiment of the present invention. This example implements the present invention in a hybrid coupling system, and since the same reference numerals as in the previous example are given, it can be understood in the same way.

第5図はさらに本発明の別の実施例回路構成図
である。この例は第二のチヤネルがハイブリツド
結合である方式に本発明を実施するものである。
FIG. 5 is a circuit configuration diagram of another embodiment of the present invention. This example implements the invention in a manner where the second channel is a hybrid coupling.

〔応用技術の説明〕[Explanation of applied technology]

本発明は2チヤネルのデイジタルデータ信号の
多重であるが、これを3チヤネル以上に拡大して
設計することも可能である。
Although the present invention involves multiplexing two channels of digital data signals, it is also possible to design this to be expanded to three or more channels.

〔効果の説明〕[Explanation of effects]

このように、本発明の分岐挿入回路はその構成
がきわめて簡単である。本発明の回路を使用する
ことにより、低速度のデータ伝送路を別に設ける
ことなく、簡単に低速度のデータ信号を伝送する
ことができる。また、従来必要であつた周波数多
重のための濾波器は、結合トランスが兼用するの
で、形状の大きい高価な低域濾波器および高域濾
波器を用いる必要がなくなり、装置を小形かつ安
価に構成することができる。
As described above, the add-drop circuit of the present invention has an extremely simple configuration. By using the circuit of the present invention, low-speed data signals can be easily transmitted without providing a separate low-speed data transmission path. In addition, since the coupling transformer doubles as the filter for frequency multiplexing that was required in the past, there is no need to use large and expensive low-pass filters and high-pass filters, making the device compact and inexpensive. can do.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例装置の回路構成図。第2図は本
発明実施例装置の回路構成図。第3図はデータ伝
送路の周波数帯配置図。第4図は本発明の別の実
施例装置回路構成図(高速度のチヤネルがハイブ
リツド結合の場合)。第5図は本発明のさらに別
の実施例装置回路構成図(低速度のチヤネルがハ
イブリツド結合の場合)。
FIG. 1 is a circuit diagram of a conventional device. FIG. 2 is a circuit diagram of a device according to an embodiment of the present invention. FIG. 3 is a frequency band layout diagram of the data transmission path. FIG. 4 is a circuit diagram of another embodiment of the present invention (in the case where the high-speed channel is a hybrid connection). FIG. 5 is a circuit configuration diagram of yet another embodiment of the present invention (in the case where the low speed channel is a hybrid coupling).

Claims (1)

【特許請求の範囲】 1 一次側の巻線数が少なく、二次側の巻線が第
一のチヤネルの入出力端子に接続された第一のト
ランスと、 一次側の巻線数が多く、二次側の巻線が上記第
一のチヤネルより低い周波数帯の信号を伝送する
第二のチヤネルの入出力端子に接続された第二の
トランスと、 を備え、 上記第一のトランスの一次側の巻線と上記第二
のトランスの一次側の巻線が直列に接続された回
路がデータ伝送路に並列に接続され、 上記第二のトランスの一次側の巻線と並列に上
記第一のチヤネルの周波数帯で低いインピーダン
スを有するコンデンサが接続されたことを特徴と
するデータ伝送路の分岐挿入回路。
[Claims] 1. A first transformer in which the number of windings on the primary side is small and the winding on the secondary side is connected to the input/output terminal of the first channel, and the number of windings on the primary side is large, a second transformer whose secondary winding transmits a signal in a frequency band lower than that of the first channel; a second transformer connected to the input/output terminal of the second channel, the primary side of the first transformer; A circuit in which the winding of the first transformer and the primary winding of the second transformer are connected in series is connected in parallel to the data transmission line, and the first winding of the second transformer is connected in parallel with the primary winding of the second transformer. A data transmission line branch/add circuit characterized in that a capacitor having low impedance in a channel frequency band is connected.
JP7031083A 1983-04-20 1983-04-20 Branching and inserting circuit of data transmission line Granted JPS59194544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7031083A JPS59194544A (en) 1983-04-20 1983-04-20 Branching and inserting circuit of data transmission line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7031083A JPS59194544A (en) 1983-04-20 1983-04-20 Branching and inserting circuit of data transmission line

Publications (2)

Publication Number Publication Date
JPS59194544A JPS59194544A (en) 1984-11-05
JPH0117619B2 true JPH0117619B2 (en) 1989-03-31

Family

ID=13427754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7031083A Granted JPS59194544A (en) 1983-04-20 1983-04-20 Branching and inserting circuit of data transmission line

Country Status (1)

Country Link
JP (1) JPS59194544A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3856334T2 (en) * 1987-08-07 1999-11-04 Mitsui Chemicals Inc Device for evaluating the insulation condition

Also Published As

Publication number Publication date
JPS59194544A (en) 1984-11-05

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