JPH01173382A - Storing circuit - Google Patents

Abstract

PURPOSE:To easily obtain synchronization at a high speed operating time by reading a purposed address to an external part without fail simultaneously with the generation of an operation prohibiting signal after a processing is restarted even when the operation prohibiting signal is generated when a reading and a writing are simultaneously executed with the same address as a subject. CONSTITUTION:A busy signal BSY is transmitted to a latch 23 while a writing allowing signal WE is true and when the signal WE is not true, the signal BSY is latched by the latch 23 and the output signal of the latch 23 goes to be 'H' until the signal WE goes to be true next. The output signal of the latch 23 is supplied through an OR gate 24 to a latch 25 together with the signal WE. The hold input signal of this latch 25 goes to be 'H' after the signal WE goes to be true in a cycle T2 until the signal WE goes to be false in a cycle T3. Accordingly, the cycle T2 and the busy signal BSY to prohibit the writing to an address B are turned off and the simultaneous reading is executed from the same address B as the writing to the address B.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) This invention provides a memory cell array that can give read addresses and write addresses separately and that can perform writing and reading simultaneously. Related to memory circuits.

(Prior Art) This type of memory circuit has conventionally been configured as shown in FIG. In FIG. 3, reference numeral 11 denotes an n-bit x m-word storage cell array constructed using, for example, m n-bit latches, and when the write enable signal WE is true, A1
The write data given by the DI large input is written into the word position specified by the write address given manually.

Independently of this write operation, the stored data at the word position in the memory cell array 11 specified by the read address given to A2 is read out as a DO ratio output.

Now, in the configuration of FIG. 3, when A1 manual content - A2 manual content (write address - read address), the write permission signal WE is output as shown in the timing chart of FIG.
If true, the DI input contents (write data) will be read out as is, which is inconvenient if you want to write to the same address while reading the stored data (old data) at that address. Become.

Therefore, in order to prevent the above-mentioned inconvenience from occurring, a transparent latch (hereinafter simply referred to as a latch) 1 is installed between the memory cell array 11 and the DO ratio output, as shown in FIG.
2 is inserted so that the data read from the memory cell array 11 when the write permission signal WE changes to true is held in the latch 12 during the period when the signal WE is true.

In the configuration of FIG. 5, as shown in FIG. 6, regardless of the write permission signal WE, A2 manual content (read address)
The storage data at the word position in the memory cell array 11 designated by is led to the Do ratio output via the latch 12, and at the same time, it is possible to write the DI input contents (write data) to that word position. In addition, in FIGS. 4 and 6,
(A>, (B), and (C) indicate storage data at word positions indicated by addresses A, B, and C, and (DI) indicates DI input content (write data).

When the memory circuit of FIG. 5 is applied to an actual device, it becomes necessary to deal with the hold caused by the busy signal BSY of other circuits operating in synchronization with this circuit.

For example, in an arithmetic circuit, if the arithmetic operation takes time, the arithmetic circuit emits a busy signal BSY as an operation prohibition signal until the arithmetic operation is completed, and a circuit that operates in synchronization with the arithmetic circuit that receives it receives the busy signal BSY. Processing is interrupted while BSY is true, and processing is restarted when busy signals B and SY are turned off. FIG. 7 shows an example in which the memory circuit of FIG. 5 is modified so as to be able to cope with the above-mentioned waiting. A NOR gate 13 is provided to which the level inversion signal of the write permission signal WE and the busy signal BSY are supplied. By controlling the writing of the memory cell array 11 by the output of the NOR gate 13, writing is prohibited when the busy signal BSY is generated.

Now, in the memory circuit shown in FIG. 7, in order to reliably inhibit writing when the busy signal BSY is generated, it is necessary to prevent writing before the write enable signal WE becomes true, as in cycle T2 of the timing chart shown in FIG. The busy signal BSY must be true, and the true period (occurrence period) of the signal BSY must be longer than the true period (pulse width) of the write enable signal WE to ensure writing to the memory cell array 11. . Under this condition, writing is completely prohibited, and the read data derived from the Do ratio output from the latch 12 remains unchanged until the next cycle T3. Therefore, if an attempt is made to read stored data at the same address at the same time as writing, if the busy signal BSY is turned off and processing is restarted in the next cycle T3, the data to be retrieved from the DO ratio will be output at the start of cycle T2. This becomes the data stored at the same address in the memory cell array 11, and it becomes possible to write while reading to the same address. However, the busy signal BSY must be set to true before the write enable signal WE becomes true, and the busy signal B must be set for a longer period than the true period (pulse width) of the write enable signal WE.
Generating SY is difficult in large and high speed circuits.

On the other hand, as in cycle T5 in FIG. 8, the busy signal BSY is made true later than the write permission signal WE, and furthermore, the busy signal BSY is generated for a shorter period than the true period (pulse width) of the write permission signal WE. This is possible because it does not impede speeding up. However, in this case, writing to the memory cell array 11 is performed although insufficiently, and the data at the address (D in this case) specified by the manual content of A1 becomes uncertain. Therefore, if you are trying to read stored data at the same address at the same time as writing,
At the time of rewriting in the next cycle T6, the data read from the same address (address D in this case) and led to the D○ ratio output (the shaded portion in FIG. 8) is not guaranteed.

(Problems to be Solved by the Invention) As mentioned above, in the past, the successive address and the write address can be given separately, and the speed of the entire device including the memory circuit that can perform writing and reading at the same time has been improved. Therefore, if the setup time of the disable signal is unrelated to the pulse width of the write enable signal and is attempted to be made shorter, insufficient writing may occur and the contents of the word location specified by the write address may become uncertain. There was a problem.

Therefore, in this invention, even if the set-up time of the operation inhibit signal is independent of the pulse width of the write enable signal and is shorter, the operation is equivalent to when writing is prohibited, and read and write operations are performed for the same address. To provide a storage circuit that can reliably retrieve data stored at a target address immediately before the generation of the operation prohibition signal to the outside even if an operation prohibition signal is generated when processing is performed simultaneously. Make it an issue to be solved.

[Structure of the Invention] Means for Solving the Problems) This invention provides a peripheral circuit for a memory cell array that can give a read address and a write address separately and can perform writing and reading at the same time. a first transparent latch having an input to which an applied operation inhibit signal is guided and set to a hold mode while the write enable signal is not true; and a first transparent latch having an input to which read data from the memory cell array is guided. and a second transparent latch in which at least one of the output and the write permission signal is set to a true period hold mode, and the output of the second transparent latch is outputted to the outside as read data from the memory cell array. Features.

(Operation) According to the above configuration, the operation inhibit signal is held in the first transparent latch until the next write enable signal becomes true, and therefore the operation inhibit signal is held in the first transparent latch during the next cycle as well as in the previous cycle. Since the held read data is held as is, even if the generation of the operation inhibit signal is delayed from the generation of the write enable signal, an operation equivalent to the case where the write inhibit operation is successful can be performed.

(Embodiment) FIG. 1 shows a block configuration of a memory circuit according to an embodiment of the present invention, in which 21 is the third
The memory cell array 11 is similar to the memory cell array 11 of FIGS. The memory cell array 21 writes the DI input content (write data) to the word position specified by the A1 manual content by separately giving the write address to A1 manual and the successive address A2 manual, and
A2: It is possible to simultaneously read stored data at word positions specified by manual content.

22 is an inverter that inverts the level of the write enable signal WE; 23 is a transparent transistor that latches the busy signal 8SY as an operation prohibition signal given from the outside (another circuit that operates in synchronization with the storage circuit in FIG. 1); This is a latch (hereinafter simply referred to as a latch). The latch 23 has an HLD (hold) input to which the output signal of the inverter 22 is supplied. 24 is an OR gate that ORs the output (output signal) of the latch 23 and the write enable signal WE; and 25 is a latch (transparent latch) for latching read data from the memory cell array 21. Latch 25 has an HLD<hold) input to which the output signal of OR gate 24 is applied.

Next, the operation of the configuration shown in FIG. 1 will be explained with reference to the timing chart shown in FIG. First, cycle T1 in FIG. 2 is a case where the busy signal 8SY is not generated and writing is performed normally. In this cycle T1, write address A is given to A1 manually, and the same address A is given to A2 manually, and the write permission signal @WE is true (true at high level).
becomes. This write enable signal WE is inverted in level by inverter 22 and supplied to the HLD input of latch 23. The latch 23 is in a transparent mode while the HLD input signal is at a low level (that is, the write enable signal WE is true);
The input signal, the busy signal BSY, is passed through as is. When the HLD input signal changes from a low level to a high level (that is, when the write enable signal WE changes from true to false), the latch 23 enters the hold mode, and the state of the busy signal BSY at that time is changed to the next HLD.
Latch until the input signal goes low. Therefore, the output signal of the latch 23 in cycle T1 is at a low level because the busy signal BSY is always at a low level (false).

When the output signal of the latch 23 is at a low level, the HLD input of the latch 25 receives the write enable signal WE from the OR gate 24.
It is supplied as is via. In this case, the storage data (A) at the word position in the storage cell array 21 specified by the read address A, which is the manual content of A2, is latched into the latch 25 in response to the change of the write permission signal WE to the true state. As a result, the DI input content (DI), which is the write data to the word position in the memory cell array 21 specified by the write address A (same as the read address), which is the manual content of A1, is directly led to the Do ratio output. Prevented.

Next, in cycle T2 of FIG. 2, the busy signal BSY is generated during writing and becomes true), and writing in this cycle T2 is desired to be prohibited. In the configuration shown in Figure 1,
The write enable signal WE is connected to the memory cell array 11 as is. Therefore, when the write enable signal WE becomes true in cycle T2, writing to the word position in the memory cell array 21 specified by the write address B, which is the manual content of A1, is performed. Well, busy signal BS
Y passes through the latch 23 as is while the write enable signal WE is true, and is latched by the latch 23 when the write enable signal WE is no longer true at the end of cycle T2. This state is maintained until the next time the write enable signal WE becomes true and writing to the same address (B in this case) is started again. Therefore, when the busy signal BSY is generated as shown in FIG. The level is high until .

The output signal of latch 23 is supplied to OR gate 24 together with write enable signal WE. The or gate 24 is the latch 2
ORL the output signal of 3 and the write enable signal WE, and
The R signal is provided to the HLD input of latch 25. This lunch 250 day D input signal is in cycle T2 in this embodiment where the busy signal BSY is generated in cycle T2.
The write enable signal WE becomes true in cycle T2 and remains high until the next write enable signal WE becomes false in cycle T3. Therefore, in cycle T2, when the busy signal BSY is generated and you want to prohibit writing to address B, and in cycle T3, when busy signal BSY is turned off, you want to write to address 8 and read from the same address B at the same time (restart). During this period, as shown in FIG. 2, the contents of address B (B) are held in the latch 25, and from the outside, writing to the memory circuit (memory cell array 21 of FIG. 1) is prohibited in cycle T2. It looks like they are doing exactly the same thing.

On the other hand, during a read-only operation, there is no need for any inhibit operation, and even if the busy signal BSY becomes true as in cycle T5 in FIG. 1-ILD input is low level and in transparent mode, Do ratio output has no effect.

[Effects of the Invention] As detailed above, according to the present invention, when an operation inhibit signal is generated in a cycle in which reading and writing from the same address are attempted at the same time, the data read at the start of this cycle is is held in a transparent latch for external output until the end of the cycle in which the operation prohibition signal turns off and the write permission signal becomes true again to restart processing, so the generation of the operation prohibition signal does not occur before the write permission signal. Even if there is a delay from the generation, and even if the set-up time of the operation inhibit signal is shorter than the pulse width of the write enable signal WE, an operation equivalent to the case where the write inhibit operation is successful can be performed. Therefore, synchronization can be easily achieved when the entire high-speed device needs to wait for its operation. In addition, even if the timing at which the operation prohibition signal applied from the outside requesting the temporary stop of processing is finalized is late, the prohibition control can be performed reliably.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a memory circuit according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation, FIGS. 3 to 8 show conventional examples, and FIG. , Figures 5 and 7 are block configuration diagrams, Figures 4 and 6 are block diagrams.
The figure and FIG. 8 are timing charts. 21...Memory cell array, 23.25...Latch (
transparent latch). Applicant's agent: Takehiko Suzue, patent attorney. 10th 20th D. 3rd mouth 40th I 50th 60th

Claims (1)

[Claims] A write address and a read address are given separately, and by making the write enable signal true, data is written to the word position specified by the write address, and data is written to the word position specified by the read address. In a memory circuit equipped with a memory cell array in which data is read from a word position, a first transparent latch has an input to which an externally applied operation prohibition signal is guided and is set in a hold mode while the write enable signal is not true. and a second transparent latch having an input to which read data from the memory cell array is guided, and at least one of the output of the first transparent latch and the write enable signal is set to a true period hold mode, A memory circuit characterized in that the output of the second transparent latch is outputted to the outside as read data from the memory cell array.