JPH01173243A - Memory protective device - Google Patents

Abstract

PURPOSE:To protect a storage area by outputting a user name corresponding to input address data from a verification table and invalidating the access as an invalid access at the time of disaccord between this user name and a user name in input data. CONSTITUTION:With respect to address data AD from a processor, the user address value is checked by a '0' decoder 48. When it is not '0', an invalid access signal generating circuit 50 is driven. In parallel with this operation, an R/W control circuit 47 reads out a user name UN in the name area of a user descriptor 51 from page data of the address in a verification table memory 46 and gives it to a disaccord detecting circuit 49. An invalid signal FAIL is issued through the circuit 50 by the disaccord output. The control circuit 47 writes '1' in the inhibit bit of the user descriptor 51 to inhibit the use and closes a gate 45 to invalidate the current access and interrupts the processor to stop the access and selects the next user. By this constitution, destruction of a memory of another user due to erroneous access of one user is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a storage protection device for a computer system.

(Prior Art) In a microprocessor system having a memory management function, storage areas are managed by a page method, a segment method, a page/segment method, a capacity check method, or the like.

Among these methods, the page method system is mainly aimed at processing large programs with a small main memory, and uses virtual addresses divided into a fixed number of bytes as shown in Figure 5. It includes a space 1, a main storage area 2 divided into a certain number of bytes, and a page table 3 for managing these areas.

In this case, the page table 3 has the same number of page descriptors 4 as the number of pages 6 (number of divisions) on the virtual address space 1, and of each page 6 on the virtual address space 1, For those transferred to each page frame (each segmented area) 5 of type @2, the value +i is set in the page fault bit 7 of the page descriptor 4 corresponding to the transferred page 6.
0++ is written, and the page frame number of the transfer destination is also written in the page frame number area 8.

And logical address data (virtual address data) A
When I is output, the page descriptor 4 specified by the page address data P of this virtual address data A is read from the page table 3, and whether the page fault bit 7 is the value "0" or not. is checked. If this is the value "'0", the page descriptor 4
One page frame 5 in the main storage area 2 is selected based on the page frame number written in the page frame number area 8 of The address specified by the location address data in □ is accessed.

Furthermore, if the page fault hit 7 of the page descriptor 4 corresponding to the page address data P of the virtual address data A is the value "1", an interrupt occurs and O5 (
operating system) is started.

Then, by this O8, the page address data P
The contents of the page 6 corresponding to this page 6 are read from the virtual address space 1 and transferred to the empty page frame 5 of the main storage area 2, and the page fault of the page descriptor 4 corresponding to this page 6 is read out from the virtual address space 1. The bit 7 is set to the value "0", and the page frame number of the transfer destination is further written in the page frame number area 8, and the interrupt operation ends. Thereafter, the main storage area 2 is accessed based on the virtual address data A1 as described above.

At this time, if there is no free page frame 5 on the main memory area 2, the contents of the page frame 5 that are not scheduled to be used immediately are transferred from the main memory area 2 side to the virtual address space 1 side, and the contents are transferred to the free page frame 5. While the frame 5 is created, the contents of the page 6 corresponding to the page address data P are read from the virtual address space 1 side and transferred into the empty page frame 5. Also, in parallel with this operation, this page 6
The contents of the page descriptor 4 corresponding to the page descriptor 4 are updated.

In addition, the main purpose of the segment method system is to be able to process large programs on the main memory, similar to the page method described above, and the system is based on the sixth method.
As shown in the figure, it includes a virtual address space 11 divided into segments 14 for each logical information unit, a main storage area 12, and a segment table 13 for managing these.

In this case, the segment table 13 has the same number of segment descriptors 15 as the number of segments 14 (number of divisions) on the virtual address space 11. For those transferred to the storage area 12, the value ``0'' is written to the segment fault hit 16j of the segment descriptor 15 corresponding to the transferred segment 14, and the address data area 17 in the main memory is written. Data AS of the start address of the transfer destination (start address on the main storage area 12) is written within.

And logical address data (virtual address data) A
When I is output, the segment table 13 is created based on the segment address data S of this virtual address data A1.
The segment descriptor 15 in the segment descriptor 15 is read out, and it is checked whether the segment fault bit 16 has the value "0". If it is the value "0", the main memory address of the segment descriptor 15 is read out. One of the addresses in the main storage area 12 is accessed based on the start address data AS written in the data area 17 and the locating address data L of the virtual address data A1.

In addition, the segment of the segment descriptor 15 corresponding to the segment address data P of the virtual address data A1
If fault bit 16 has the value "'1", an interrupt is generated and O8 is activated.

Then, by this O5, the contents of the segment 14 corresponding to the segment address data S are read out from the virtual address space 11 and transferred to a vacant area of the main storage area 11, and the contents of the segment 14 corresponding to this segment 14 are Descriptor 15 segment fault
Bit 16 is set to the value "0". Also, at this time, the start address data AS of the transfer destination is written into the address area 17 in the main memory, the interrupt operation ends, and then the normal access operation returns.

At this time, if there is no free space on the main storage area 12, the contents of segments that are not scheduled to be used immediately are transferred from the main storage area 12 side to the virtual address space 11 side, and a free space is created. The contents of the segment 14 corresponding to the segment address data S are read from the virtual address space 11 side and transferred to the free area.

In parallel with this, the contents of the segment descriptors 15 corresponding to these segments 14 are updated.

In addition, the system based on the page/segment method has the main purpose of being able to process large programs in the main storage area, similar to the above-mentioned page method and segment method, and as shown in Figure 7. It includes a virtual address space 21, a main storage area 22, a segment table 23 for managing these areas, and a page table group 24.

In this case, the virtual address space 21 includes a plurality of segments 25 divided into logical information units. Each of these segments 25 is divided into predetermined sizes and each constitutes a page 26.

Further, the main storage area 22 is divided into sections of a certain size, each of which constitutes a page frame 27.

Furthermore, the segment table 23 has the same number of segment descriptors 28 as the number of 25 segments (number of divisions) on the virtual address space 21, and among the pages 26 on the virtual address space 21, the main storage area 22, the value "0" is written to the segment fault hit 29 of the segment descriptor 28 corresponding to the segment 25 that includes the transferred page 26, and Address data (address on page table 24) of page table 31 managing this page 26 (address on page table 24) A p s is written in 30 .

The page table group 24 includes the same number of page tables 31 as the number of segments 25 in the virtual address space 21.

Each page table 31 has the same number of page descriptors 32 as the number of pages 2G in the corresponding segment 25, and among each page 26 on the virtual address space 21,
For those transferred to each page frame 27 of the main storage area 22, the value ``'0'' is written to the page fault bit 33 of the page descriptor 32 corresponding to the transferred page 26. The page frame number AP of the transfer destination is written in the page frame number area 34.

And logical address data (virtual address data) A
When I is output, the segment table 23 is created based on the segment address data S of this virtual address data A1.
The segment descriptor 28 within is read and it is checked whether its segment fault bit 29 has the value "0". And if this is the value “O”, then
Page address area 30 of this segment descriptor 28
One page table 31 is selected from the page table group 24 based on the address data A P S written therein.

After this, the page descriptor 32 in the page table 31 is read based on the page address data Pζ of the virtual address data A1, and it is checked whether the page fault hit 33 is the value "0". If this value is "0", the page frame 27 in the main storage area 22 is selected based on the page frame number A p written in the page frame number area 34 of this page descriptor 32. One of them is selected.

Thereafter, one of the addresses within this page frame 27 is accessed based on the locating address data L of the virtual address data A1.

Also, the segment of the segment descriptor 28 corresponding to the segment address data S of the virtual address data A1
Fault bit 29 and page descriptor 32
If fault bit 33 has the value "1", an interrupt is generated and O8 is activated.

Then, the page 2 corresponding to the segment address data S and the page address data P is O5.
6 is read from the virtual address space 21 and transferred to the empty page frame 27 of the main storage area 22, and the segment fault bit 29 of the segment descriptor 28 corresponding to this segment 25 is set. Value “0”
” (Rubbed.

Also, at this time, address data A of the page table 31 managing this page 26 is stored in the page address area 30.
ps is written and the page fault hit 3 of the page descriptor 32 corresponding to this page 26 is written.
3 is set to the value "0", and the page frame number A p p of the transfer destination is written in the page frame number area 34. After this, the interrupt operation ends.

In addition, in the page transfer operation described above, the main storage area 2
If there is no free page frame 27 on the page frame 2, contents that are not scheduled to be used soon are transferred from the main memory area 22 side to the virtual address space 21 side in page frame units, an empty page frame 27 is created, and The contents of the page 26 corresponding to the segment address data S and page address data P are read from the address space 21 side and transferred to the empty page frame 27. In parallel with this, the contents of the segment descriptor 28 and the page descriptor 32 corresponding to each of these segments 25 and pages 26 are updated.

By the way, can each of these methods be used in a system that has a memory management function? In a microprocessor system that has a process switching function and does not output the internal gfl status or does not have a memory management function, each of these methods cannot be used. method could not be used.

For this reason, in such a microprocessor system, when the installed memory is divided and used by a plurality of users, erroneous access by one user may destroy the memory contents of another user.

(Object of the Invention) In view of the above circumstances, the present invention provides a memory protection system that can protect storage areas even in a system using a microprocessor that has a process switching function, does not output internal status, or does not have a memory management function. The purpose is to provide equipment.

(Summary of the Invention) In order to solve the above problems, the memory protection device according to the present invention outputs user name data corresponding to the address data from the verification table when address data is output from the microprocessor. , checks whether this matches the user name data included in the address data, and if they do not match, it is determined that the access is not by a legitimate user and the current access is invalidated.

(Embodiment) FIG. 1 is a circuit block diagram showing an example of a microprocessor system to which an embodiment of the storage protection device according to the present invention is applied.

The microprocessor system shown in this figure includes a microprocessor 40, an input/output device 4J, a storage device 42, and a storage protection device 43, and is used by a plurality of users in a time-sharing manner.

The input/output device 41 includes an input device such as a keyboard and an output device such as a CRT (display), and supplies data, commands, etc. input via the input device to the microprocessor 40, The display data etc. output from 40 are displayed on the output device.

Furthermore, the storage device 42 has a storage area of n as shown in FIG.
Main memory 4 divided into pages 55a to 55n
4, and a gate 45 connecting the data terminal of the main memory 44 and the data terminal of the microprocessor 40.
Of course, each page has a specified user.

When the address data AD is supplied from the microprocessor 40, the address specified by the address data in the main memory 44 becomes active, and the data stored at this address is read out and sent to the microprocessor 40. Data supplied or supplied from this microprocessor 40 is written to the z location. Further, at this time, if the illegal access signal FAIL is supplied, the gate 45 is closed and reading and writing of data is prohibited.

In addition, the microprocessor 40 includes a CPU, various timing generators, address decoders, etc.
Address data AD in the format shown in FIG. 3 is generated based on instructions manually inputted from the input/output device 41, written procedures, etc., and the storage device 42 is accessed to perform various processing.

Furthermore, when the illegal access signal FAIL is supplied,
After an interrupt occurs in the microprocessor 40, the processing of the user who caused the generation of this unauthorized access signal FAIL is invalidated.

The storage protection device 43 also includes a verification table memory 46, a read/write control circuit 47, as shown in FIG.
It is equipped with a "0" decoder 48, a mismatch detection circuit 49, and an illegal access signal generation circuit 50.
It is checked whether the access specified by is by a legitimate user, and if it is an unauthorized access, an unauthorized access signal FAIL is generated to prohibit use by this user.

As shown in FIG. 3, the verification table memory 46 stores the same number of user descriptors 51 as the number of pages of the main memory 44.
The user name area 52 of each user descriptor 51 includes each page 55a to 55 of the main memory 44.
5. Name of each user using 1 (user name UN is written.

Then, while the page address data PAD of the address data AD is being supplied, the read signal R (second
) is supplied, the user name UN written in the user name area 52 of the user descriptor 51 specified by the page address data PAD is read out, and this is supplied to the mismatch detection circuit 49. Ru.

Also, the page address data P of the address data AD
When the write signal W (see FIG. 2) is supplied while AD is being supplied, the page address data PA
In the user name area 52 of the user descriptor 51 specified by D, the name indicated by the user name data UDD from the microprocessor 40 is the user name U.
Written as N.

In addition, the use prohibition bit 53 of each user descriptor 51 is initially written with 1 and a value ``0'' indicating that it can be used.Then, while the illegal access signal FAIL is being supplied, the write signal W is supplied, a value "P1" indicating use prohibition is written to the use prohibition bit 53 of the user descriptor 51 selected at this time.

Furthermore, when the user name data UND of the address data has a value other than "0", that is, when a user other than O8 of the system uses this microprocessor system, the decoder 48 detects this and issues a check permission. A signal (“0” signal) CIIEN is generated and supplied to the illegal access signal generation circuit 50.

Further, the mismatch detection circuit 49 is equipped with a digital comparator and the like, and the user name UN indicated by the user name data D of the address data AD and the user name UN supplied from the verification table memory 46 are When they do not match, a mismatch signal S1 is generated and supplied to the illegal access signal generation circuit 50.

The illegal access signal generation circuit 50 includes AND-1-5.
4, and when the mismatch signal S1 is supplied from the mismatch detection circuit 49 while the check enable signal CHEN is being supplied from the "0'' decoder 48, an illegal access signal FAIL is generated. is supplied to the read/write control circuit 47, the gate 45 of the storage device 42, and the interrupt terminal of the microprocessor 40.

The read/write control circuit 47 also receives a read/write control signal R/W from the microprocessor 40.
A read signal R and a write signal W are supplied to the verification table memory 46 based on the signal W.

Next, the operation of this embodiment will be explained with reference to the timing charts shown in FIGS. 4(a) to 4(d).

First, as shown in FIG. 4(a), the microprocessor 40
When address data AD is output from address data AD, the value of user address data UND of D is checked by the "0" decoder 48.

If this value is other than "0", the "0" decoder 48 determines that the system is being used by a user other than the system, outputs the check permission signal CI-IEN, and puts the illegal access signal generation circuit 50 into the operating state. Make it.

Also, in parallel with this operation, the read/write control circuit 47
sets the verification table memory 46 to read operation, and reads the user name data 52 of the user descriptor 51 specified by the page address data PAD of the address data AD.
The user name UN written in is read out and supplied to the mismatch detection circuit 49.

If the user name UN output from the verification table memory 46 does not match the user name UN indicated by the user name data IJND of the address data AO, the mismatch detection circuit 49 detects this and it is invalid. From the access signal generation circuit 50 to the fourth
The illegal access signal FAIL is output as shown in FIG. 3(c).

As a result, the read/write control circuit 47 prohibits the use of the user descriptor 51 selected at this time 53i.
This value "1" is written to prohibit future use by this user, and the gate 45 of the storage device 42 is closed to invalidate the current access as shown in FIG. 4(b).

At this time, as shown in FIG. 4(d), an interrupt is applied to the microprocessor 40 to abort the current access, and the process switching function of the microprocessor 40 automatically selects the desired user. .

In addition, in the above-described operation, the verification table memory 4
If the user name UN output from 6 and the user name UN indicated by the user name data UND of the address data AD match, the current access is determined to be an access by a legitimate user, and the data is stored. Data is read from the device 42 and data is written to the storage device 42.

As described above, in this embodiment, when the user attempts to access a page other than the predetermined page,
Since this access is disabled and future use by this user is prohibited, the following effects can be obtained.

(a) Since address conversion is not performed as in the conventional page segment method, it is possible to prevent the storage device from being accessed illegally without using a circuit such as an MMU (memory management unit).

(b) Also, since the process switching function of the microprocessor 40 is used to switch users, it is possible to prevent unnecessary overhead from occurring when switching users, as is the case when switching users using O8, etc. .

Furthermore, in the embodiment described above, the names of each user (user name data UND) are simply made different, and the correlation between these is left to the discretion of the system designer; however, the Hamming distance ( It is also possible to increase the inter-symbol distance to reduce the possibility of misjudgment at the time of user check.

(Effects of the Invention) As explained above, according to the present invention, even in a microprocessor that does not have a memory management function, which was considered impossible in the past, and does not output information indicating the internal state, programs of each user can mutually communicate with each other. It is possible to prevent interference, thereby guaranteeing the operation of each user's program, and preventing one user's erroneous access from destroying another user's memory contents. be able to.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an example of a microprocessor system to which an embodiment of the storage protection device according to the present invention is applied, and FIG. 2 is a circuit block diagram showing details of the storage device and storage protection device shown in FIG. 1. , FIG. 3 is a schematic diagram for explaining the storage protection device shown in FIG. 2, and FIGS. 4(a) to (d)
) are timing charts showing operation examples of the same embodiment,
FIG. 5 is a schematic diagram for explaining the conventional page method, and FIG. 6 is a schematic diagram for explaining the conventional segment method.
FIG. 7 is a schematic diagram for explaining the conventional page segment method. 40... Microprocessor, 46... Verification table (verification table memory), 49... Judgment unit (mismatch detection circuit). Patent applicant: Toyo Tsushinki Co., Ltd.

Claims (1)

[Claims] A memory protection device that disables access to a storage device by a microprocessor when the access is not by a legitimate user, and a user who takes in address data output from the microprocessor and responds to this address data. a verification table that outputs name data; and a determination unit that determines whether the user name data output from the verification table matches the user name data included in the address data; What is claimed is: 1. A storage protection device that controls invalidation/validity of access to a storage device based on a determination result of a storage device.