JPH01172150U - - Google Patents
Info
- Publication number
- JPH01172150U JPH01172150U JP6643588U JP6643588U JPH01172150U JP H01172150 U JPH01172150 U JP H01172150U JP 6643588 U JP6643588 U JP 6643588U JP 6643588 U JP6643588 U JP 6643588U JP H01172150 U JPH01172150 U JP H01172150U
- Authority
- JP
- Japan
- Prior art keywords
- board
- dual port
- port ram
- board testing
- host computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図はこの考案の一実施例による基板試験装
置を示す構成図、第２図はこの考案の他の実施例
を示す基板試験装置の構成図、第３図は従来の基
板試験装置を示す構成図である。
図において、６はＣＲＴデイスプレイ装置、７
はキーボード、８はフロツピーデイスクドライブ
装置、９はデユアルポートＲＡＭ、１０は基板試
験装置、１１は上位のコンピユータである。なお
、図中、同一符号は同一、又は相当部分を示す。
Fig. 1 is a block diagram showing a board testing device according to one embodiment of this invention, Fig. 2 is a block diagram of a board testing device showing another embodiment of this invention, and Fig. 3 shows a conventional board testing device. FIG. In the figure, 6 is a CRT display device; 7 is a CRT display device;
8 is a keyboard, 8 is a floppy disk drive device, 9 is a dual port RAM, 10 is a board testing device, and 11 is a host computer. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
する入力手段・表示手段と上記基板の種類に応じ
た試験手段を記憶した記憶媒体を有する外部記憶
手段とを備えた上位のコンピユータと、この上位
のコンピユータとデユアルポートＲＡＭを介して
接続される基板試験装置本体とから成り、上記入
力手段から入力された試験手段を上記外部記憶手
段からデユアルポートＲＡＭを介して基板試験装
置本体に取り込むとともに、この試験手段に基づ
いた試験結果を上記デユアルポートＲＡＭに書き
込むことを特徴とする基板試験装置。 A host computer equipped with an input means/display means for inputting and displaying the type of board to be tested, and an external storage means having a storage medium storing test means corresponding to the type of board, and this host computer. and a board testing apparatus main body connected via a dual port RAM, and the test means inputted from the input means is imported from the external storage means to the board testing apparatus main body via the dual port RAM. A board testing device characterized in that a test result based on the above is written into the dual port RAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6643588U JPH01172150U (en) | 1988-05-20 | 1988-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6643588U JPH01172150U (en) | 1988-05-20 | 1988-05-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01172150U true JPH01172150U (en) | 1989-12-06 |
Family
ID=31291840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6643588U Pending JPH01172150U (en) | 1988-05-20 | 1988-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01172150U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0773077A (en) * | 1993-06-29 | 1995-03-17 | Koninkl Ptt Nederland Nv | Processor circuit containing first processor and system containing processor circuit and second processor |
-
1988
- 1988-05-20 JP JP6643588U patent/JPH01172150U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0773077A (en) * | 1993-06-29 | 1995-03-17 | Koninkl Ptt Nederland Nv | Processor circuit containing first processor and system containing processor circuit and second processor |
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