JPH01171316A - Clock signal fault detecting circuit - Google Patents

Abstract

PURPOSE:To detect a fault state of a clock signal with simple constitution by adding a simple circuit to an ECL circuit and selecting its circuit constant so that a level of an output signal is changed only when a clock signal being an input signal is not normal. CONSTITUTION:An ECL(Emitter Coupled Logic) circuit consists of a current switch circuit 10 and emitter follower circuits 11, 12, and further comprises capacitors C1, C2 connected between each output terminal of the emitter followers 11, 12 and ground and an OR circuit 13. Resistors R4, R5 and capacitors C1, C2 being components of the emitter followers 11, 12 are selected so that one of output voltages of two emitter followers does not reach a threshold level or below when two signals in opposite phase are inputted to the emitter followers 11, 12 from a current switching circuit 10. When a normal clock signal is inputted, the signal level at the output terminal is always kept to logic '0' and if any clock pulse is not outputted even tentatively, the signal level at the output terminal goes to logic '1'.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a clock signal abnormality detection circuit, and particularly to a clock signal abnormality detection circuit.
The present invention relates to a tarlock signal abnormality detection circuit that detects an abnormal state of a clock signal distributed to an SI.

[Conventional technology]

The present invention deals with abnormal states of the lock signal, such as the period of the clock signal supplied to the logic device, which usually changes between high and low levels at a constant period, or the clock pulse is not output. However, conventionally, abnormal states of clock signals have not been detected in this way.

[Problem that the invention seeks to solve]

In general, logic LSI (Larg
eScale Integration) typically includes
A clock signal with a constant cycle is supplied, and if an abnormal state of the clock signal occurs such that the clock signal is temporarily not output or the cycle becomes long, the logic device malfunctions.

Conventionally, there was no means for detecting such an abnormal state of the lock signal, so there was a problem in that it was impossible to determine whether the malfunction of the logic device was caused by an abnormality in the clock signal or another cause.

The present invention was made in view of these circumstances, and
It is an object of the present invention to provide a clock signal abnormality detection circuit that can detect an abnormal state of a clock signal with a simple configuration.

[Means for solving problems]

In the clock signal abnormality detection circuit according to the present invention, the emitters of a pair of transistors are commonly connected and connected to a constant current source, and the base potential of one of the transistors in the pair is a threshold that serves as a reference for switching. This current switch circuit consists of a transistor and a resistor, and a current switch circuit that outputs two signals that are set at the same level and have a constant period and are in an antiphase relationship to each other by inputting a clock signal of a constant period to the base of another transistor, and a transistor and a resistor. Of the two signals that are
Two emitter followers that receive one of the signals, a capacitor connected between the output ends of these two emitter followers and the power supply or ground, and one of the output voltages of the two emitter followers described above is a current switch circuit. and a detection circuit that detects a state in which the switching threshold level has become lower than the switching threshold level.

The constants of the resistors and the above-mentioned capacitors that constitute the two emitter followers are such that when two signals having mutually opposite phases from the current switch circuit are input to the two emitter followers, One of the output voltages is selected to a value that does not fall below the threshold level.

Further, a constant current source may be used instead of the resistors forming the two emitter followers.

With the above configuration, according to the present invention, it is possible to determine whether a malfunction of a logic device is due to an abnormality in the clock signal.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of a clock signal abnormality detection circuit according to the present invention. In the figure, the clock signal abnormality detection circuit includes a current switch circuit 10, two emitter followers 11.12, capacitors C1 and C2 connected between the output ends of these emitter followers 11.12 and ground, and an OR circuit. It consists of 13.

The current switch circuit 10 includes transistors Q1 and Q2.
, Qs and resistors R2 and R3, the emitters of transistors Q, , Q2 are commonly connected, and are configured to be driven at a constant current by transistor Q3 and resistor R3. A clock signal is input to the base of the transistor Q1, and the base potential of the transistor Q2 is set to a threshold level serving as a reference for switching in the current switch circuit 10, which is -1.2V in this embodiment. By the way, transistor Q3
The current value of the constant current circuit is determined by the base potential of , and this base potential is the output signal 1 of the current switch circuit 10.
The voltage amplitude (absolute value) of 03.104 is set to 0.8■.

Emitter follower 11 is connected to transistor Q4 and resistor R1, and emitter follower 12 is connected to transistor Q4.
, and resistor R5, and their output signals 105, 106 are connected to NΔAND gates 131, 132, 13.
The signal is input to an OR circuit 13 consisting of 3.

In addition, the current switch circuit 10 and the emitter follower circuit 11.12 provide a general ECL (εm1tter C
ouupIed Logic) circuit is configured.

Note that the logic "0" at the output terminal of the current switch circuit 10 is 0■ to 0.4V, and the logic "1" is -0.4V to -.
〇, 8■, and the input terminal of the current switch circuit 10,
Output terminal of emitter follower 11.12 and OR circuit 1
-Logic "0" at the output terminal of 3 -0,8V to -1
, 2■, and logic "1" is defined as -1,2v to -1,6■.

The operation of the clock signal abnormality detection circuit having the above configuration will be explained with reference to the timing charts of FIGS. 2 and 3.

FIG. 2 shows the circuit operation when the clock signal is normal, and FIG. 3 shows the circuit operation when the clock signal is abnormal.

First, when a clock signal with a high level of 10.8V and a low level of -1.6V with a cycle T is input to the input 4100 of the current switch circuit 10 (Fig. 2(a)), one output of the current switch 10 From one end, a signal 103 that is in phase with the clock signal has a high level of 0■ and a low level of -0.8V, and from the other output end, a signal 103 that is in phase with the clock signal has a high level of 0■ and a low level of Q. , 3V (7)
A signal 104 is output to the bases of transistors Q, , Qs in emitter follower IL12 (see Fig. 2(b)).
), (C)). At this time, the signal 103 is logic “
When the logic changes from “1” to “0”, the emitter follower 11
Transistor Q4 becomes conductive, and capacitor C
3 is charged.

Further, when the signal 103 changes from logic "0" to logic "1", transistor Q4 becomes non-conductive, and the charge accumulated in capacitor C4 is discharged via resistor R4.

However, during period T/2 when the signal 103 is at logic "1", the level of the output signal 105 of the emitter follower 11 is -
The constants of the resistor R4% and the capacitor C1 are selected so that the voltage does not go below 1.2V (this is the switching threshold level of the current switch circuit 10). Therefore, the input terminal 1 of the current switch circuit 10
When a clock signal with a pulse width T/2 and a period T as shown in FIG. d)).

Similarly, the constants of the resistor R5 and capacitor C2 are selected so that the signal level at the output end of the emitter follower 12 is maintained at logic "0".

Therefore, the output signals 105, 106 of these two emitter followers 11, 12 (Fig. 2(d), (e))
The signal level at the output end of the OR circuit 13 which calculates the logical sum of , is logic "0". (Figure 2(f)).

Next, the circuit operation when the clock signal is abnormal will be explained.

3 (a) at the input 1100 of the current switch circuit 10.
As shown in ), it is assumed that one lock pulse is missed and the clock pulse period becomes temporarily longer, and a lock signal is input. In this case, the period during which the level of the output signal 104 of the current switch circuit 10 is logic "1" is 3T/2 (FIG. 3(C)), and the charge accumulated in the capacitor C2 is transferred via the resistor R5. Discharging time becomes longer. For this reason, the output signal of the emitter follower 12 becomes lower than the switching threshold level of the current switch circuit 10 (-1.2) within the period of 3T/2 and becomes logic "1", and therefore the OR circuit 13 The signal level at the output terminal 107 becomes logic "1" (FIGS. 3(e) and 3(f)).

As explained above, according to this embodiment, when a normal lock signal with pulse width T/2 and period T is input to the input terminal as an input signal, the signal level at the output terminal is always maintained at logic "0". If even one clock pulse is temporarily not output as a clock signal, the signal level at the output terminal becomes logic "1", and an abnormal state of the clock signal can be detected.

Furthermore, when the period of the clock signal becomes longer, it is similarly detected as an abnormality of the clock signal.

〔Effect of the invention〕

As explained above, in the present invention, a simple circuit is added to the ECL circuit, and these circuit constants are selected so that the level of the output signal changes only when the clock signal, which is the input signal, is not normal. According to the invention, it is possible to realize a clock signal abnormality detection circuit with a simple configuration capable of detecting an abnormal state of a clock signal.

Therefore, if the clock signal abnormality detection circuit according to the present invention is used in a logic device, when the logic device malfunctions, it can be determined whether the malfunction is due to an abnormality in the clock signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the clock signal abnormality detection circuit according to the present invention, and FIG. 2 is a timing chart showing the operating state of each part of the clock signal abnormality detection circuit when the clock signal is normal. , FIG. 3 is a timing chart showing the operating state of each part of the clock signal abnormality detection circuit when the clock signal is abnormal. 10...Current switch circuit, 11.12.
...Emitter follower, 13...OR circuit, Ql to Q5...Transistor, C+, C
2... Capacitor, R1-R5... Resistor, 1 3 1-1 33... NAND
Gate. Applicant NEC Corporation Agent Patent Attorney Masao Yamauchi

Claims (1)

[Claims] 1. The emitters of the pair of transistors are commonly connected and connected to a constant current source, and the base potential of one of the pair of transistors is set to a threshold level serving as a reference for switching. , and a current switch circuit that receives a clock signal of a fixed period and outputs two signals having a mutually antiphase relationship to the base of the other transistor, and a current switch circuit that is made up of a transistor and a resistor and outputs from this current switch circuit. two emitter followers each receiving one of the two signals; a capacitor connected between the output ends of these two emitter followers and a power supply or ground; and one of the output voltages of the two emitter followers. a detection circuit that detects a state in which one of the current switch circuits has become lower than the switching threshold level of the current switch circuit; A clock signal characterized in that when two signals having mutually opposite phases from a circuit are input, one of the output voltages of these two emitter followers is selected to a value that does not fall below the threshold level. Abnormality detection circuit. 2. The clock signal abnormality detection circuit according to claim 1, wherein a constant current source is connected in place of the resistors constituting the two emitter followers.