JPH01170090A - Soldering - Google Patents
SolderingInfo
- Publication number
- JPH01170090A JPH01170090A JP32700087A JP32700087A JPH01170090A JP H01170090 A JPH01170090 A JP H01170090A JP 32700087 A JP32700087 A JP 32700087A JP 32700087 A JP32700087 A JP 32700087A JP H01170090 A JPH01170090 A JP H01170090A
- Authority
- JP
- Japan
- Prior art keywords
- soldering
- flux
- land
- chip
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 claims abstract description 26
- 230000004907 flux Effects 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910000990 Ni alloy Inorganic materials 0.000 claims 1
- 229920002803 thermoplastic polyurethane Polymers 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 35
- 230000000694 effects Effects 0.000 abstract description 4
- 230000002411 adverse Effects 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 1
- 238000009736 wetting Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000002457 bidirectional effect Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 2
- 244000007853 Sarothamnus scoparius Species 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000004100 electronic packaging Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000003973 paint Substances 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000006260 foam Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010019 resist printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3489—Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はプリント配線板に、抵抗、コンデンサなどの表
面実装チップ状部品をリフローはんだ付けするのに好適
なプリント配線板上のはんだ付けランド形成方法に関す
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the formation of soldering lands on a printed wiring board suitable for reflow soldering surface-mounted chip-like components such as resistors and capacitors to the printed wiring board. Regarding the method.
従来のプリント配線板上に、抵抗、コンデンサなどの表
面実装部品をはんだ付けする方法として、ハイブリッド
サーキット第9巻(1986年1月)第9頁から第12
頁(Hybrid C1rcuits No、 9(J
anuary 1986) pp9−123において、
赤外線によるリフローはんだ付け方法が論じられている
。Hybrid Circuit Vol. 9 (January 1986), pages 9 to 12, describes how to solder surface mount components such as resistors and capacitors onto a conventional printed wiring board.
Page (Hybrid C1rcuits No. 9 (J
annual 1986) pp9-123,
An infrared reflow soldering method is discussed.
また、エレクトロニックパッケージングアンドプロダク
ション第25巻第2号(1985年2月)第96頁から
第99頁(E 1ectronie P ackagi
ng &Production vol、25. No
、 2 (February 1985)pp96−9
9 )に、表面実装部品のウェーブソルダリング技術の
問題点について論究されている。Also, Electronic Packaging and Production Vol. 25, No. 2 (February 1985), pages 96 to 99 (E 1 electronic packaging and production)
ng & Production vol, 25. No
, 2 (February 1985) pp96-9
9) discusses the problems of wave soldering technology for surface mount components.
これら従来のプリント配線板上における表面実装部品の
はんだ付け方法は、プリント配線板、例えば銅張り積層
板をエツチングして形成した配線回路板に、表面実装チ
ップ状部品のリードはんだ付け用ランドを設け、その周
辺をソルダーレジストで囲い、上記ランドに表面実装部
品のはんだ付けを行う方法が多用されている。このソル
ダーレジストはフローソルダー用に適合され、はんだ付
け中にフラックスが全面に均一に濡れ拡がることを目的
とした、少なくともフラックスと相溶性を有することを
必要とする絶縁性有機皮膜材が多く用いられ、エツチン
グ後印刷あるいは光重合または熱硬化させる方法で形成
される。しかし、このソルダーレジストは、リフローは
んだ付けにも併用されており、このため次のようなはん
だ付け欠陥が生じる一原因となっている。These conventional methods of soldering surface mount components on a printed wiring board include lands for lead soldering of surface mount chip components on a printed wiring board, such as a wiring circuit board formed by etching a copper-clad laminate. A commonly used method is to surround the land with a solder resist and then solder surface-mounted components to the land. This solder resist is adapted for use in flow soldering, and is often made of an insulating organic film material that must be at least compatible with the flux so that the flux spreads uniformly over the entire surface during soldering. , etching followed by printing, photopolymerization, or heat curing. However, this solder resist is also used in reflow soldering, which is one of the causes of the following soldering defects.
すなわち、チップ部品のリフローはんだ付けの多くの方
法は、はんだペーストを印刷あるいはデイスペンサなど
でリフローはんだ付けランド上に供給し、チップ部品を
装着したあと、適当な加熱方法でペーストを溶かしては
んだ付けする方法である。この方法においては、温度の
不均一やはんだ供給量の不均一などの原因の他、ペース
ト中のフラックスがはんだ付けするランドの周辺に流れ
出る。このため、これにはんだが引かれて、第5図に示
すごとくチップ部品の位置ずれを起こしたり、さらには
双方向ランドの一方にのみ先行してはんだ付けされるた
め、第4図に示すごとく、チップ部品が立上がってしま
う欠陥が生じるという問題があった。In other words, in many methods of reflow soldering chip components, solder paste is supplied onto the reflow soldering land using a print or dispenser, and after the chip component is mounted, the paste is melted using an appropriate heating method and soldered. It's a method. In this method, in addition to being caused by non-uniform temperatures and non-uniform solder supply amounts, flux in the paste flows out around the lands to be soldered. For this reason, solder is drawn to this, causing the chip components to be misaligned as shown in Figure 5, and furthermore, the solder is soldered to only one side of the bidirectional land first, as shown in Figure 4. However, there was a problem in that a defect occurred in which the chip component stood up.
上述したごとく、従来技術においては、ソルダーレジス
トとフラックスとが相溶性であるため。As mentioned above, in the conventional technology, the solder resist and flux are compatible.
ソルダーレジスト上へのフラックスの流出を助長するこ
とになり、これにはんだが引かれてチップ状部品の位置
ずれを起こしたり、あるいは双方向ランドの一方にのみ
先行してはんだ付けされるためにチップ状部品が立ち上
がるなどの欠陥が生ずるという問題があった。This promotes the flow of flux onto the solder resist, which may attract solder and cause the chip-shaped components to shift, or the chip may be soldered to only one side of the bidirectional land in advance. There was a problem in that defects such as shaped parts standing up occurred.
本発明の目的は、プリント配線板などに、表面実装チッ
プ状部品をはんだ付けする場合において。An object of the present invention is to solder surface-mounted chip-like components to a printed wiring board or the like.
チップ状部品の位置ずれ、あるいはチップ状部品の立ち
上がりなどの欠陥の生じないプリント配線板上に表面実
装部品のはんだ付け方法に関する。The present invention relates to a method for soldering surface-mounted components onto a printed wiring board without causing defects such as misalignment of chip-shaped components or rising of chip-shaped components.
上記本発明の目的は、プリント配線板上などにチップ状
部品をリフローはんだ付けする場合において、基材上に
形成されたソルダーレジストとはんだ付けランドとの境
界に、はんだペースト中のフラックスとは非相溶性で濡
れ拡がりにくい材料で構成された堰(せき)体を設け、
はんだペーストをはんだ付けランド上に局在させること
により。The object of the present invention is to prevent the flux in the solder paste from forming at the boundary between the solder resist formed on the base material and the soldering land when reflow soldering chip-like components onto a printed wiring board or the like. We provide a weir body made of compatible materials that do not spread easily.
By localizing the solder paste onto the soldering lands.
達成される。achieved.
なお、ソルダーレジスト全体を、フラックスとは非相溶
性の材料と置換することも一つの問題解決手段であるが
、これはリフローはんだ付けの用途にのみ限定される。Note that one solution to the problem is to replace the entire solder resist with a material that is incompatible with flux, but this is limited only to reflow soldering applications.
しかし、一般にはフローはんだ付けを併用するプロセス
が必要であり、このためフローはんだ付けには直接影響
を及ぼさない解決方法として、上記のはんだペーストを
はんだ付けランド上に局在させる局在的はんだ付け方法
を必要とするのである。However, in general, a process that uses flow soldering in combination is required, so as a solution that does not directly affect flow soldering, localized soldering, in which the solder paste described above is localized on the soldering land, is used. We need a method.
はんだ付けランドとソルダーレジストとの間に設けたせ
き体は、はんだペーストを加熱することによって低温で
溶解し発砲して濡れ拡がり始めるフラックス成分を、せ
き体の内周部のはんだ付けランド上に局在させる。さら
にはんだ合金の溶ける温度まで加熱すると、溶けたはん
だはフラックスがせき体の内周部に停留しているため上
記ランド外にはんだが引かれることがない。第5図は。The barrier body provided between the soldering land and the solder resist localizes the flux component, which melts at a low temperature by heating the solder paste and begins to foam and spread, onto the soldering land on the inner periphery of the barrier body. make it exist Furthermore, when the solder alloy is heated to a temperature at which it melts, the flux of the molten solder remains on the inner periphery of the weir, so that the solder is not drawn outside the land. Figure 5 is.
従来のせき体のない場合に、はんだ付けランド外にフラ
ックスが流れ出し、この方向にはんだが引かれて、同時
にチップ状部品が位置ずれを起こす場合を示し、極端な
時にはチップ状部品が立ち上がる場合を示している。し
たがって、フラックスがソルダーレジスト上に流れ出な
いようにすることが必要であり、本発明のはんだ付け方
法において、はんだ付けランドに設けるせき体は極めて
有効な作用を示すものである。This shows a case in which flux flows out of the soldering land when there is no conventional barrier, and the solder is pulled in this direction, causing the chip-shaped component to shift its position. In extreme cases, the chip-shaped component can stand up. It shows. Therefore, it is necessary to prevent the flux from flowing onto the solder resist, and in the soldering method of the present invention, the weir body provided on the soldering land exhibits an extremely effective effect.
以下に、本発明の一実施例を挙げ、図面に基づいてさら
に詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in more detail based on the drawings.
(実施例1)
第1図は、本発明のプリント配線板上にチップ状部品を
はんだ付けした場合の構成の一例を示す平面図で、第2
図は第1図の側面を示す側面図である。(Example 1) FIG. 1 is a plan view showing an example of the configuration when chip-shaped components are soldered onto the printed wiring board of the present invention.
The figure is a side view showing the side of FIG. 1.
図において、プリント板の基材6の上に形成した銅箔で
形成された双方向ランド3の周辺は、ソルダーレジスト
5で囲まれている。このソルダーレジスト5は、双方向
ランド3上に重なっていることもある0本発明はこれら
の境界に、フラックスとは濡れにくい材料を用いたせき
体4を、双方向ランド3を取り囲むように構成している
。チップ状部品1の電極2は当然せき体4内に装着され
る。せき体材料としては、銅張り積層板の製造プロセス
を考慮し、レジスト印刷、硬化後にせき体を印刷供給す
る方法を採用し、かつ、リフローはんだ付けの耐熱性お
よび絶縁性などを考慮してウレタン塗料を用いた。In the figure, a bidirectional land 3 made of copper foil formed on a base material 6 of a printed board is surrounded by a solder resist 5. This solder resist 5 may overlap the two-way land 3. The present invention includes a weir body 4 made of a material that is difficult to get wet with flux at these boundaries so as to surround the two-way land 3. are doing. The electrode 2 of the chip-shaped component 1 is naturally mounted within the weir body 4. Considering the manufacturing process of copper-clad laminates, we adopted a method of resist printing and printing and supplying the barrier body after curing, and urethane was used as the material for the barrier body, taking into consideration the heat resistance and insulation properties of reflow soldering. Paint was used.
もちろん、これらの必要とする特性を満足するならば、
せき体材料はウレタン塗料に限定されるものではない。Of course, if these required characteristics are satisfied,
The material for the weir body is not limited to urethane paint.
(実施例2)
本発明の他の実施例として、第3図に示すように、双方
向ランド3上をそれぞれ個別に取り囲む方法で、はんだ
やフラックスに濡れにくい金属材料でせき体8を構成し
ている。このような材料尼して、銅箔エツチング工程の
後に、めっき法で供給することを検討した結果、ボロン
入りのニッケルめっきが適切であることを見出した。こ
の理由は、ニッケルめっきの表面にボロン濃度の高い皮
膜が形成されるためフラックスが濡れないからである。(Embodiment 2) As another embodiment of the present invention, as shown in FIG. 3, the weir body 8 is constructed of a metal material that is difficult to get wet with solder or flux by a method of individually surrounding the tops of the two-way lands 3. ing. As a result of considering the possibility of supplying such a material by plating after the copper foil etching process, it was found that nickel plating containing boron was suitable. The reason for this is that a film with a high boron concentration is formed on the nickel plating surface, which prevents the flux from getting wet.
せき体8に金属材料を用いる場合の効果は。What are the effects of using a metal material for the weir body 8?
その電気伝導性がプリント配線板の性能に悪影響を及ぼ
すことがないという利点がある。It has the advantage that its electrical conductivity does not adversely affect the performance of the printed wiring board.
また、上記実施例1の方法において、双方向ランド3周
辺をそれぞれ個々に取り囲むせき体を構成しても有効で
あることは言うまでもない。Furthermore, it goes without saying that in the method of the first embodiment, it is also effective to construct a weir body that individually surrounds the two-way land 3.
以上詳細に説明したごとく、本発明のプリント配線板上
にチップ部品などのリフローまたはフローはんだ付けを
行う方法において、はんだ付けランド外にフラックスの
流出する障害を防止し、その結果チップ状部品などのは
んだ付け後の位置ずれおよびその立ち上がりを防止する
ことができ、欠陥のないはんだ付け製品が得られる。As explained in detail above, in the method of reflow or flow soldering of chip components etc. on a printed wiring board of the present invention, troubles such as leakage of flux outside the soldering land are prevented, and as a result, chip components etc. It is possible to prevent positional displacement and rise after soldering, and a defect-free soldered product can be obtained.
なお、本発明のはんだ付け方法において、チップ部品の
立ち上がりについて、従来の方法では0.15%程度発
生していた欠陥率を、0.01%以下に低減することが
できる。また、はんだペースト中のフラックス含有量は
、一般に7〜1(wt、%であるが、多くの量がソルダ
ーレジスト上に流出するため、従来の方法では、はんだ
付けに必要な量より過剰量を必要とした。はんだペース
トの粘度は、フラックス量が多いと低下するため、従来
の方法においては粘度調整と安定性に問題が生じ、はん
だペースト供給後に、だれが生じ易かった。しがし1本
発明の方法の一例によると、フラックスを10wt%か
ら7wt%程度に低減することができ、だけの無い良質
のはんだ付け製品を得ることができた。In addition, in the soldering method of the present invention, the defect rate for rising of chip components, which was approximately 0.15% in the conventional method, can be reduced to 0.01% or less. In addition, the flux content in solder paste is generally 7 to 1 (wt,%), but since a large amount flows out onto the solder resist, in conventional methods, it is difficult to use an excess amount than is necessary for soldering. The viscosity of the solder paste decreases when the amount of flux is large, so conventional methods have problems with viscosity adjustment and stability, and drips are likely to occur after supplying the solder paste.1 stick According to an example of the method of the invention, it was possible to reduce the flux from 10 wt% to about 7 wt%, and it was possible to obtain a high-quality soldered product without any blemishes.
第1図は本発明の実施例1におけるプリント配線板上に
チップ状部品をはんだ付けした場合の構成を示す平面図
、第2図は第1図の側面を示す側面図、第3図は本発明
の実施例2におけるチップ状部品のはんだ付けランドと
せき体の配置構成を示す平面図、第4図および第5図は
従来のチップ状部品のはんだ付け欠陥を示す説明図であ
る。
1・・・チップ状部品、2・・・電極、3・・・双方向
ランド、4・・・せき体、5・・・ソルダーレジスト、
6・・・基材、7・・・はんだ、8・・・せき体、9・
・・フラックス。
箒 1 回
第 2 閏
纂 5 回
!・−千岬プ伏−91s&
2− 電極
3−m−双方向ランド
7−−−ttAJtε゛
9−−−−7フ・ノグ人FIG. 1 is a plan view showing the configuration when chip-shaped components are soldered onto a printed wiring board in Embodiment 1 of the present invention, FIG. 2 is a side view showing the side view of FIG. 1, and FIG. FIGS. 4 and 5 are a plan view showing the arrangement of soldering lands and dams of a chip-shaped component in Example 2 of the invention, and FIGS. 4 and 5 are explanatory diagrams showing soldering defects of a conventional chip-shaped component. DESCRIPTION OF SYMBOLS 1... Chip-shaped component, 2... Electrode, 3... Bidirectional land, 4... Weir body, 5... Solder resist,
6... Base material, 7... Solder, 8... Weir body, 9...
··flux. Broom 1st time 2nd Broom 5th time!・-Chimisaki Pubushi-91s & 2- Electrode 3-m-Two-way land 7---ttAJtε゛9----7 Fu Nogu person
Claims (3)
る領域であるはんだ付けランドを複数個形成させて、上
記表面実装部品をはんだ付けする方法において、上記は
んだ付けランドに対して、単独もしくは2個以上の複数
のはんだ付けランドを包囲し、かつはんだ付けフラック
スと濡れにくい材料によつて構成されるせき(堰)体を
、上記はんだ付けランドの周辺近傍に設けて、上記表面
実装部品のはんだ付けを行うことを特徴とするはんだ付
け方法。1. In the method of soldering the above-mentioned surface-mounted components by forming a plurality of soldering lands, which are areas for soldering surface-mounted components, on the printed wiring board, one or more soldering lands are formed for the above-mentioned soldering lands. A weir body that surrounds the plurality of soldering lands and is made of soldering flux and a material that is difficult to wet is provided near the periphery of the soldering lands to prevent soldering of the surface mount components. A soldering method characterized by:
付け方法であることを特徴とする特許請求の範囲第1項
に記載のはんだ付け方法。2. The soldering method according to claim 1, wherein the soldering method is a flow or reflow soldering method.
ッケル合金からなることを特徴とする特許請求の範囲第
1項または第2項に記載のはんだ付け方法。3. 3. The soldering method according to claim 1, wherein the weir body is made of a urethane resin or a nickel alloy containing boron.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32700087A JPH01170090A (en) | 1987-12-25 | 1987-12-25 | Soldering |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32700087A JPH01170090A (en) | 1987-12-25 | 1987-12-25 | Soldering |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01170090A true JPH01170090A (en) | 1989-07-05 |
Family
ID=18194190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32700087A Pending JPH01170090A (en) | 1987-12-25 | 1987-12-25 | Soldering |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01170090A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0681416A3 (en) * | 1994-05-06 | 1996-07-03 | Seiko Epson Corp | Printed circuit board and method of connecting electronic parts. |
US6904673B1 (en) | 2002-09-24 | 2005-06-14 | International Business Machines Corporation | Control of flux by ink stop line in chip joining |
US8865584B2 (en) | 2010-05-18 | 2014-10-21 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
-
1987
- 1987-12-25 JP JP32700087A patent/JPH01170090A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0681416A3 (en) * | 1994-05-06 | 1996-07-03 | Seiko Epson Corp | Printed circuit board and method of connecting electronic parts. |
US5943217A (en) * | 1994-05-06 | 1999-08-24 | Seiko Epson Corporation | Printed circuit board for mounting at least one electronic part |
US6201193B1 (en) | 1994-05-06 | 2001-03-13 | Seiko Epson Corporation | Printed circuit board having a positioning marks for mounting at least one electronic part |
US6904673B1 (en) | 2002-09-24 | 2005-06-14 | International Business Machines Corporation | Control of flux by ink stop line in chip joining |
US8865584B2 (en) | 2010-05-18 | 2014-10-21 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
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