JPH01166538A - Field programmable gate array - Google Patents

Abstract

PURPOSE:To easily perform a custom IC in a working site by selecting a P-N junction having an intrinsic address through a decoder, and supplying a writing current to set it to a conductive state. CONSTITUTION:Inverse AND elements are arranged longitudinally and laterally in a logic circuit 400. Address signals A1-Al from an exterior decode through an input buffer 100 address lines A0-Ai by a Y decoder 200, and selects one of P-N junctions in the circuit 400. An X decoder 300 decodes address lines Ai+l-Al, and further selects (n+1) pieces of the P-N junctions from the selected set of the P-N junctions. A writing current is supplied to (n+1) pieces of the P-N junctions by (n+1) pieces of writing signal lines P1-Pn, and an insulator breakdown occurs to set it to a conductive state. Accordingly, a custom IC can be easily obtained by a P-ROM writer even in a working site.

Description

Detailed Description of the Invention (Industrial Use ￥f) The present invention relates to a gate array that is used to easily manufacture custom ICs, and particularly to a P-ROM that can be used at a work site.
Custom IC can be easily created by programming if you consult the writer.
Regarding gate arrays that can be

(Prior art) Conventionally, for gate arrays, layout design, mask production, etc. must be performed from the moment the design of the circuit to be realized is completed and the design data (for example, logical connection information) is prepared. It took several weeks from then until the actual product (sample) was completed.

(Problems to be Solved by the Invention) As mentioned above, with conventional gate arrays, a considerable amount of time and expense is required from the time the logic design of the required custom IC is completed until the time when a sample is obtained. It took a long time and a lot of money to develop the entire IC.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides means in which a plurality of inverting logic elements are arranged in an array, and the inverting logic elements are combined to obtain the required information. A gate array that realizes a custom logic circuit IC, which includes an input buffer that draws in signals from the outside, an output buffer that sends internal signals to the outside, and a logic circuit section that realizes an arbitrary logic circuit. a decoder for decoding an address signal inputted through the input buffer, and the logic circuit section includes a plurality of inverting AND elements, and a PN junction connecting the outputs and inputs of the inverting AND elements. The PN junction has a unique address assigned in advance, and the decoder selects a PN junction at an address indicated by the address signal and guides a write current to the selected PN junction. shall be.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an overall block diagram showing an IC according to an embodiment of the present invention. The input buffer 100 receives a signal from outside this embodiment (IC), converts the level, and generates a signal Is It.
, As-At, Pa-P, respectively in the logic circuit 40
0, lead to decoder 200, 300<, Y decoder 20
0 decodes the address lines A, -A, and selects one set of PN junctions (one horizontal row shown in FIG. 2) in the logic circuit section 400 through the word line. The X decoder 300 decodes the address line A1゜□-M and further selects n+1 PN junctions from the set of PN junctions that have been selected as described above (in Fig. 2, the vertical columns are selected). Depends on the matter)
6. A logic circuit that performs programming by causing dielectric breakdown by passing a write current guided by P and -P through n+1 PN junctions selected in the sixth order and making the PN junctions conductive. The unit 400 receives an input signal from the outside via the input buffer 100, performs a logical operation, and outputs the signal to the outside of the IC via the output buffer 500.

Next, a detailed description will be given of how to realize the logic functions (combinational circuit, sequential circuit) in the logic circuit section 400. The logic circuit section 400 has a plurality of inverted AND (NAND) elements arranged vertically and horizontally.

FIG. 3 shows the only NAND element (4
10) and shows part of the logic circuit 400, part of the input buffer 100, and part of the output buffer 500. As shown in the figure, the output of one NAND element is sent to the three input terminals of the four NAND elements on the top, bottom, left and right (one of them is the control signal input for setting the output of the NAND element to a high impedance state). They are connected via a PN junction.

Furthermore, the inputs of all NAND elements other than the control signal input are grounded via a PN junction.

``Here, if the input buffer 100 is
and the output buffer 500 is a NAN in the logic circuit section 400.
They are connected to the input of the D element 410 and the output of the NAND element 420, respectively, and if you want to realize the circuit shown in FIG. It's fine if you can.

The method of programming has already been described, but it will be explained in more detail below with reference to FIG. Each of the PN junctions shown in Figure 2 corresponds to the PN junctions AOI and AO shown in Figure 3.
2... corresponds to each one. and PN junction n
+1 set (one word) is assigned one address, and the Y decoder 200 selects one horizontal row.

The X-decoder 300 selects a set of PN junctions for one word in the n+1 columns. Then, the input PM is “High”
”, the write current is guided to the n+1 PN junctions by the n+1 write signal lines ?, -P.

Note that during normal operation (other than programming), PM is set to “Lo”.
Also, according to FIG. 1, the X decoder 300 is composed of n+1 selectors 310-31n, but in the second r!A, only one selector 310 is set. shown, and the others are omitted.

(Effects of the Invention) As explained below, according to the present invention, if a CAD system that converts any logic circuit into a ROM hood is available, a custom IC can be obtained immediately at the work site, shortening the development period. and cost reduction.

Additionally, the present invention can be used as a hardware simulator in creating conventional types of custom ICs.

[Brief explanation of the drawing]

FIG. 1 is an overall block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a PN junction arrangement in the embodiment, and FIG. 3 is a circuit diagram showing a part of the logic circuit section in the embodiment of FIG. , FIG. 4 is a circuit diagram showing an example of a circuit of a custom IC realized by the gate array of FIG. 1. 100... Input buffer, 200... Y7' footer, 300... - Inverted logical product (NAND) element, AOO-A15...PN junction, AND... logical product (AND) circuit.

Claims (1)

[Claims] In a gate array in which a plurality of inverting logic elements are arranged in an array, and the inverting logic elements are combined to realize a custom IC with a desired logic circuit, a signal from the outside is internally transmitted. an input buffer that draws internal signals to the outside, an output buffer that sends internal signals to the outside, a logic circuit section that realizes an arbitrary logic circuit, and a decoder that decodes the address signal input via the input buffer, The logic circuit section includes a plurality of inverting AND elements and a PN junction that connects the output and input of the inverting AND element, the PN junction having a unique address assigned in advance,
A field programmable gate array, wherein the decoder selects a PN junction at an address indicated by the address signal and directs a write current to the selected PN junction.