JPH01166377A - Error rate reducing circuit for cd signal - Google Patents

Error rate reducing circuit for cd signal

Info

Publication number
JPH01166377A
JPH01166377A JP32397787A JP32397787A JPH01166377A JP H01166377 A JPH01166377 A JP H01166377A JP 32397787 A JP32397787 A JP 32397787A JP 32397787 A JP32397787 A JP 32397787A JP H01166377 A JPH01166377 A JP H01166377A
Authority
JP
Japan
Prior art keywords
error
circuit
signal
equalizer
error rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32397787A
Other languages
Japanese (ja)
Inventor
Tokikatsu Furuichi
古市 時功
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP32397787A priority Critical patent/JPH01166377A/en
Publication of JPH01166377A publication Critical patent/JPH01166377A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a noise from being leaked into the neighborhood of a slice level by deciding asymmetry according to an error rate or the quantity of a synchronizing error and causing an equalize characteristic to be variable. CONSTITUTION:The output of an equalizer circuit 2 is inputted to a demodulating circuit 3 and demodulated. Next, this demodulating output signal is inputted to an error detecting section 4 and an error is detected. Then, this error signal is inputted to an integrator 5 and compared with a certain threshold value by a comparator 6. When the error signal is over the threshold value, the equalizer circuit 2 is controlled. Since amplitude correction is generally main for the equalizer circuit 2, it is enough to turn off the equalizer 2 to the increase of the error. Thus, the leaking-in noise due to a ringing, etc., can be reduced to a slice level position.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、LD/CD/CDV等の各種ディスクの再生
兼用プレーヤに係り、特に再生時のエラーレート低減に
好適なCD信号(再生信号)のエラーレート低減回路に
関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a player that also plays back various types of discs such as LD/CD/CDV, and particularly relates to a CD signal (playback signal) suitable for reducing the error rate during playback. This invention relates to an error rate reduction circuit.

〔従来の技術〕[Conventional technology]

従来のCD信号のエラーレート低減は、イコライザを用
い【周波数特性の劣化等を補5ことにより行っていた。
Conventionally, the error rate of CD signals has been reduced by using an equalizer to compensate for deterioration of frequency characteristics, etc.

この種の方法として例えばオーム社発行の書物「コンパ
クトディスク読本」のP129記載の如きものが知られ
ている。
As a method of this type, for example, the one described on page 129 of the book "Compact Disc Reader" published by Ohmsha is known.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術は、 CDプレーヤでCDディスクを再生
する場合であり、異種例えばcnv/x、nディスク等
を再生するプレーヤでは、レンズ開口率の差及びピック
アップ系のあおり角等により生じるアシンメトリの増加
の点については配慮がされておらず、アシンメトリ大の
ディスクを兼用プレーヤで再生しようとすると、再生不
能となるという問題がありた6 本発明の目的は、上記問題点を解決し、再生可能とする
ためのCD信号のエラーレート低減回路を提供すること
にある。
The above conventional technology is for playing back CD discs with a CD player, and in a player that plays different types of discs, such as CNV/X and N discs, it is difficult to avoid an increase in asymmetry caused by differences in lens aperture ratio, tilt angle of the pickup system, etc. No consideration was given to this point, and there was a problem that if an asymmetrical disc was tried to be played on a dual-purpose player, it would become unplayable.6 The object of the present invention is to solve the above problems and make it possible to play the disc. An object of the present invention is to provide an error rate reduction circuit for CD signals.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、アシンメトリをエラーレート又は同期エラ
ーの量により判定し、イコライズ特性を可変する事によ
り達成される。
The above object is achieved by determining asymmetry based on the error rate or the amount of synchronization error and varying the equalization characteristics.

〔作用〕[Effect]

アシンメトリ大の場合、イコライザを通す事により、ス
ライスレベル位置検出不能となり、エラーの増加となる
。そこでエラー量がある閾値を超えた場合、イコライズ
特性を可変させ、スライスレベル位置を検出し易くして
エラーの低減を図る。
In the case of large asymmetry, passing through an equalizer makes it impossible to detect the slice level position, resulting in an increase in errors. Therefore, when the error amount exceeds a certain threshold value, the equalization characteristic is varied to make it easier to detect the slice level position and reduce the error.

〔実施例〕〔Example〕

以下1本発明の一実施例を図により説明する。 An embodiment of the present invention will be described below with reference to the drawings.

図は本発明の一実施例を示すブロック図である。The figure is a block diagram showing one embodiment of the present invention.

1はピックアップ部で、図示せざるディスクのEFM信
号を抽出する。2はイコライザ回路でピックアップ部1
出力が1周波数特性を持っているのでこれを補正する。
Reference numeral 1 denotes a pickup section that extracts an EFM signal from a disk (not shown). 2 is an equalizer circuit and pickup section 1
Since the output has a one-frequency characteristic, this is corrected.

イコライザ回路2出カは復調回路3に入力され、復調さ
れる。復調出力信号をエラー検出部4に入力し、エラー
を検出する。該エラー信号を積分器5に入力し、比較器
6で、ある閾値と比較して、それを超えたらイコライザ
回路2を制御する。
The output of the equalizer circuit 2 is input to a demodulation circuit 3 and demodulated. The demodulated output signal is input to the error detection section 4 to detect errors. The error signal is input to an integrator 5, compared with a certain threshold value by a comparator 6, and if it exceeds the threshold value, the equalizer circuit 2 is controlled.

イコライザ回路2は、一般的に振幅補正が主であるので
、エラーの増加に対し、イコライザ2をOFFさせられ
る様にしておけば良い。つまり高域での振幅長を止める
拳により、リンギング等によるスライスレベル位置への
もれ込みノイズを低減させる。
Since the equalizer circuit 2 generally mainly performs amplitude correction, the equalizer 2 may be configured to be turned off in response to an increase in errors. In other words, by stopping the amplitude length in the high range, noise leaking into the slice level position due to ringing etc. is reduced.

本実施例によれば、イコライザによりスライスレベル近
傍へのノイズもれ込みを防ぐ事ができるという効果があ
る。
According to this embodiment, the equalizer has the effect of preventing noise from leaking into the vicinity of the slice level.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、兼用のプレーヤにおいて、アシンメト
リ大のディスクに対しても、イコライザを可変する事に
より、スライスレベル近傍へのノイズもれ込みを防ぐこ
とができるという効果がある。
According to the present invention, in a dual-purpose player, by varying the equalizer, it is possible to prevent noise from seeping into the vicinity of the slice level, even for highly asymmetrical discs.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例のプロ、ツク図である。 1・・・・・・・・・・・・ピックアップ部2・・・・
・−・・・・・イコライザ回路3・・・・・・・・・・
・・復調回路 4・・・・・・・・・・・・エラー検出部5・・・・・
・・・・・・・積分器 6・・・・・・・・・・・・比較器 代理人 弁理士 小 川 勝 男 ム      5
The figure is a professional diagram of one embodiment of the present invention. 1...Pickup section 2...
・−・・Equalizer circuit 3・・・・・・・・・・
... Demodulation circuit 4 ...... Error detection section 5 ...
......Integrator 6...Comparator agent Patent attorney Masaru Ogawa 5

Claims (1)

【特許請求の範囲】 1、ディスクよりEFM信号を再生して取り出すピック
アップ部と、該ピックアップ部より取り出したEFM信
号の周波数特性の補正を行うイコライザ回路と、該イコ
ライザ回路よりの出力信号を入力されそのピットクロッ
クを再生し復調する復調回路と、を有するCD信号の再
生装置において、 前記復調回路からの復調出力より信号エラーを検出する
エラー検出回路と、該検出回路により検出されたエラー
量が一定限度を超したら前記イコライザ回路の補正特性
を可変させてエラーを低減させる補正特性可変回路と、
を具備したことを特徴とするCD信号のエラーレート低
減回路。
[Claims] 1. A pickup unit that reproduces and extracts an EFM signal from a disk, an equalizer circuit that corrects the frequency characteristics of the EFM signal extracted from the pickup unit, and an output signal from the equalizer circuit that is input. A CD signal reproducing device having a demodulation circuit that reproduces and demodulates the pit clock, an error detection circuit that detects a signal error from a demodulated output from the demodulation circuit, and an error amount detected by the detection circuit that is constant a correction characteristic variable circuit that changes the correction characteristic of the equalizer circuit to reduce the error when the limit is exceeded;
A CD signal error rate reduction circuit characterized by comprising:
JP32397787A 1987-12-23 1987-12-23 Error rate reducing circuit for cd signal Pending JPH01166377A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32397787A JPH01166377A (en) 1987-12-23 1987-12-23 Error rate reducing circuit for cd signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32397787A JPH01166377A (en) 1987-12-23 1987-12-23 Error rate reducing circuit for cd signal

Publications (1)

Publication Number Publication Date
JPH01166377A true JPH01166377A (en) 1989-06-30

Family

ID=18160740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32397787A Pending JPH01166377A (en) 1987-12-23 1987-12-23 Error rate reducing circuit for cd signal

Country Status (1)

Country Link
JP (1) JPH01166377A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008122833A (en) * 2006-11-15 2008-05-29 Canon Inc Cleaning device and image forming apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008122833A (en) * 2006-11-15 2008-05-29 Canon Inc Cleaning device and image forming apparatus

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