JPH01166137A - Ic testing device - Google Patents

Abstract

PURPOSE:To execute a test at speed higher than the highest action speed of fail memories by executing repeatedly the writing of defective data, etc., of a tested IC memory to an N fail memories in turn and reading simultaneously with N pieces of them. CONSTITUTION:Signals whose periods are four times as much as the basic period of the output of a timing generator 1 and whose phases are successively dislocated by one period are generated by a control signal generating circuit 4 and supplied to a write enable generating circuit 10 and write enable signals are supplied to corresponding memory circuits 91-94 for storing the defective data. A pattern generating circuit 3 generates a pattern whose data changes at basic period and supplies it to a tested IC memory 5. The output of the tested IC memory 5 is compared with the output of a comparison pattern generator 2 by a comparator 6 and its output is successively supplied to the memory circuits 91-94 for storing the defective data. On the other hand, the reading out of the memory circuits 91-94 for storing the defective data is executed all simultaneously with the four pieces and their outputs are composed and outputted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an IC testing device such as an IC memory, and particularly relates to an IC testing device suitable for writing defective data in a short time.
Regarding C test equipment.

[Conventional technology]

As described in Japanese Unexamined Patent Application Publication No. 56-73363, when a failure occurs during testing of an IC under test such as an IC memory, the conventional device uses an address signal 9 expected value pattern given to the IC under test, Sequential memory was supposed to be used to store defective data in sequence.

[Problem that the invention seeks to solve]

The above conventional technology does not take into account the maximum operating speed of the sequential memory that sequentially stores defective data, etc., and if the maximum operating speed of the IC memory under test exceeds the maximum operating speed of the sequential memory, the sequential There was a problem in that it was not possible to test the IC memory under test at its maximum operating speed because it was not possible to write to the memory.

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to perform a test at a speed higher than the maximum operating speed of a fail memory that stores invalid data, etc. of an IC memory under test.

[Means for solving problems]

The above object is achieved by using N fail memories, repeatedly writing defective data, etc. to the N memories in order, and reading from the N fail memories simultaneously.

[For production]

The writing of defective data, etc. to the N fail memories is repeated in order from 1 to N by a control circuit that operates in synchronization with the test cycle using a basic clock, and the defective data storage address in the fail memories is written to the IC under test. The address supplied to the memory is changed from 1 to N using the above control circuit.
It is supplied repeatedly in the order up to.

On the other hand, reading from a fail memory is performed by ORing the outputs of N fail memories using a logic circuit and accessing N fail memories simultaneously.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

The pattern generator 3 and expected value pattern generator 2 shown in FIG. 1 are driven by a reference clock from the timing generator 1, and each generates data at each basic period determined by the reference clock. Divide the basic period by the number of memory circuits for storing defective data, that is, in this example, divide it into 4 parts, and in each 1/4 part, write the address under test of the output of the pattern generator 2 one by one into the registers 10□ to 104. Take it out. Therefore, the selection signal generation circuit 4 generates a signal whose period is four times the basic period of the output of the timing generator 1 and whose phase is sequentially shifted by one period, and the address holding register 7□
~74. Defective data holding registers 8□ to 84. It is supplied to the write enable generator 10.

For example, with respect to the reference clock of the timing generator 1 shown in A in FIG. 2, a corresponding control signal whose fundamental period is divided into four is generated by the control signal generation circuit 4 in FIG. 1 as shown in CLI to CL2 in FIG. do. This control signal is applied to the lock inputs of registers 71 to 74, respectively, and the outputs of the pattern generators 3 are respectively connected to the data inputs of these registers.The six pattern generators 3 are shown in FIG. 2B. This generates a pattern in which the data changes in the basic cycle, and this is done by register 7 once in the basic cycle.
The signals are sequentially supplied to □ to 74 and the IC memory under test. Therefore, registers 71-7. As shown in FIG. 2 81-S4, the outputs are data P1-P4 whose phase is sequentially shifted by one period at a period four times the basic period. This is applied to the address input of the memory element for storing bad data.

On the other hand, the output of the IC memory under test generated by the output of the pattern generator 3 is compared with the output of the comparison pattern generator 2 by the comparator 6. The output of comparator 6 is registered in register 8.
Connected to data inputs □ to 84. Register 8□
CLI to CL4 shown in FIG. 2 generated by the control signal generation circuit 4 are respectively supplied to the clock inputs of 84 to 84, and the comparator output C
is set to 01 in FIG. 2 by registers 8□ to 84 shown in FIG.
A memory circuit 9.1 for storing defective data with outputs similar to the outputs of the registers 71 to 74 as shown in ~G4.
-94 are sequentially supplied. On the other hand, the write enable signal for the memory circuits 9□ to 94 for storing defective data is generated by the write enable generation circuit 1 which receives the signal from the control signal generation circuit 4.
Signals W1 to W4 shown in FIG. 2 are generated by o,
Each is supplied to a corresponding memory circuit. On the other hand, data is simultaneously read from four memory circuits 9□-94 for storing defective data, and the memory circuit outputs are combined by an OR circuit 11 and output as defective data.

By providing a plurality of memory circuits, four in this example, for storing defective data, etc., it is possible to test the IC memory under test, which operates at four times the speed of the memory circuit, at the highest cycle. Therefore, even if the maximum operating speed of the memory circuit that stores defective data and the like is somewhat slow, it is possible to test the IC at high speed.

〔Effect of the invention〕

Although four memory circuits are provided in the above example, more circuits can be provided. When N memory circuits are provided, it is possible to test up to an IC memory under test whose maximum cycle is N times faster than the circuit for storing defective data. Further, according to the present invention, even when the number of test cycles is very large, the test speed can be increased and the test time can be shortened, and ICs can be tested with high efficiency, resulting in an effect of improving efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing diagram of one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Timing generator, 2... Comparison pattern generator, 3... Pattern generator, 4... Control signal generation circuit. 5... IC memory under test, 6... Comparator, 7□~7
4...Address signal holding register, 8□~84...
- Registers for holding defective data, 91 to 94...Memory circuit for storing defective data, 11...OR circuit. 1st mouth

Claims (1)

[Claims] 1. N memory circuits, N address holding circuits connected to address inputs of the memory circuits, and N data holding circuits connected to write data inputs of the memory circuits; and a data holding circuit are connected to a common holding control circuit, the address holding circuit is further connected to an address output of a memory test pattern generator, the data holding circuit is connected to a test result output of a test circuit, and the N In a memory device consisting of a logic circuit that ORs data outputs of memory circuits, when writing to N memory circuits, the N memory circuits are sequentially written repeatedly, and when reading, N memory circuits are repeatedly written. An IC testing device characterized by reading out multiple memory circuits at the same time and taking an OR output.