JPH01165153A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01165153A
JPH01165153A JP62322920A JP32292087A JPH01165153A JP H01165153 A JPH01165153 A JP H01165153A JP 62322920 A JP62322920 A JP 62322920A JP 32292087 A JP32292087 A JP 32292087A JP H01165153 A JPH01165153 A JP H01165153A
Authority
JP
Japan
Prior art keywords
semiconductor
layer
etching
section
surface side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62322920A
Other languages
Japanese (ja)
Inventor
Fumikoto Hisamori
久森 文詞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP62322920A priority Critical patent/JPH01165153A/en
Publication of JPH01165153A publication Critical patent/JPH01165153A/en
Pending legal-status Critical Current

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To decrease mandays for thinning a semiconductor section by selectively etching an operating layer region in a semiconductor wafer polished up to specified thickness in fixed depth from the rear and forming a heat sink by filling an etched section with a plating metallic layer. CONSTITUTION:An ohmic electrode 2 is shaped on the surface side of an epitaxial wafer 1, and the wafer 1 is polished in thickness of 80mum from the rear side. An silicon oxide film 3 and the pattern 4 of a photo-resist are formed onto the whole surface of the rear side, and an exposed region in a semiconductor is etched in depth of 50mum. An ohmic metallic film 5 is shaped onto the rear, the photo-resist 4 is dissolved by an organic solvent and the metallic film 5 on surfaces except an etching surface is removed, and the metallic film 5 on the etching surface is brought to an ohmic state through heat treatment. The surface side is coated with an insulating film, and an etching section is filled with a plating Au layer 6. The insulating film on the surface side is gotten rid of, the etching of a semiconductor section is conducted to the surface side, the semiconductor section is isolated, and a semiconductor layer is cut at specified positions, thus isolating an element.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、動作層領域の一方の面にめっき金属層によ
るヒートシンクの形成されたプレーテッドヒートシンク
(Plated Heat 5ink ) (以下PH
8と記す)構造の半導体装置の製造方法に関するもので
ある。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a plated heat sink (hereinafter referred to as PH
The present invention relates to a method for manufacturing a semiconductor device having a structure (denoted as 8).

〔従来の技術〕[Conventional technology]

ガンダイオード、インノセットダイオード、高出力電界
効果トランジスタなどのパワーデバイスでは、熱の放散
をよくするため、半導体部分の薄層化とともに、一方の
面にめりき金属層によるヒートシンクを形成するPH8
構造が採られている。
In power devices such as Gunn diodes, Innoset diodes, and high-output field effect transistors, PH8 is used to improve heat dissipation by making the semiconductor part thinner and forming a heat sink with a plated metal layer on one side.
structure is adopted.

第2図は従来のPH8構造のガンダイオードの製造方法
の一例を示す。
FIG. 2 shows an example of a method for manufacturing a conventional Gunn diode having a PH8 structure.

(100)方向の面方位を持つ厚さ約350μmのGa
AsN型単結晶基板の表面(図では下側)に、エピタキ
シャル成長法により、不純物濃度7 X 10”crr
T 3、厚さ5μmのバッファ層、不純物濃度lXl0
  cm  、厚さ10μmの動作層、不純物濃度lX
10 α 、厚さ3μmのコンタクト層が連続的に成長
されているエピタキシャルウェハ1〔図(a)〕の表面
にA uGeNi等のオーミック金属膜5aを形成し、
電解めっき法により、金属膜5a上に熱伝導のよいAu
などのめっき金属層6aを50μmの厚さに形成する〔
図(b)〕エピタキシャルウェハlのガンダイオードの
動作に直接必要な部分はエピタキシャル層であって、基
板層部分はウニへのハンドリングのために必要な部分で
あるが、熱伝導が悪く、熱放散の妨げとなるので、下記
の方法で、基板層の大部分の層を除去する。
Approximately 350 μm thick Ga with (100) plane orientation
An impurity concentration of 7 x 10" crr is formed on the surface (lower side in the figure) of the AsN type single crystal substrate by epitaxial growth.
T 3, 5 μm thick buffer layer, impurity concentration lXl0
cm, 10 μm thick active layer, impurity concentration lX
An ohmic metal film 5a such as AuGeNi is formed on the surface of the epitaxial wafer 1 [Fig.
By electrolytic plating, Au with good thermal conductivity is deposited on the metal film 5a.
A plating metal layer 6a such as [
Figure (b)] The part of the epitaxial wafer l that is directly necessary for the operation of the Gunn diode is the epitaxial layer, and the substrate layer part is necessary for handling the sea urchin, but it has poor heat conduction and dissipates heat. Most of the substrate layers are removed using the method described below.

めっき金属層6a側を研磨用の重りにはりつけ、研磨法
により、裏側(基板層側)から半導体層が全面均一に3
0μmの厚さになるまで研磨する〔図(C)〕。
The plated metal layer 6a side is attached to a polishing weight, and the semiconductor layer is uniformly coated on the entire surface from the back side (substrate layer side) by a polishing method.
Polish until the thickness is 0 μm [Figure (C)].

次に、研磨側の面に径100μmのオーミック用電極2
aを形成し〔図(d)〕、この電極2aをマスクに半導
体層部分のエツチングを行ない、半導体層部分の分離を
行ない〔図(e)〕、めっき金属層6aを切断して素子
の分離を行なう〔図(f)〕。
Next, an ohmic electrode 2 with a diameter of 100 μm is placed on the polishing side surface.
A is formed [Figure (d)], and the semiconductor layer portion is etched using this electrode 2a as a mask to separate the semiconductor layer portion [Figure (e)], and the plated metal layer 6a is cut to separate the elements. [Figure (f)].

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の製造方法では、上記のように、半導体ウェハの動
作層の形成されている表面側にヒートシンクのめつき金
属層を形成した後、裏面からの機械的な研磨によって、
基板層の大部分を除去して、放熱をよくするための半導
体部分の薄層化を実現していたが、機械的な研磨による
30μmの均一な厚さの薄層化は、工数がかかるととも
に、技術的に難しく、歩留りが悪くて、コスト高の要因
となっていた。
In the conventional manufacturing method, as described above, after forming the plating metal layer of the heat sink on the front side of the semiconductor wafer where the active layer is formed, mechanical polishing is performed from the back side.
Most of the substrate layer was removed to make the semiconductor part thinner for better heat dissipation, but mechanically polishing the layer to a uniform thickness of 30 μm was time consuming and time consuming. , which was technically difficult and had low yields, contributing to high costs.

この発明は上記の問題を解消するためになされたもので
、半導体部分の薄層化に余シエ数がかからなく、歩留り
よく実現できる方法を提供することを目的とする。
The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method for thinning a semiconductor portion without requiring an additional number of layers and achieving a high yield.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の製造方法は、半導体部分の薄層化を加工精度の
高いエツチングで行なうもので、所定の厚さにまで研磨
した半導体ウェハの動作層領域に裏面から所定の深さに
達する選択エツチングを行ない、ヒートシンクをエツチ
ングされた部分にめっき金属層を充填して形成する方法
である。
The manufacturing method of the present invention thins the semiconductor portion by etching with high processing precision, and selectively etches the active layer region of a semiconductor wafer polished to a predetermined thickness to a predetermined depth from the back surface. In this method, a heat sink is formed by filling the etched portion with a plating metal layer.

〔発明の実施例〕[Embodiments of the invention]

第1図は本発明の一実施例を示す。 FIG. 1 shows an embodiment of the invention.

第2′図に示したものと同様に表面にエピタキシャル層
が成長されているエピタキシャルウエノS1の表面側に
オーミック電極2を形成する〔図(a)〕。
An ohmic electrode 2 is formed on the surface side of the epitaxial wafer S1 on which an epitaxial layer is grown, similar to that shown in FIG. 2' [FIG. 2(a)].

次に、ウェハ1の表面側を研磨用の重りにはシつけ、研
磨法により、裏側(図では下側から)から半導体層が全
面均一に80μmの厚さになるまで研磨する〔図(b)
〕。
Next, the front side of the wafer 1 is attached to a polishing weight, and the semiconductor layer is polished from the back side (from the bottom in the figure) until the semiconductor layer has a uniform thickness of 80 μm over the entire surface [Figure (b) )
].

次に、裏側の全面に、スパンター法などにより、酸化シ
リコン膜3を形成し、酸化シリコン膜3上にホトレジス
トのノぞターン4を形成する〔図(C)〕。
Next, a silicon oxide film 3 is formed on the entire back surface by a spunter method or the like, and a photoresist groove turn 4 is formed on the silicon oxide film 3 [FIG. (C)].

ホトレノスト4をマスクに酸化シリコン膜3のエツチン
グを行ない〔図(d) ] 、半導体の露出した領域を
硫酸−過酸化水素水:水=1−8:1のエツチング液に
より50μmの深さにエツチングを行なう〔図(e)〕
The silicon oxide film 3 is etched using the photorenost 4 as a mask [Figure (d)], and the exposed area of the semiconductor is etched to a depth of 50 μm with an etching solution of sulfuric acid-hydrogen peroxide:water = 1-8:1. [Figure (e)]
.

次に、真空蒸着法により、裏面にオーミック金属膜5を
形成し、ホトレジスト4を有機溶剤で溶解してエツチン
グ面以外の面の・金属膜5を除去し、熱処理によりエッ
チング面の金属膜5のオーミック化を行なう〔図(f)
〕。
Next, an ohmic metal film 5 is formed on the back surface by vacuum evaporation, the photoresist 4 is dissolved in an organic solvent to remove the metal film 5 on the surface other than the etched surface, and the metal film 5 on the etched surface is removed by heat treatment. Perform ohmic conversion [Figure (f)
].

次に、表側を絶縁膜でおおい、電解めっき法により、裏
側にAuめっきを行ない、エツチング部分をめっきAu
層6で充填する〔図(g)〕。
Next, the front side is covered with an insulating film, and the back side is plated with Au using an electrolytic plating method.
Fill with layer 6 [Figure (g)].

このとき裏面よりはみ出しためつき層6は、裏面を基準
に研磨法により除去する。
At this time, the sticking layer 6 protruding from the back surface is removed by a polishing method using the back surface as a reference.

次に、表側の絶縁膜を除去し、表側に対し、オーミック
電極2をマスクに、半導体部分のエツチングを行ない、
半導体部分を分離し、ダイヤモンドスクライプ法等によ
る所定の個所での半導体層の切断によって、素子の分離
を行なう〔図(h)〕。
Next, the insulating film on the front side is removed, and the semiconductor portion is etched on the front side using the ohmic electrode 2 as a mask.
The semiconductor portion is separated and the semiconductor layer is cut at predetermined locations using a diamond scribe method or the like to separate the elements [Figure (h)].

以上のとおシ、本発明によれば、半導体部分の薄層化は
、エツチングによるため、工数がかからなくなり、技術
的に易しく、歩留りがよくなる。
As described above, according to the present invention, since the semiconductor portion is thinned by etching, the number of man-hours is reduced, it is technically easy, and the yield is improved.

さらに、めっきAu層が必要な部分にのみ形成されるの
でAu材料の節減となる。
Furthermore, since the plated Au layer is formed only in the necessary areas, the amount of Au material can be saved.

なお、上記においてはガンダイオードの製造方法を例に
本発明を説明したが、他のPH8構造の半導体装置の製
造に適用できることは勿論である。
Although the present invention has been described above using the method of manufacturing a Gunn diode as an example, it is of course applicable to manufacturing other semiconductor devices having a PH8 structure.

〔発明の効果〕〔Effect of the invention〕

以上説明したとおり、本発明によれば、半導体部分の薄
層化が容易になシ、従来の方法に比べ、工数がかからな
くなるとともに歩留シが上シ、さらにM材料を節減でき
、コストダウンに連なる効果がある。
As explained above, according to the present invention, the thickness of the semiconductor part can be easily reduced, the number of man-hours is reduced and the yield is improved compared to the conventional method, and the M material can be reduced, resulting in cost. It has a similar effect to down.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す断面図、第2図は従来
のPH8構造のガンダイオードの製造方法の一例を示す
断面図である。 1・・・エピタキシャルウェハ、2・・・オーミック電
極、3・・・酸化シリコン膜、4・・・ホトレゾスト、
5・・・オーミック金属膜、6・・・めっきAu層なお
図中同一符号は同一または相当するものを示す。 特許出願人  新日本無線株式会社 第1図
FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing an example of a conventional method for manufacturing a Gunn diode having a PH8 structure. DESCRIPTION OF SYMBOLS 1... Epitaxial wafer, 2... Ohmic electrode, 3... Silicon oxide film, 4... Photoresist,
5... Ohmic metal film, 6... Plated Au layer The same reference numerals in the drawings indicate the same or equivalent parts. Patent applicant New Japan Radio Co., Ltd. Figure 1

Claims (1)

【特許請求の範囲】[Claims]  動作層領域の一方の面にめっき金属層によるヒートシ
ンク(放熱電極)の形成されたプレーテッドヒートシン
ク構造の半導体装置の製造方法において、半導体ウェハ
を機械的な研磨により所定の厚さにまで研磨した後裏面
から動作層領域に所定の深さに達する選択エッチングを
行なう工程と、前記工程でエッチングされた部分にめっ
き金属層を充填してヒートシンクを形成する工程とを備
えたことを特徴とする半導体装置の製造方法。
In a method for manufacturing a semiconductor device with a plated heat sink structure in which a heat sink (heat dissipation electrode) is formed by a plated metal layer on one side of an active layer region, after a semiconductor wafer is mechanically polished to a predetermined thickness. A semiconductor device comprising the steps of selectively etching an active layer region from the back surface to a predetermined depth, and filling the portion etched in the step with a plated metal layer to form a heat sink. manufacturing method.
JP62322920A 1987-12-22 1987-12-22 Manufacture of semiconductor device Pending JPH01165153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62322920A JPH01165153A (en) 1987-12-22 1987-12-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62322920A JPH01165153A (en) 1987-12-22 1987-12-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01165153A true JPH01165153A (en) 1989-06-29

Family

ID=18149104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62322920A Pending JPH01165153A (en) 1987-12-22 1987-12-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01165153A (en)

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