JPH01162959A - Continuous data transfer system - Google Patents

Abstract

PURPOSE:To minimize the loss in terms of time when a parity error occurs by restarting the transfer of data at the time point when the parity error occurs in case this error is detected. CONSTITUTION:A parity error is detected after a control part 16 sets an initial address at an address register 18 and also sets initially a pointer 20 to start the continuous transfer of data. In this case, the count-up actions are inhibited to the register 18 and the pointer 20 and the next transfer of data is started at the time point when a parity error occurs. The transfer of data is newly started at said time point even though a parity error occurs during the continuous transfer of data. Therefore the double transfer is not required for those data that are transferred in a normal way. Thus the highly efficient transfer of data is ensured with the minimum time loss.

Description

[Detailed description of the invention] [! I! ! [Required] Regarding the continuous data transfer method that continuously transfers one data from an external storage device to multiple internal registers, the purpose is to minimize time loss and perform efficient data transfer even if a parity error occurs. , When a parity error is detected, the pointer that selects the internal register and the address register that specifies the address of the external storage device are prohibited from counting up, and data transfer is resumed from the point where the error occurred.

[Industrial Application Field] The present invention relates to a continuous data transfer device that continuously transfers data from an external storage device to a plurality of internal registers.

When data exceeding the number of data bus transfer customers is transferred by read access to an external storage device, multiple registers with a storage capacity equivalent to the data bus transfer capacity are installed, and these registers are divided into data bus transfer capacity units. Read data is transferred and stored continuously.

[Prior art] Figure 4 is a diagram showing an example of a conventional continuous data transfer method.
This is a clear diagram.

In FIG. 4, a plurality of internal registers 148 to 14n connected to the external storage device 12 via a 1-byte wide data path code 0 are provided in a device equipped with a processor 16a as a control circuit. Registers 14a-14
A pointer circuit 20a for selecting n and an address register 18 for specifying the address of the external storage device 12 via an address bus 28 are provided. External storage device 1
2 to internal register 14. Data transfer to a to 14n is started by the processor 16a initializing the pointer circuit 20a to select the first internal register 14a and inputting and outputting an initial address to the address register 18. Each time the data for 2 is transferred, the processor 16a counts up the pointer circuit 20a and the address register 18; selects the missing internal register and specifies the read address, and sequentially transfers the transferred data to the internal registers 14a to 14.
14n.

Furthermore, a parity error detection circuit 22a is provided to detect a parity error in the transfer data. If a parity error is detected by the parity error detection circuit 22a, the processor 16a temporarily stops the transfer operation, and the pointer circuit After resetting 20a and address register 18 to their initial values, the data transfer operation is executed again.

[Problems to be Solved by the Invention] However, in such a conventional continuous data transfer method, when a parity error occurs, it is necessary to initialize the pointer and read/write the initial address again to the address register at the same time. However, there is a problem in that this increases the burden on the firmware and causes a loss of time.

Furthermore, in the conventional method, since data transfer is retried from the beginning, data that has not caused an error is redundantly transferred again, resulting in a problem that efficient data transfer cannot be performed.

The present invention has been made in view of these conventional problems, and it is an object of the present invention to provide a continuous data transfer method that can minimize time loss and perform efficient data transfer even if a parity error occurs. purpose.

[Means for solving problems] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, a plurality of internal registers 14a to 14n having a capacity that is an integer multiple of the data bus width are connected to an external storage device 12 via a data path controller 0, and a control unit 16 controls the address of the external storage device 12. A parity error detection unit 22 continuously performs data transfer by counting up each of the address register 1B that specifies the address register 1B and the pointer 20 that selects the internal registers 14a to 14n for each data transfer, and further detects parity errors in the transferred data. is provided.

In the present invention, the control unit 16 has the address register 18
If a parity error is detected after setting the initial address and initializing the pointer 20 and starting continuous data transfer, counting up of the address register 18 and pointer 20 is prohibited, and the next data transfer is performed as an error. Restart from the point of occurrence.

Resuming the data transfer from the error occurrence point is performed by providing the control unit 16 with a reset signal generated by the reset generation unit 24 based on the parity error detection output.

Further, the number of attempts to resume data transfer based on the output of the error reset generation circuit 24 is counted by a retry counter 26, and when the count value of the retry counter 26 reaches a set value, the control unit 16 is notified of retry cancellation, etc. .

[Effect] Even if a parity error occurs during continuous data transfer,
Since new data transfer is restarted from the point where the error occurred, there is no need to redundantly transfer the data that was successfully transferred up to that point, minimizing time loss and reducing the power of address registers and pointers. Since it is only necessary to disable the C-kund add, there are fewer 9 firmware functions, and data can be transferred efficiently.

Furthermore, when the count value of the retry counter reaches a predetermined value,
Since resumption of data transfer is aborted, appropriate countermeasures can be taken against fatal errors such as hard errors.

[Embodiment 2] FIG. 2 is an embodiment +14 diagram showing an embodiment of the present invention.

In FIG. 2, 16a is a processor as a control unit, and a device equipped with the processor 16a has a data bus 1.
The external storage device 12 is connected via the address bus 28 and address bus 28 . Data pasco 0 from external storage device 12
are connected in parallel to a plurality of internal registers 148 to 1.4n, and each of the internal registers 14a to 14n has a storage capacity of the data bus width of data pathco 0, that is, 1 byte width.

Further, an address register 18 and a pointer circuit 20a are connected to the processor 16a, and the processor 16a stores the initial address in the address register 18 when reading the external storage device 12, and also stores the initial address in the address register 18 when accessing the external storage device 12.
0a is initialized to the selected state of the first internal register 14a. Furthermore, an external storage device 12 and a data bus 10
A parity error detection circuit 22a is provided to detect parity errors in the transferred data due to the transfer data.

In addition to such a configuration, in the present invention, the error detection output of the parity error detection circuit 22a is applied as a count-up prohibition signal to the address register 1B and the pointer circuit 20a.

That is, when no parity error is detected, the address register 18 and pointer circuit 20a are counted up each time data is transferred to any one of the internal registers 14a to 14n, and the next address and internal register are selected. Parity error detection circuit 22a
When a parity error is detected, the address register 18 and pointer circuit 20a are inhibited from counting up by receiving a count-up prohibition signal, and the point where the parity error occurs is maintained as it is.

Furthermore, in the present invention, the parity error detection circuit 22
An error reset generation circuit 24a is provided which inputs the error detection output of the error point a and generates a reset signal for resuming data transfer from the error point.
6, and the processor 16a, which receives the reset output from the error reset generating circuit 24.8, resumes data transfer from the error occurrence point, that is, performs a try operation.

The error reset generation circuit 24
The reset output of a is counted, and when it reaches a predetermined value of 8″1, an overflow output is generated and the processor 1
6a is notified of cancellation of retry, etc., to prevent a retry loop due to recurrence of a parity error in the same data transfer.

Next, the operation of the embodiment shown in FIG. 2 will be explained with reference to the operation time chart shown in FIG.

First, when the processor 16a executes, for example, a read operation on the external storage device 12, it first sets the initial address of the external storage device 12 in the address register 18 and the number of retries in the retry counter 26 as initial settings.

After completing this initial cell set, processor 1
6a, the processor 16a issues memory select and memory REET to the external storage device 12 through a control line (not shown), and at the same time uses the address bus 28 to write the first address data "X". 20'', data 1 read from the corresponding address is transferred to the internal register 1 selected by the pointer circuit 20a via the data path code 0.
4a and stored.

Once this initial data transfer is complete, processor 16a
outputs a count-up signal to each of the address register 18 and pointer circuit 20a, so the address value of the address register 18 changes from rX '20' J to '
X"21'", and the pointer value of the pointer circuit 20a is switched from the pointer value of the internal register 14a to the pointer value of the internal register 14b.

In this way, address register 18 and pointer circuit 20
When the count-up of a is completed, the processor 16 again performs memory selection and memory read on the external storage device 12, and the second read data is transferred and stored in the selected internal register 14b via the data pathco 0.

However, if the parity error detection circuit 22a detects a parity error in the data transfer of Q=J to the internal register 14b, then the parity error detection circuit 22a detects a parity error.
From a, a count-up prohibition signal as a parity error detection output or address register 18 and pointer circuit 20
The address (direct) of the address register 18 is held at "X"21'", and the pointer value of the pointer circuit 20a is held in the selected state of the register 14b.

At the same time, the error detection output of the parity error detection circuit 22a is also given to the error reset generation circuit 24a, and the error reset generation circuit 24 sends the error reset signal via the counter 26 to The error reset signal is output to the processor 16a, and the processor 16a, which receives this error reset signal, issues a memory REET] and a memory read to the external storage device 12. At this time, address register 18 and pointer circuit 2
0a is the address value [X'21
'J and the pointer value of internal register 14b, data 2 read from the same address rX'21' is transferred to internal register 14-b. If no parity error is detected in the try operation, the processor 16a outputs a count-up signal to the address register 18 and the pointer circuit 20a, and selects the next address value "X"22'" and the internal register 14C. The pointer value will be set.

Thereafter, similar processing is repeated until the transfer of the final data is completed.

On the other hand, even if the parity error detection circuit 22a detects a parity error and restarts data transfer from the point where the error occurred, the parity error will be detected again, resulting in a fatal error in which the try operation is repeated based on the detection of the parity error. If this occurs, the retry counter 26 counts 'ri' based on the reset output of the error reset generation circuit 24 or the number of plies.
When the count value of the retry counter 26 reaches a set value, an overflow signal is issued to the processor 16a.

Upon receiving this overflow signal from the retry counter 26, the processor 168 performs the same data transfer by setting the retry counter 26. It is determined that the retry operation has occurred, and the retry operation is canceled and the operator etc. is notified of this fact.

Therefore, it is possible to prevent a retry operation from becoming a loop due to a data transfer abnormality that permanently generates a parity error, thereby preventing other processing from being possible.

Although the above embodiment takes the read operation to the external storage device 12 as an example, the continuous write operation for occupying the external storage device 12 with the data stored in the internal registers 148 to 14rl of the number of tanks. Regarding data transfer, when a parity error is detected, data transfer to the external storage device 12 is restarted from the point where the error occurred.

[Effects of the Invention] As explained above, according to the present invention, when a parity error is detected, data transfer is restarted from the point where the error occurred, so there is no need to redundantly transfer data that has been successfully transferred up to that point. This eliminates the loss of time when a parity error occurs, and minimizes the time loss when a parity error occurs.

Furthermore, when a parity error occurs, resuming data transfer from the error occurrence point can be done by simply prohibiting the address register and pointer from counting up based on the parity error detection output, thereby reducing the burden on the control section.

Furthermore, in the event of a fatal error, a predetermined number of retries are detected and the controller is notified, thereby preventing other processing from becoming impossible due to a retry loop.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention; FIG. 2 is a configuration diagram of an embodiment of the present invention; FIG. 3 is an operation time chart of the present invention; and FIG. 4 is an explanatory diagram of a conventional system. In the figure, 10: Data path 12: External storage devices 14a to 14n: Internal register 16 2 Control unit 16a: Processor 18 Near address register 20: Pointer 20a: Pointer circuit 22: Parity error detection unit 22a: Parity error detection circuit 24: Error reset generation section 24a: Error reset generation circuit 26: Retry counter 28: Address bus

Claims (3)

[Claims] (1) External storage device (12) via data bus (10)
) is equipped with a plurality of internal registers (14a to 14n) having a capacity that is an integral multiple of the data bus width, and
6), an address register (18) that specifies the address of the external storage device (12) and the internal register (
14a to 14n) are incremented each time data is transferred to continuously transfer data, and further includes a parity error detection unit (22) that detects a parity error in the transferred data. When a parity error is detected by the parity error detection section (22), the system is equipped with the address register (22).
18) and pointer (20) are prohibited from counting up, and the next data transfer is restarted from the point where an error occurs. (2) Resume data transfer from the error occurrence point by an error reset generation unit (2) that generates a reset signal from the error detection output of the parity error detection unit (22).
4), and the control unit (16) restarts data transfer from the error occurrence point based on the reset output of the error reset generation unit (24). Continuous data transfer method. (3) A retry counter (26) is provided for counting the reset output of the error reset generation section (24), and when the count value of the retry counter (26) reaches a predetermined value, the control section (16) is given a retry counter. The continuous data transfer system according to claim 1, characterized in that notification of cancellation, etc. is provided.