JPH01162083A - Character broadcasting signal fetching circuit - Google Patents

Character broadcasting signal fetching circuit

Info

Publication number
JPH01162083A
JPH01162083A JP32082287A JP32082287A JPH01162083A JP H01162083 A JPH01162083 A JP H01162083A JP 32082287 A JP32082287 A JP 32082287A JP 32082287 A JP32082287 A JP 32082287A JP H01162083 A JPH01162083 A JP H01162083A
Authority
JP
Japan
Prior art keywords
memory
tuner
signal
data
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32082287A
Other languages
Japanese (ja)
Inventor
Yuji Minami
南 裕治
Kota Hashiguchi
橋口 耕太
Junji Maeda
前田 淳司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Original Assignee
Fujitsu General Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd filed Critical Fujitsu General Ltd
Priority to JP32082287A priority Critical patent/JPH01162083A/en
Publication of JPH01162083A publication Critical patent/JPH01162083A/en
Pending legal-status Critical Current

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  • Television Systems (AREA)

Abstract

PURPOSE:To simultaneously execute the memory of the program data of plural channels by providing the plural couples of a tuner and a signal sampling circuit, coupling a buffer memory to respectively temporarily execute the memory of a character broadcasting signal independently in each couple and coupling the buffer memory to a main memory. CONSTITUTION:The character broadcasting signal of a channel to be selected by a first tuner 1 is sampled by a first signal sampling circuit 2 from a vertical retrace line period and temporarily stored through a first error correcting circuit 3 to a first RAM4. The data of this RAM4 are transferred to a first main memory 13 in a processable block which is interval until the next vertical retrace line period. Next, during a time the data of the first memory 13 are displayed in a display part 12, a signal to be received by a second tuner 7 and to be sampled by a second signal sampling circuit 8 is successively shifted in a short time and stored in a second memory 14. Thus, the data to be stored in the first and second memories 13 and 14 are wholly displayed in the display part 12 immediately by a command from a microcomputer 6.

Description

【発明の詳細な説明】 「産業上の利用分野」 本発明は異なるチャンネルの文字放送のデータを同時に
メモリすることを可能とした文字放送信号取込み回路に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a teletext signal acquisition circuit that is capable of simultaneously storing teletext data of different channels in memory.

「従来の技術」 従来の文字放送信号取込み回路はTV放送のチューナと
文字放送信号抜取り回路を1組設け、このチューナによ
っであるチャンネルのある番組を選択して表示しながら
同一チャンネル内であれば異なる番組をすべてメモリす
ることができるようになっていた。
``Prior Art'' A conventional teletext signal acquisition circuit includes a TV broadcast tuner and a teletext signal extracting circuit, and uses this tuner to select and display a certain program on a certain channel, even if it is within the same channel. It was possible to store all different programs in memory.

「発明が解決しようとする問題点」 ところが、このような従来の回路ではあるチャンネルを
選択して表示しながら同時に他のチャンネルを選択して
メモリしたいと思ってもメモリすることができないので
、まずあるチャンネルの番組のデータのメモリが終了し
てから、他の目的のチャンネルに切換えてメモリしなけ
ればならない。
``Problems to be Solved by the Invention'' However, with such conventional circuits, even if you want to select and display a certain channel and simultaneously select and memorize another channel, you cannot memorize it. After the program data of a certain channel has been stored, it is necessary to switch to another desired channel and store the data.

そのため、他のチャンネルに切換えた後に1画面分のデ
ータをメモリするまでに時間がかかってしまい、また、
同時放送の裏番組はタイミングがずれるとデータのメモ
リができなくなるなどの問題があった。
Therefore, it takes time to memorize one screen's worth of data after switching to another channel, and
Simultaneous broadcasts of counter programs had problems such as data being unable to be stored in memory if the timing was off.

本発明は2組以上のチューナを具備することによって同
時に2つのチャンネルの番組データをメモリできるもの
を得ることを目的とするものである。
An object of the present invention is to provide a device that can simultaneously store program data of two channels by providing two or more sets of tuners.

r問題点を解決するための手段」 本発明は上述のような目的を達成するためになされたも
ので、チューナで受信した文字放送信号を、コントロー
ラの指令により信号抜取り回路で抜取り主メモリにメモ
リするとともに、表示部に目的の番組を表示するように
した回路において、前記チューナと信号抜取り回路を複
数組設け、かつそれぞれの組毎に文字放送信号を独立し
てそれぞれ一時的にメモリするバッファメモリを結合し
、これらのバッファメモリを、前記コントローラ内のバ
ス切換回路を介して前記主メモリに結合してなるもので
ある。
The present invention has been made to achieve the above-mentioned object, and it extracts teletext signals received by a tuner using a signal sampling circuit according to instructions from a controller, and stores them in a main memory. At the same time, in the circuit for displaying a target program on the display section, a plurality of sets of the tuner and the signal sampling circuit are provided, and a buffer memory for temporarily storing the teletext signal independently for each set. and these buffer memories are coupled to the main memory via a bus switching circuit within the controller.

「作用」 一方のチューナによりあるチャンネルの文字信号を受信
しているときには、そのチャンネルの文字信号データは
一旦バッファメモリにメモリされた後、主メモリにメモ
リされて表示部で表示される。この状態で、他方のチュ
ーナにより他のチャンネルの文字信号を受信すると、−
旦バッファメモリにメモリされた後、瞬時に移1動して
主メモリにメモリされる。したがって、チャンネルを他
のチャンネルに切換えると、主メモリ内のデータが即座
に表示部に表示される。
"Operation" When a character signal of a certain channel is being received by one tuner, the character signal data of that channel is temporarily stored in the buffer memory, then stored in the main memory and displayed on the display section. In this state, if the other tuner receives a character signal from another channel, -
After being stored in the buffer memory, the data is instantly moved and stored in the main memory. Therefore, when the channel is switched to another channel, the data in the main memory is immediately displayed on the display.

「実施例」 以下、本発明の一実施例を図面に基づき説明する。"Example" Hereinafter, one embodiment of the present invention will be described based on the drawings.

図において、(1)は第1のチューナで、この第1のチ
ューナ(1)は、第1の信号抜取り回路(2)、第1の
誤り訂正回路(3)を介してバッファメモリとしての第
1のRA M (4)とコントローラ(5)内のマイコ
ン(6)に結合されている。同様に、第2のチューナ(
7)は第2の信号抜取り回路(8)、第2の誤り訂正回
路(9)を介してバッファメモリとしての第2のRA 
M (10)と前記コントローラ(5)内のマイコン(
6)に結合されている。前記第1、第2のRA M (
4) (10)はバス切換回路(11)を介して前記マ
イコン(6)に結合されている。このマイコン(6)に
は表示部(12)、第1、第2の主メモリ(13)(1
4)が結合されている。
In the figure, (1) is a first tuner, and this first tuner (1) is connected to a buffer memory via a first signal extraction circuit (2) and a first error correction circuit (3). 1 RAM (4) and a microcomputer (6) in the controller (5). Similarly, the second tuner (
7) is connected to the second RA as a buffer memory via the second signal sampling circuit (8) and the second error correction circuit (9).
M (10) and the microcomputer (
6). The first and second RAM (
4) (10) is coupled to the microcomputer (6) via a bus switching circuit (11). This microcomputer (6) includes a display section (12), first and second main memories (13) (1
4) are combined.

以上のような構成における作用を説明する。The operation of the above configuration will be explained.

第1のチューナ(1)で選択したあるチャンネルの文字
放送信号が垂直帰線期間から第1の信号抜取り回路(2
)で抜取られ、第1の誤り訂正回路(3)を経て第1の
RA M (4)に−時的にメモリされる。
The teletext signal of a certain channel selected by the first tuner (1) is transmitted to the first signal sampling circuit (2) from the vertical blanking period.
) and is temporarily stored in the first RAM (4) via the first error correction circuit (3).

この第1のRA M (4)のデータはつぎの垂直帰線
期間までの間の処理可能区間に第1の主メモリ(13)
へ転送される。このようにして、あるチャンネルである
番組の文字放送データが主メモリ(13)にメモリされ
る。
The data in this first RAM (4) is stored in the first main memory (13) in a processable period up to the next vertical retrace period.
will be forwarded to. In this way, teletext data of a certain program on a certain channel is stored in the main memory (13).

ここで、マイコン(6)からの指令により第1の主メモ
リ(13)内のデータを表示部(12)に呼び出すと既
にメモリされているデータが即座に表示部(12)に表
示される。
Here, when the data in the first main memory (13) is called to the display section (12) by a command from the microcomputer (6), the data already stored in the memory is immediately displayed on the display section (12).

つぎに、表示部(12)にて第1メモリ(13)のデー
タが表示されている時間中に、第2のチューナ(7)で
受信した第1のチューナ(1)とは異なる他のチャンネ
ルを受信してそれをメモリするには、第2の信号抜取り
回路(8)で抜取った文字放送信号を第2のRA M 
(10)に−時的にメモリする。この第2のRA M 
(10)にメモリされたデータは訂正動作期間後に割込
み信号がマイコン(6)からバス切換回路(11)を介
して第2のRA M (10)へ送られ、かつバス切換
回路(11)で第2のRA M (10)とマイコン(
6)とを結合するバスに切換えられて、第2のRA M
 (10)のデータは第2のメモリ(14)へ移送され
てメモリされる。同様にして第2のチューナ(7)で受
信され第2の信号抜取り回路(8)で抜取られた信号が
順次短時間で移送されて第2のメモリ(14)へメモリ
される。このようにして第1、第2のメモリ(13) 
(14)にメモリされたデータは、マイコン(6)から
の指令によりすべて即座に表示部(12)に表示される
Next, during the time when the data in the first memory (13) is displayed on the display section (12), the second tuner (7) receives data from another channel different from the first tuner (1). In order to receive and store it in memory, the teletext signal extracted by the second signal extraction circuit (8) is transferred to the second RAM
(10) - Temporarily memorize. This second RAM
After the correction operation period, the data stored in (10) is sent as an interrupt signal from the microcomputer (6) to the second RAM (10) via the bus switching circuit (11). Second RAM (10) and microcomputer (
6) and the second RAM
The data (10) is transferred to the second memory (14) and stored therein. Similarly, signals received by the second tuner (7) and extracted by the second signal extraction circuit (8) are sequentially transferred in a short time and stored in the second memory (14). In this way, the first and second memories (13)
All data stored in (14) are immediately displayed on the display section (12) according to instructions from the microcomputer (6).

「発明の効果」 本発明は上述のように構成したので、一方のチューナで
正規受信をしているとき、同一時間内に他方チューナで
裏チャンネルの文字放送信号をメモリでき、したがって
、2つのチャンネルの番組の文字放送がチャンネル切換
と同時に表示できる。
"Effects of the Invention" Since the present invention is configured as described above, when one tuner is performing regular reception, the teletext signal of the back channel can be memorized in the other tuner within the same time, so that the teletext signal of the back channel can be stored in the memory of the two channels. Teletext broadcasts of programs can be displayed at the same time as changing channels.

また1表示部が1つだけであり、2台の装置を設ける場
合に比し大巾に安価に提供できる。
In addition, since there is only one display section, it can be provided at a much lower cost than when two devices are provided.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明による文字放送信号取込み回路のブロック図
である。 (1)(7)・・・チューナ、 (2)(8)・・・信
号抜取り回路、(3)(9)・・・誤り訂正回路、 (
4)(10)・・・RAM、(5)・・・コントローラ
、(6)・・・マイコン、(11)・・・バス切換回路
、(12)・・・表示部、 (13)(14)・・・主
メモリ。 出願人  株式会社富士通ゼネラル
The figure is a block diagram of a teletext signal acquisition circuit according to the present invention. (1)(7)...Tuner, (2)(8)...Signal extraction circuit, (3)(9)...Error correction circuit, (
4)(10)...RAM, (5)...Controller, (6)...Microcomputer, (11)...Bus switching circuit, (12)...Display section, (13)(14) )...Main memory. Applicant Fujitsu General Ltd.

Claims (2)

【特許請求の範囲】[Claims] (1)チューナで受信した文字放送信号を、コントロー
ラの指令により信号抜取り回路で抜取り主メモリにメモ
リするとともに、表示部に目的の番組を表示するように
した回路において、前記チューナと信号抜取り回路を複
数組設け、かつそれぞれの組毎に文字放送信号を独立し
てそれぞれ一時的にメモリするバッファメモリを結合し
、これらのバッファメモリを、前記コントローラ内のバ
ス切換回路を介して前記主メモリに結合してなることを
特徴とする文字放送信号取込み回路。
(1) In a circuit that extracts a teletext signal received by a tuner by a signal sampling circuit according to a command from a controller, stores it in the main memory, and displays the desired program on a display section, the tuner and the signal sampling circuit are connected to each other. A plurality of sets are provided, and buffer memories for temporarily storing teletext signals independently for each set are coupled, and these buffer memories are coupled to the main memory via a bus switching circuit in the controller. A teletext signal acquisition circuit characterized by:
(2)チューナと信号抜取り回路を2組設けてなる特許
請求の範囲第1項記載の文字放送信号取込み回路。
(2) The teletext signal acquisition circuit according to claim 1, which comprises two sets of tuners and signal extraction circuits.
JP32082287A 1987-12-18 1987-12-18 Character broadcasting signal fetching circuit Pending JPH01162083A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32082287A JPH01162083A (en) 1987-12-18 1987-12-18 Character broadcasting signal fetching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32082287A JPH01162083A (en) 1987-12-18 1987-12-18 Character broadcasting signal fetching circuit

Publications (1)

Publication Number Publication Date
JPH01162083A true JPH01162083A (en) 1989-06-26

Family

ID=18125621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32082287A Pending JPH01162083A (en) 1987-12-18 1987-12-18 Character broadcasting signal fetching circuit

Country Status (1)

Country Link
JP (1) JPH01162083A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5477521A (en) * 1977-12-02 1979-06-21 Matsushita Electric Ind Co Ltd Television picture receiver
JPS62166674A (en) * 1986-01-17 1987-07-23 Sharp Corp Character broadcast receiver

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5477521A (en) * 1977-12-02 1979-06-21 Matsushita Electric Ind Co Ltd Television picture receiver
JPS62166674A (en) * 1986-01-17 1987-07-23 Sharp Corp Character broadcast receiver

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