JPH01160710U - - Google Patents
Info
- Publication number
- JPH01160710U JPH01160710U JP5658588U JP5658588U JPH01160710U JP H01160710 U JPH01160710 U JP H01160710U JP 5658588 U JP5658588 U JP 5658588U JP 5658588 U JP5658588 U JP 5658588U JP H01160710 U JPH01160710 U JP H01160710U
- Authority
- JP
- Japan
- Prior art keywords
- fet
- resistor
- capacitor
- source
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 4
- 230000003321 amplification Effects 0.000 claims 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Amplifiers (AREA)
Description
第１図及び第２図はこの考案によるＦＥＴ増幅
回路の一実施例を示す回路構成図、第３図は第２
図のＦＥＴ増幅回路を構成しているＦＥＴ素子の
等価回路図、第４図はＦＥＴ増幅回路の入出力位
相差特性図、第５図は従来のＦＥＴ増幅回路を示
す回路構成図である。
４，２４…ＦＥＴ、１４…抵抗、１５…コンデ
ンサ。
1 and 2 are circuit configuration diagrams showing one embodiment of the FET amplifier circuit according to this invention, and FIG.
FIG. 4 is an equivalent circuit diagram of the FET elements constituting the FET amplifier circuit shown in the figure, FIG. 4 is an input/output phase difference characteristic diagram of the FET amplifier circuit, and FIG. 5 is a circuit configuration diagram showing a conventional FET amplifier circuit. 4, 24...FET, 14...Resistor, 15...Capacitor.
Claims (1)
いて、ゲート端子とソース端子との間に抵抗とコ
ンデンサとの直列回路を接続したことを特徴とす
るＦＥＴ増幅回路。 (2) ソース接地した増幅用ＦＥＴ素子を使用す
るＦＥＴ増幅回路において、前記ＦＥＴ素子に抵
抗とコンデンサが内蔵され、この抵抗とコンデン
サが前記ＦＥＴのゲートとソース間に直列接続し
たことを特徴とするＦＥＴ増幅回路。[Claims for Utility Model Registration] (1) An FET amplifier circuit whose source terminal is grounded, characterized in that a series circuit of a resistor and a capacitor is connected between the gate terminal and the source terminal. (2) A FET amplification circuit using a source-grounded amplification FET element, characterized in that the FET element has a built-in resistor and a capacitor, and the resistor and capacitor are connected in series between the gate and source of the FET. FET amplifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5658588U JPH01160710U (en) | 1988-04-28 | 1988-04-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5658588U JPH01160710U (en) | 1988-04-28 | 1988-04-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01160710U true JPH01160710U (en) | 1989-11-08 |
Family
ID=31282455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5658588U Pending JPH01160710U (en) | 1988-04-28 | 1988-04-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01160710U (en) |
-
1988
- 1988-04-28 JP JP5658588U patent/JPH01160710U/ja active Pending