JPH01159868A - Recording timing compensating circuit - Google Patents

Abstract

PURPOSE:To sufficiently secure the margin of a data discrimination by considering a data pattern, a cylinder position and a dispersion between heads and suppressing a peak shifting value. CONSTITUTION:A data pattern identifying circuit 1 outputs an identifying signal as to how the recording density of encoding data is changed, and on the other hand, a delaying circuit 2 outputs several kinds of the recording data of delaying quantities. Next, a recording compensating quantity selecting signal generating circuit 5 outputs a gate signal for selecting optimum data among the several kinds of the recording data of the delaying quantities prepared by the delaying circuit 2 according to the identifying signal, cylinder position information and head address information. A recording compensating quantity selecting circuit 3 opens only one corresponding gate by the gate signal, and gives the recording data to a current converting circuit 4. Thus, the data discrimination margin at the time of reproducing can be sufficiently secured without being influenced by the cylinder position and a head core shape.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a magnetic disk device, and in particular, the peak of the reproduced waveform when encoded data stored on a magnetic disk is reproduced is the same as that of the encoded data. The present invention relates to a recording timing compensation circuit that compensates during recording so as to match edges.

(Prior art) Fig. 2 is an explanatory diagram explaining the relationship between the recording current of the magnetic disk and the reproduction waveform, and the encoded data shown in Fig. 2 (b) is recorded using the reference clock shown in Fig. 2 (a). At this time, as shown in the figure (c), a recording current whose portion corresponding to "1" changes in accordance with the edge of the reference clock is applied, and the corresponding reproduction waveform is as shown in the figure (d). A positive peak is shown at the rising edge of the recording current, and a negative peak is shown at the falling edge of the recording current.

The reference clock is also used to discriminate encoded data from this reproduced waveform, but the positive peak point of the reproduced waveform is 6
It advances by one hour, and the negative peak point lags by 61 hours.

Originally, the peak point of the reproduced waveform should coincide with the polarity switching point of the recording current flowing through the magnetic head, but as the recording density increases and the interval between the polarity switching points of the recording current becomes narrower, the isolated reproduction waveform becomes more The peak point begins to shift relative to the recording position due to interference.

The reference clock is also used to discriminate encoded data from the reproduced waveform, but the larger the amount of shift of the peak point of the reproduced waveform with respect to the edge of this reference clock, the lower the margin for data discrimination, which increases the risk of data errors. cause.

Therefore, as shown in Figure 2(e), by delaying the rise of the recording current in advance and advancing its rise, the peak point of the reproduced waveform is made to coincide with the edge of the reference clock as shown in Figure 2(f). A recording timing compensation circuit is used.

FIG. 3 is a block diagram showing the configuration of a conventional recording timing compensation circuit disclosed in, for example, Japanese Unexamined Patent Publication No. 181118/1982. In the same figure, encoded data (NRZ
I) is applied to a data pattern identification circuit (1), which identifies how much peak shift the data pattern causes, that is, how the recording density changes. The delay circuit (2) receives encoded data and outputs data that has been variously delayed so that the rise time is delayed and the fall time is advanced in accordance with the recording timing compensation amount. Also, the recording compensation selection circuit (3) selects the delay circuit (2) based on the identification result of the data pattern identification circuit (1).
When data with an appropriate delay time is selected and outputted from among the recorded data generated, a current conversion circuit (4) converts this into a current and supplies it to a magnetic head (not shown).

The reproduced waveform peak shift amount not only changes according to the data pattern, but also changes depending on the recording density depending on the inner and outer circumferential position of the magnetic disk, that is, the cylinder position, or
Through experiments conducted by the inventors, the inventors have discovered that the isolated reproduction waveform varies due to variations in the shape of the head core (particularly the ball face length in a thin-film head).

(Problems to be Solved by the Invention) Conventional recording timing compensation circuits configured as described above determine the recording timing compensation amount based only on the pattern of encoded data, so it is difficult to find the optimal recording timing compensation circuit. There is a problem in that recording timing compensation is not performed and a sufficient data discrimination margin cannot be secured during reproduction.

This invention was made to solve the above problems, and it is possible to appropriately compensate recording timing without being affected by variations in cylinder position or head core shape, thereby improving data discrimination margin during playback. It is an object of the present invention to obtain a recording timing compensation circuit that can ensure sufficient recording timing.

[Means for solving problems]

A recording timing compensation circuit according to the present invention includes a data pattern identification circuit that identifies a pattern of encoded data, a delay circuit that generates a plurality of delayed data in which encoded data is variously delayed in accordance with an amount of recording timing compensation; It is equipped with a selection signal generation circuit that generates a signal for selecting an appropriate one from the above-mentioned delayed data based on the data pattern identification result, cylinder position information on the magnetic disk, and head address information of the magnetic head. be.

[Effect]

In this invention, recording timing is compensated by considering not only the data pattern of encoded data but also cylinder position information and head address, so data discrimination margin during playback is not affected by cylinder position or head core shape. can be secured sufficiently.

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the same reference numerals as in FIG. 3 indicate the same elements. And between the data pattern identification circuit (1) and the memory compensation amount selection circuit (3),
A compensation amount selection signal generation circuit that inputs a data pattern identification signal, cylinder position information, and head address information and generates a gate signal for selecting a recording compensation amount (
5) has been added.

The operation of this embodiment configured as described above will be explained.

First, the data pattern identification circuit (1) outputs an identification signal indicating how the recording density of encoded data changes, while the delay circuit (2) outputs recording data with several types of delay amounts.

Next, the recording compensation fk selection signal generation circuit (5) selects among the recording data of several types of delay amounts generated by the delay circuit (2) according to this identification signal, cylinder position information, and head address information. outputs a gate signal for selecting the optimal one.

Therefore, the recording compensation amount selection circuit (3) opens only one corresponding gate according to this gate signal and supplies recording data to the current conversion circuit (4).

Thus, according to this embodiment, the recording compensation amount selection signal generating circuit (5) variously combines data patterns, cylinder positions, and head addresses, and selects the optimum recording data corresponding to the combination.

(Effects of the Invention) As is clear from the above explanation, according to the present invention, the amount of peak shift is suppressed by taking into consideration data patterns, cylinder positions, and variations between heads. In a magnetic disk device with high recording density, a sufficient margin for data discrimination can be ensured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a time chart showing the relationship between recording current and reproduction waveform in a general magnetic disk device together with a reference clock, and FIG. 3 is a block diagram showing a conventional recording timing compensation circuit. (1)...Data pattern identification circuit, (2)...Delay circuit, (3)...Storage compensation amount selection circuit, (4)...Current conversion circuit, (5)...Recording compensation Amount selection signal generation circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] Recording is performed in a recording timing compensation circuit that compensates when recording the encoded data so that the edge of the encoded data recorded on the magnetic disk using a magnetic head matches the peak of the reproduced waveform when reproduced. a data pattern identification circuit that identifies patterns of encoded data; a delay circuit that generates a plurality of recording data by delaying the encoded data in accordance with various amounts of recording timing compensation; and a data pattern identification circuit that identifies patterns of encoded data; and a selection signal generation circuit that generates a selection signal for recording data of the delay circuit based on a data pattern identification result, cylinder position information on the magnetic disk, and head address information of the magnetic head. Recording timing compensation circuit.