JPH01158985U

JPH01158985U -

Info

Publication number: JPH01158985U
Application number: JP7109388U
Authority: JP
Priority date: 1988-05-31
Filing date: 1988-05-31
Publication date: 1989-11-02

Description

[Brief explanation of the drawing]

図面は実施例を示し、第１図は総体ブロツク構
成略図、第２図はＩＲＳのブロツク構成図、第３
図はゲートの要部信号図、第４図はクロツク選択
回路のブロツク構成図、第４Ａ図はデータセレク
タの機能図、第５図はクロツク選択動作のフロー
チヤート、第６図及び８図はクリア回路の要部信
号波形図、第７図はＰＣクリア回路の構成図、第
９図はＰＣクリア動作のフローチヤート、第１０
図は動作限定回路の構成図、第１１図は限定動作
の要部波形図、第１２図は限定動作のフローチヤ
ート、第１３図はレンジゲートとクロツクの信号
関係図。０……空中線、１……送受切換回路、２……受
信回路、３……ＩＲＳ、４……映像指示回路、５
……送信変調部、６……タイムベース回路、７，
２６……アンドゲート、８，１８，１９，２２，
２５……ナンドゲート、９……プログラムカウン
タ、１０……データセレクタ、１１……ＰＣクリ
ア回路、１２……クロツク発生器、１３……カウ
ンタ、１４……イニシヤルトリガ発生回路、１５
……レンジゲート発生回路、１６……動作限定回
路、１７，２１，２７……フリツプフロツプ、２
０，２３，２４……インバータ、Ａ……レーダ指
示機、３Ａ…比較器、３Ｂ……メモリー、３Ｃ…
…一致回路、ａ１……ＵＢＫゲート入力、ａ２…
…ＵＢＫゲート出力、ａ４……出力端子、ａ６…
…ＰＣクリアパルス、ａ７……イニシヤルトリガ
、ａ１０……正ゲート、ｂ２……出力クロツク、
ｂ４……ポインタ、ｂ７……Ｑ出力端子、ｃ１…
…受信信号、ｃ２……正ゲート、ｄ１……入力ビ
デオ信号、ｄ２……入力クロツク、ｄ７……負ゲ
ート、ｅ１……出力ビデオ信号、ｅ２……動作範
囲限定ゲート、ｅ７……Ｑ出力信号、ｆ７……負
パルス、ｇ７……パルス、ｉ７……反転イニシヤ
ルトリガ、ＣＫ……クロツク端子。 The drawings show an embodiment, and Fig. 1 is a schematic diagram of the overall block configuration, Fig. 2 is a block diagram of the IRS, and Fig. 3 is a schematic diagram of the overall block configuration.
The figure is a signal diagram of the main parts of the gate, Figure 4 is a block diagram of the clock selection circuit, Figure 4A is a functional diagram of the data selector, Figure 5 is a flowchart of the clock selection operation, and Figures 6 and 8 are clear. Main part signal waveform diagram of the circuit, Figure 7 is a configuration diagram of the PC clear circuit, Figure 9 is a flowchart of PC clear operation, Figure 10
11 is a diagram of the main part waveforms of the limiting operation, FIG. 12 is a flowchart of the limiting operation, and FIG. 13 is a diagram of the signal relationship between the range gate and the clock. 0... Antenna, 1... Transmission/reception switching circuit, 2... Receiving circuit, 3... IRS, 4... Video instruction circuit, 5
...Transmission modulation section, 6...Time base circuit, 7,
26...and gate, 8, 18, 19, 22,
25... NAND gate, 9... Program counter, 10... Data selector, 11... PC clear circuit, 12... Clock generator, 13... Counter, 14... Initial trigger generation circuit, 15
... Range gate generation circuit, 16 ... Operation limitation circuit, 17, 21, 27 ... Flip-flop, 2
0, 23, 24...Inverter, A...Radar indicator, 3A...Comparator, 3B...Memory, 3C...
... Matching circuit, a1... UBK gate input, a2...
...UBK gate output, a4...output terminal, a6...
...PC clear pulse, a7...Initial trigger, a10...Positive gate, b2...Output clock,
b4...pointer, b7...Q output terminal, c1...
... Reception signal, c2 ... Positive gate, d1 ... Input video signal, d2 ... Input clock, d7 ... Negative gate, e1 ... Output video signal, e2 ... Operating range limited gate, e7 ... Q output signal , f7...negative pulse, g7...pulse, i7...inverted initial trigger, CK...clock terminal.

Claims

[Claims for Utility Model Registration] 1. In a radar that processes a signal obtained by a detection signal in a memory and displays it in one display range selected from a plurality of display ranges, a. Storing in the memory; b) a plurality of unblanking means corresponding to the plurality of display ranges; c) based on one unblanking selected from the plurality of unblankings; clock selection means for comparing the obtained signal with each signal obtained by the plurality of clocks, selecting one clock from the plurality of clocks, and supplying the selected clock to the memory; A radar characterized by: 2 Utility Model Registration The radar according to claim 1, characterized in that interference removal processing is performed by the memory.