JPH01156468U - - Google Patents
Info
- Publication number
- JPH01156468U JPH01156468U JP5221588U JP5221588U JPH01156468U JP H01156468 U JPH01156468 U JP H01156468U JP 5221588 U JP5221588 U JP 5221588U JP 5221588 U JP5221588 U JP 5221588U JP H01156468 U JPH01156468 U JP H01156468U
- Authority
- JP
- Japan
- Prior art keywords
- attenuator
- digital data
- converter
- control means
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Description
第１図はこの考案の一実施例の構成を示すブロ
ツク図。第２図はこの考案の一実施例の作用の説
明に供するフローチヤート。
１，２，〜，ｎ……入力端子、１１，１２，〜
，１ｎ……バツフア回路、３１，３２〜，３ｎ…
…アツテネータ、４１，４２，〜，４ｎ……Ａ／
Ｄ変換器、５１，５２，〜，５ｎ……ＲＡＭ、６
……マイクロコンピユータ、７……Ｄ／Ａ変換器
、９１，９２，〜，９ｎ−１……切替リレー。
FIG. 1 is a block diagram showing the configuration of an embodiment of this invention. FIG. 2 is a flowchart for explaining the operation of one embodiment of this invention. 1, 2, ~, n... Input terminal, 1 1 , 1 2 , ~
, 1 n ... buffer circuit, 3 1 , 3 2 ~, 3 n ...
...Attenuator, 4 1 , 4 2 , ~, 4 n ...A/
D converter, 5 1 , 5 2 , ~, 5 n ... RAM, 6
. . . Microcomputer, 7 . . . D/A converter, 9 1 , 9 2 , ~, 9 n-1 . . . Switching relay.
Claims (1)
ンネルに対してアツテネータと、アツテネータか
らの出力信号をデジタルデータに変換するＡ／Ｄ
変換器と、Ａ／Ｄ変換器で変換されたデジタルデ
ータを記憶するメモリとを有するデジタルストレ
ージオシロスコープにおいて、 特定チヤンネルに供給された入力信号を全ての
入力チヤンネルに供給すると共に、各アツテネー
タの減衰率を異なる値に設定する第１の制御手段
と、所望のメモリに記憶のデジタルデータを読み
出す第２の制御手段とを備えたことを特徴とする
デジタルストレージオシロスコープ。[Claims for Utility Model Registration] An A/D that has multiple input channels, includes an attenuator for each input channel, and converts the output signal from the attenuator into digital data.
In a digital storage oscilloscope that has a converter and a memory that stores digital data converted by an A/D converter, the input signal supplied to a specific channel is supplied to all input channels, and the attenuation rate of each attenuator is 1. A digital storage oscilloscope comprising: a first control means for setting the values to different values; and a second control means for reading out digital data stored in a desired memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5221588U JPH01156468U (en) | 1988-04-20 | 1988-04-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5221588U JPH01156468U (en) | 1988-04-20 | 1988-04-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01156468U true JPH01156468U (en) | 1989-10-27 |
Family
ID=31278222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5221588U Pending JPH01156468U (en) | 1988-04-20 | 1988-04-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01156468U (en) |
-
1988
- 1988-04-20 JP JP5221588U patent/JPH01156468U/ja active Pending
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